Bin Meng d508a74a74 target/riscv: cpu: Add a new 'resetvec' property ... Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Backports 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511		2021-03-08 13:57:57 -05:00
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insn_trans	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: Enable vector extensions	2021-03-08 11:18:36 -05:00
cpu.h	target/riscv: cpu: Add a new 'resetvec' property	2021-03-08 13:57:57 -05:00
cpu_bits.h	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
cpu_helper.c	target/riscv: Support the v0.6 Hypervisor extension CRSs	2021-03-08 13:40:30 -05:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
fpu_helper.c	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
helper.h	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
internals.h	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
Makefile.objs	target/riscv: add vector configure instruction	2021-02-26 02:37:59 -05:00
op_helper.c	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
pmp.c	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
pmp.h	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
translate.c	target/riscv: Update the Hypervisor trap return/entry	2021-03-08 13:31:03 -05:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2021-03-08 12:18:39 -05:00