unicorn/qemu/target/arm
Peter Maydell fbbd582fb9
target/arm: Limit ID register assertions to TCG
In arm_cpu_realizefn() we make several assertions about the values of
guest ID registers:
* if the CPU provides AArch32 v7VE or better it must advertise the
ARM_DIV feature
* if the CPU provides AArch32 A-profile v6 or better it must
advertise the Jazelle feature

These are essentially consistency checks that our ID register
specifications in cpu.c didn't accidentally miss out a feature,
because increasingly the TCG emulation gates features on the values
in ID registers rather than using old-style checks of ARM_FEATURE_FOO
bits.

Unfortunately, these asserts can cause problems if we're running KVM,
because in that case we don't control the values of the ID registers
-- we read them from the host kernel. In particular, if the host
kernel is older than 4.15 then it doesn't expose the ID registers via
the KVM_GET_ONE_REG ioctl, and we set up dummy values for some
registers and leave the rest at zero. (See the comment in
target/arm/kvm64.c kvm_arm_get_host_cpu_features().) This set of
dummy values is not sufficient to pass our assertions, and so on
those kernels running an AArch32 guest on AArch64 will assert.

We could provide a more sophisticated set of dummy ID registers in
this case, but that still leaves the possibility of a host CPU which
reports bogus ID register values that would cause us to assert. It's
more robust to only do these ID register checks if we're using TCG,
as that is the only case where this is truly a QEMU code bug.

Backports commit 8f4821d77e465bc2ef77302d47640d5a43d92b30 from qemu
2019-08-08 19:44:16 -04:00
..
arm-powerctl.c arm: Clarify the logic of set_pc() 2019-02-03 17:55:30 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2018-03-02 00:20:11 -05:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 19:35:46 -04:00
cpu-qom.h target/arm: Add "-cpu max" support 2018-03-12 10:11:49 -04:00
cpu.c target/arm: Limit ID register assertions to TCG 2019-08-08 19:44:16 -04:00
cpu.h target/arm: Restrict semi-hosting to TCG 2019-08-08 17:48:34 -04:00
cpu64.c target/arm: Use env_cpu, env_archcpu 2019-06-12 11:34:08 -04:00
crypto_helper.c target/arm/cpu and crypto_helper: Correct bad merge and adjust to qemu code style 2018-03-12 11:57:24 -04:00
debug_helper.c target/arm: Move debug routines to debug_helper.c 2019-08-08 17:46:56 -04:00
helper-a64.c target/arm: Use env_cpu, env_archcpu 2019-06-12 11:34:08 -04:00
helper-a64.h target/arm: check CF_PARALLEL instead of parallel_cpus 2019-05-04 22:44:32 -04:00
helper-sve.h target/arm: Rewrite vector gather first-fault loads 2018-10-08 14:15:15 -04:00
helper.c target/arm: Add missing break statement for Hypervisor Trap Exception 2019-08-08 19:43:01 -04:00
helper.h target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs 2019-05-16 16:43:02 -04:00
internals.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
iwmmxt_helper.c target/arm: Untabify iwmmxt_helper.c 2018-08-25 04:33:44 -04:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
m_helper.c target/arm: NS BusFault on vector table fetch escalates to NS HardFault 2019-08-08 19:32:53 -04:00
Makefile.objs target/arm/helper: Move M profile routines to m_helper.c 2019-08-08 18:04:08 -04:00
neon_helper.c target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs 2019-05-16 16:43:02 -04:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c target/arm: Move debug routines to debug_helper.c 2019-08-08 17:46:56 -04:00
pauth_helper.c target/arm: Fix output of PAuth Auth 2019-06-13 16:17:00 -04:00
psci.c fix WFI/WFE length in syndrome register 2018-03-05 11:21:51 -05:00
sve.decode target/arm: Sychronize with qemu 2019-04-18 04:49:11 -04:00
sve_helper.c tcg: Use tlb_fill probe from tlb_vaddr_to_host 2019-05-16 18:27:03 -04:00
tlb_helper.c target/arm: Move TLB related routines to tlb_helper.c 2019-08-08 15:24:26 -04:00
translate-a64.c target/arm: Move vfp_expand_imm() to translate.[ch] 2019-06-25 18:17:49 -05:00
translate-a64.h target/arm: Move vfp_expand_imm() to translate.[ch] 2019-06-25 18:17:49 -05:00
translate-sve.c tcg: Specify optional vector requirements with a list 2019-05-16 15:05:02 -04:00
translate-vfp.inc.c target/arm: Correct VMOV_imm_dp handling of short vectors 2019-08-08 18:08:55 -04:00
translate.c target/arm: Execute Thumb instructions when their condbits are 0xf 2019-08-08 18:07:57 -04:00
translate.h target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d 2019-06-25 18:45:53 -05:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
unicorn_arm.c unicorn_arm: Treat registers as unsigned values in casts 2019-04-26 08:48:31 -04:00
vec_helper.c target/arm: Add helpers for FMLAL 2019-02-28 15:31:48 -05:00
vfp-uncond.decode target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree 2019-06-13 16:54:42 -04:00
vfp.decode target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm 2019-06-25 18:20:19 -05:00
vfp_helper.c target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR 2019-08-08 19:21:28 -04:00