unicorn/qemu/target/riscv/Makefile.objs

obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o pmp.o
obj-y += unicorn.o

DECODETREE = $(SRC_PATH)/scripts/decodetree.py

decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode

target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
	$(call quiet-command, \
	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
	  "GEN", $(TARGET_DIR)$@)

target/riscv/decode_insn16.inc.c: \
  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
	$(call quiet-command, \
	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
	  "GEN", $(TARGET_DIR)$@)

target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
	target/riscv/decode_insn16.inc.c
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality. 2019-03-08 18:06:28 +00:00			`obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o pmp.o`
			`obj-y += unicorn.o`
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu 2019-03-18 19:41:19 +00:00
			`DECODETREE = $(SRC_PATH)/scripts/decodetree.py`

target/riscv: Convert RV64I load/store insns to decodetree this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu 2019-03-18 20:02:12 +00:00			`decode32-y = $(SRC_PATH)/target/riscv/insn32.decode`
			`decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode`

			`target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)`
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu 2019-03-18 19:41:19 +00:00			`$(call quiet-command, \`
target/riscv: Convert RV64I load/store insns to decodetree this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu 2019-03-18 20:02:12 +00:00			`$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \`
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu 2019-03-18 19:41:19 +00:00			`"GEN", $(TARGET_DIR)$@)`

target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-19 08:45:40 +00:00			`target/riscv/decode_insn16.inc.c: \`
			`$(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)`
			`$(call quiet-command, \`
			`$(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \`
			`"GEN", $(TARGET_DIR)$@)`

			`target/riscv/translate.o: target/riscv/decode_insn32.inc.c \`
			`target/riscv/decode_insn16.inc.c`