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59 commits

Author SHA1 Message Date
Paolo Bonzini 5b02b2728a
target-i386: make xmm_regs 512-bit wide 
Right now, the AVX512 registers are split in many different fields:
xmm_regs for the low 128 bits of the first 16 registers, ymmh_regs
for the next 128 bits of the same first 16 registers, zmmh_regs
for the next 256 bits of the same first 16 registers, and finally
hi16_zmm_regs for the full 512 bits of the second 16 bit registers.

This makes it simple to move data in and out of the xsave region,
but would be a nightmare for a hypothetical TCG implementation and
leads to a proliferation of [XYZ]MM_[BWLSQD] macros. Instead,
this patch marshals data manually from the xsave region to a single
32x512-bit array, simplifying the macro jungle and clarifying which
bits are in which vmstate subsection.

The migration format is unaffected.

Backports commit b7711471f551aa4419f9d46a11121f48ced422da from qemu
 2018-02-12 12:38:43 -05:00
Andrew Dutcher d7735487f7 Use the qemu helpers to get/set the x86 eflags (#878) 2017-09-15 22:18:38 +07:00
bulaza 4b9efdc986 Adding INSN hook checks for x86 (#833) 
* adding INSN hook checking for x86

* tabs to spaces

* need to return bool not uc_err

* fixed conditional after switching to bool
 2017-05-14 00:16:17 +07:00
Samuel Groß 5385baba39 Implemented read and write access to the YMM registers (#819) 2017-05-05 09:02:58 +08:00
Nguyen Anh Quynh c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
Ahmed Samy 02e6c14e12 x86: add MSR API via reg API (#755) 
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...

So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
	Byte	Value		Size
	0	MSR ID		4
	4       MSR val		8
 2017-02-24 21:37:19 +08:00
Nguyen Anh Quynh 6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
Chris Eagle a03e908611 Fix initial state of segment registers (#751) 
* Remove glib from samples makefile

* changes to 16 bit segment registers needs to update segment base as well as segment selector

* change how x86 segment registers are set in 16-bit mode

* more appropriate solution to initial state of x86 segment registers in 16-bit mode

* remove commented lines
 2017-02-09 23:49:54 +08:00
Chris Eagle f05984961b Fix 16-bit address computations (#747) 
* Remove glib from samples makefile

* changes to 16 bit segment registers needs to update segment base as well as segment selector

* change how x86 segment registers are set in 16-bit mode
 2017-02-08 09:37:41 +08:00
xorstream 770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Chris Eagle fccbcfd4c2 revert to use of g_free to make future qemu integrations easier (#695) 
* revert to use of g_free to make future qemu integrations easier

* bracing
 2016-12-21 22:28:36 +08:00
Chris Eagle e46545f722 remove glib dependency by provide compatible replacements 2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh b7cdbe7a88 Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore 2016-10-07 09:57:07 +08:00
Ryan Hileman cb615fdba7 remove uc->cpus 2016-09-23 07:38:21 -07:00
Andrew Dutcher 0ef2b5fd71 New feature: registers can be bulk saved/restored in an opaque blob 2016-08-20 04:14:07 -07:00
Andrew Dutcher 4a8f52ae7f support xmm registers 2016-08-09 19:34:34 -07:00
Nguyen Anh Quynh cc6cbc5cf7 Merge branch 'memleak' into m2 2016-04-18 12:48:13 +08:00
Ryan Hileman acd88856e1 add batched reg access 2016-04-04 20:51:38 -07:00
Chris Eagle 4c4203cec8 fix x86 segment setup by updating cached segment registers on reg_write 2016-03-22 23:54:30 -07:00
Nguyen Anh Quynh 859111f8f5 x86: return immediately after handling FPSW/FPCW/FPTAG registers 2016-03-20 18:15:41 +08:00
Nguyen Anh Quynh fb1ebac000 Merge branch 'master' into m1 2016-03-09 15:13:42 +08:00
Hiroyuki UEKAWA c5888e5670 move macros in qemu/target-*/unicorn*.c to uc_priv.h 2016-03-02 12:43:02 +09:00
Hiroyuki UEKAWA 1cd3c3093b fix WRITE_BYTE_H 2016-03-02 10:51:50 +09:00
Nguyen Anh Quynh b69feb8d0b Merge branch 'master' into memleak2 2016-02-15 15:52:10 +08:00
Nguyen Anh Quynh 3bd7fa4bfe chmod -x qemu/target-i386/unicorn.c 2016-02-12 13:48:58 +08:00
Nguyen Anh Quynh 6478a24404 Merge branch 'gdt_idt' of https://github.com/cseagle/unicorn into cseagle-gdt_idt 2016-02-06 17:31:42 +08:00
Chris Eagle dec3615d12 ldtr and tr limit is 20 bits, not 16 bits 2016-02-04 19:26:47 -08:00
Chris Eagle b49358524f fix reg_read casting for x86 segment registers 2016-02-04 19:22:39 -08:00
Chris Eagle 4cb43be5bf fix reg_read casting for x86 segment registers 2016-02-04 19:20:59 -08:00
Chris Eagle 49b9f4f8da uc_x86_mmr type available in qemu/target-i386/unicorn.c 2016-02-04 19:09:41 -08:00
Chris Eagle c339ced218 file perms 2016-02-04 17:18:24 -08:00
Chris Eagle f3dc2522a0 read/write of x86 segment registers should modify selector field not base field 2016-02-04 17:17:40 -08:00
Chris Eagle 59f7bf3be7 file perms 2016-02-04 16:48:27 -08:00
Chris Eagle e59382e030 updated gdtr/idtr/ldtr/tr read/write code 2016-02-04 16:44:52 -08:00
Chris Eagle 9977054a15 add support for setting gdtr, idtr, ldtr, and tr programatically 2016-02-03 09:22:29 -08:00
Nguyen Anh Quynh 20b01a6933 fix merge conflict 2016-02-01 12:08:38 +08:00
Nguyen Anh Quynh 5a04bcb115 allow to change PC during callback. this solves issue #210 2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh 7695fb1578 x86: no need to reset env->invalid_error in x86_reg_reset() as we always do that in cpu_exec() 2016-01-12 01:01:11 +08:00
Nguyen Anh Quynh a0aa26d6ee c89 2016-01-10 23:34:36 +08:00
Spl3en bb375e4fa9 Reset correctly the register CR0 in protected mode by calling cpu_x86_update_cr0 instead of setting it manually. 2015-12-25 04:55:15 +01:00
Nguyen Anh Quynh 51323c9c17 x86: properly calculate EFLAGS when UC_HOOK_CODE is used. this should fix issue #246 2015-11-05 20:26:39 +08:00
Ryan Hileman 8c60d0dca5 allow setting x86 segment base to host-sized value 2015-10-23 00:15:08 -07:00
feliam b43f89566f Bugfix 2016-03-15 12:17:40 -03:00
Nguyen Anh Quynh 75e5fb466c x86: fix writing to UC_X86_REG_FPCW 2016-03-14 09:27:46 +08:00
feliam 23b3f651f9 Indentation 2016-03-10 07:45:36 -03:00
feliam 0a3799eada FPU control word and tags 2016-03-09 19:14:33 -03:00
feliam ff66a72d7b GDT/LDT/IDT/FPU access from python bingings 2016-03-09 18:07:38 -03:00
Nguyen Anh Quynh 84e3b5c897 cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98 2015-09-04 11:17:08 +08:00
Jonathon Reinhart 2c802a3e4b Merge remote-tracking branch 'upstream/master' into change-handle-based-api 
# Conflicts:
#	qemu/target-i386/unicorn.c
 2015-09-01 13:17:03 -04:00