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108 commits

Author SHA1 Message Date
Merry 29d38d7c22
Merge pull request #10 from lioncash/el-busto-ldst-exclusive 
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks
 2018-02-05 20:59:25 +00:00
Merry 82c4212ce3
Merge pull request #8 from lioncash/optimize 
Backport REV16 optimizations from qemu
 2018-02-05 20:58:58 +00:00
Lioncash 1e451b386a
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks 
Backports commit e14f0eb12f920fd96b9f79d15cedd437648e8667 from qemu
 2018-02-04 23:17:45 -05:00
Lioncash 5a37b8c28e
Backport optimizations to AArch32's REV16 handling 
Backports commit 68cedf733ae32363ccf54f0b52c8a424d5ec98ed from qemu
 2018-02-04 14:53:28 -05:00
Lioncash 4a8a92bad2
Backport optimizations to AArch64's REV16 handling 
Backports commits abb1066df313602ef0ca631126bd342d399d5359 and e4256c3cbf7eefebc0bc6e1f472c47c6dd20b996 from qemu.
 2018-02-04 14:45:39 -05:00
Lioncash 122d54e23e
Backport the SVE feature flag 
Backports commit 0d0a16c647650d476219a5e1313dec434f9fbebb in qemu to unicorn
 2018-02-02 08:52:15 -05:00
Lioncash 4fb2fbfacf
Backport the JAZELLE feature flag 
Backports commit c99a55d38dd5b5131f3fcbbaf41828a09ee62544 in qemu to unicorn
 2018-02-02 08:50:18 -05:00
Lioncash 84319130cd
Backport the M_SECURITY feature flag 
Backports relevant parts from commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f in qemu to unicorn
 2018-02-02 08:44:46 -05:00
Lioncash 20038fb801
Backport the PMU feature flag 
Backports the applicable code from commit 929e754d5a621cd53f30e69b766ccf381b58d124 to unicorn
 2018-02-02 08:28:27 -05:00
Lioncash 35100ce4e0
Backport the VBAR feature flag 
Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn
 2018-02-02 08:24:12 -05:00
Lioncash 291b5753eb
Backport the THUMB_DSP feature flag 
Backports commit 62b44f059a84d1ac580a653fc4110dfabaef6b83 in qemu to unicorn.
 2018-02-02 07:59:26 -05:00
Lioncash 438e2836e0
helper_a64: Fix CRC32's implementation 2018-01-29 09:24:36 -05:00
Lioncash d41b200fd4
A64: Add EOR3 and BCAX support 
Backported to unicorn from: https://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg05003.html
 2018-01-25 21:18:36 -05:00
MerryMage 4128f3b259 aarch64: Add FPCR and FPSR registers 2018-01-16 17:37:47 +00:00
MerryMage f90c819a33 aarch64: Add pstate pseudoregister 2018-01-16 17:37:17 +00:00
bunnei 73f4573535 aarch64: Add exception syndrome pseudo register. 2018-01-03 19:41:12 -05:00
Nguyen Anh Quynh d5f83a9c2e arm: cleanup for ARM_CPU 2017-12-21 09:43:33 +08:00
Nguyen Anh Quynh e67be36c88 arm: remove unused variable in arm_cpu_get_phys_page_debug() 2017-12-20 22:12:35 +08:00
misson20000 014ccfb94a Aarch64 add thread registers (#834) 
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
 2017-05-14 14:42:49 +07:00
Ryan Hileman ae6ea3b91d fix arm64 hang (fix #827) (#828) 2017-05-09 20:19:32 +08:00
zhangwm 4a62409949 arm64eb: arm64 big endian also using little endian instructions. (#816) 
* arm64eb: arm64 big endian also using little endian instructions.

* arm64: using another example that depends on endians.

example:
1. store a word: 0x12345678
2. load a byte:
   * little endian : 0x78
   * big endian    : 0x12
 2017-05-04 20:00:48 +08:00
Ryan Hileman 1b00d3f89a remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
Ryan Hileman 187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
zhangwm 2e973a13f0 arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh 513075e061 arm: fix an warning reported by GCC 2017-04-21 21:12:57 +08:00
Nguyen Anh Quynh e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
0xSeb 605400e10e determine correct Thumb/Thumb2 instruction size (16/32-bit) for code … (#796) 
* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook

* determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook
 2017-04-15 00:39:56 +08:00
bunnei 4eca426fb6 unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. (#791) 2017-03-31 10:21:45 +08:00
Nguyen Anh Quynh 094ca80092 fix conflicts 2017-03-30 12:23:24 +08:00
zhangwm ccdb0ff523 armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00
zhangwm d8fe34a2e8 armeb: Add support for ARM big endian. 2017-03-13 22:32:44 +08:00
Nguyen Anh Quynh c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
feliam 0150ca24b1 Add support for ARM application flags - APSR register (#776) 2017-03-09 22:28:03 +08:00
stevielavern b3a5eae81c uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) 
* uc_reg_read & uc_reg_write now support ARM64 Neon registers

* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
 2017-03-07 21:29:34 +08:00
Nguyen Anh Quynh 6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
Nguyen Anh Quynh 714cf2c609 arm: fix a warning 2017-02-23 20:32:09 +08:00
Parker Thompson 053ecd7bf4 Added ARM coproc registers (#684) 
* Added ARM coproc registers

* Added regression test for vfp
 2017-01-25 11:56:19 +08:00
xorstream e08d1bf7c6 Arm issue fix. (#738) 
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file

* Arm issue fix.
 2017-01-24 17:45:01 +08:00
xorstream 8e45102b43 Arm support ported. (#736) 
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file
 2017-01-23 23:30:57 +08:00
Nguyen Anh Quynh 206819bd98 cleanup after msvc port 2017-01-22 21:27:17 +08:00
xorstream 770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream 429bfca48e Fixes for MSVC native support to still work with GCC/GNU. 2017-01-21 01:07:10 +11:00
xorstream fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream 92392e0f57 Merge with current master. 2017-01-20 18:22:28 +11:00
Nguyen Anh Quynh b678512fc1 remove kvm stuffs 2017-01-20 01:03:59 +08:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh 287e047fdb delete sparc32_dma.h & arm-semi.c 2017-01-19 15:10:41 +08:00
Elton G 47150b6df3 reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) 
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton

* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write

* Fixed WRITE_DWORD macro

reg_write would zero out the high order bits when writing to 32 bit registers

e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
 2017-01-15 20:13:35 +08:00
Agustin Gianni a63a34bfbc Allow the client to write to CPSR 2017-01-05 00:00:15 +01:00
Chris Eagle fccbcfd4c2 revert to use of g_free to make future qemu integrations easier (#695) 
* revert to use of g_free to make future qemu integrations easier

* bracing
 2016-12-21 22:28:36 +08:00