16 commits

Author	SHA1	Message	Date
Alistair Francis	1e17cbc52c	target/riscv: Remove the hret instruction ... The hret instruction does not exist in the new spec versions, so remove it from QEMU. Backports commit 0736febb2d0e1bb503ca07091c16a16e78480366 from qemu	2020-03-22 01:44:55 -04:00
Alistair Francis	13a7b74827	target/riscv: Add hfence instructions ... Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu	2020-03-22 01:43:53 -04:00
Richard Henderson	d51505f6e9	target/riscv: Name the argument sets for all of insn32 formats ... Backports commit e761799796ac2211b9706753c459e117e7be58fa from qemu	2019-05-28 18:36:53 -04:00
Bastian Koppelmann	177726afb8	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists ... manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu	2019-03-19 05:17:54 -04:00
Bastian Koppelmann	cb7c94fbc4	target/riscv: Move gen_arith_imm() decoding into trans_* functions ... gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Backports commit 7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130 from qemu	2019-03-19 05:14:21 -04:00
Bastian Koppelmann	67164f2b29	target/riscv: Convert RV priv insns to decodetree ... Backports commit 4ba79c47a205b3af4b62b9b1b6090dee678a1069 from qemu	2019-03-19 04:40:24 -04:00
Bastian Koppelmann	71f2ed2959	target/riscv: Convert RV32D insns to decodetree ... Backports commit 97f8b49372d73aab4d172df4ea297d7f3ce4e02e from qemu	2019-03-18 16:51:20 -04:00
Bastian Koppelmann	9edaf2069e	target/riscv: Convert RV32F insns to decodetree ... Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu	2019-03-18 16:40:04 -04:00
Bastian Koppelmann	81013f9e2b	target/riscv: Convert RV32A insns to decodetree ... Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu	2019-03-18 16:25:50 -04:00
Bastian Koppelmann	3a5da0b939	target/riscv: Convert RVXM insns to decodetree ... Backports commit d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1 from qemu	2019-03-18 16:20:29 -04:00
Bastian Koppelmann	4ea449a809	target/riscv: Convert RVXI csr insns to decodetree ... Backports commit 771fbe156a2a2be964a4fbe6251339a5570a26c4 from qemu	2019-03-18 16:17:59 -04:00
Bastian Koppelmann	de580ee378	target/riscv: Convert RVXI fence insns to decodetree ... Backports commit 0c865e856a7e97d37c4dea4cf2ff875faa6e72ed from qemu	2019-03-18 16:09:21 -04:00
Bastian Koppelmann	11e2b9c410	target/riscv: Convert RVXI arithmetic insns to decodetree ... we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu	2019-03-18 16:04:49 -04:00
Bastian Koppelmann	65a415372b	target/riscv: Convert RV32I load/store insns to decodetree ... Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu	2019-03-18 15:59:43 -04:00
Bastian Koppelmann	55dc0038e8	target/riscv: Convert RVXI branch insns to decodetree ... Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu	2019-03-18 15:58:16 -04:00
Bastian Koppelmann	5e5b3e9ea9	target/riscv: Activate decodetree and implemnt LUI & AUIPC ... for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu	2019-03-18 15:54:17 -04:00