13 commits

Author	SHA1	Message	Date
Alistair Francis	95537388c5	target/riscv: Add the virtulisation mode ... Backports commit ef6bb7b62682badefdcb744831510aaa5971684f from qemu	2020-03-22 01:15:06 -04:00
Alistair Francis	fa04e7ea45	target/riscv: Rename the H irqs to VS irqs ... Backports commit 205377f8940898e4c53d1b44350a3d4934a2da72 from qemu	2020-03-22 01:09:04 -04:00
Alistair Francis	0198a09698	target/riscv: Add support for the new execption numbers ... The v0.5 Hypervisor spec add new execption numbers, let's add support for those. Backports commit ab67a1d07a4f6f1b4d577c5c47013273b9804551 from qemu	2020-03-22 01:07:23 -04:00
Alistair Francis	870603305d	target/riscv: Add the Hypervisor CSRs to CPUState ... Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Backports commit bd023ce33b85d73791b7bc78fd04a8115c60995e from qemu	2020-03-22 01:05:23 -04:00
Alistair Francis	2ed6459e98	target/riscv: Add the mcountinhibit CSR ... 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Backports commit 747a43e818dc36bd50ef98c2b11a7c31ceb810fa from qemu	2019-08-08 17:04:52 -04:00
Markus Armbruster	5e5197b136	Supply missing header guards ... Backports applicable parts of commit f91005e195e7e1485e60cb121731589960f1a3c9 from qemu	2019-06-12 10:59:10 -04:00
Alistair Francis	aca20201d4	target/riscv: Add the HGATP register masks ... Backports commit e06431108b0b1ef6ca76398d2b0b792ea24ae6bc from qemu	2019-05-28 19:19:00 -04:00
Alistair Francis	294297b646	target/riscv: Add the HSTATUS register masks ... Backports commit d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c from qemu	2019-05-28 19:18:28 -04:00
Alistair Francis	2e6d11ee47	target/riscv: Add Hypervisor CSR macros ... Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Backports commit 71f09a5bb48d0c51b87e70158407ec2db4a9c6e2 from qemu	2019-05-28 19:17:54 -04:00
Alistair Francis	c64f57c360	target/riscv: Add the MPV and MTL mstatus bits ... Backports commit 49aaa3e534f5422a56313bb93c1880e70fc1da7e from qemu	2019-05-28 19:15:33 -04:00
Alistair Francis	4b0355dcfc	target/riscv: Mark privilege level 2 as reserved ... Backports commit 356d74192a035c71a78a22d24812a6df6099ae40 from qemu	2019-05-28 19:12:10 -04:00
Jim Wilson	30ab335bb3	RISC-V: Fixes to CSR_* register macros. ... This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu	2019-03-19 23:39:49 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00