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18 commits

Author SHA1 Message Date
LIU Zhiwei bff31d8822 target/riscv: implementation-defined constant parameters 
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.

Backports 32931383270e2ca8209267ca99f23f3c5f780982 from qemu
 2021-02-26 02:23:28 -05:00
Alistair Francis 2b2f91f82c target/riscv: Add the lowRISC Ibex CPU 
The reset vector is set in the init function don't set it again in
realize.

Backports commit 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 from qemu
 2020-06-14 22:28:55 -04:00
Alistair Francis e35d56a146 target/riscv: Remove the deprecated CPUs 2020-06-14 22:15:16 -04:00
Corey Wharton bc097bd2ae target/riscv: Add a sifive-e34 cpu type 
The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.

Backports commit d784733bf1875c1ba355c69739518f24d56f1260 from qemu
 2020-04-30 21:08:10 -04:00
Alistair Francis dc7cbbe2c1 target/riscv: Remove user version information 
Remove the user version information. This was never used and never
publically exposed in a release of QEMU, so let's just remove it. In
future to manage versions we can extend the extension properties to
specify version.

Backports commit c9a73910c34a2147bcf6a3b5194d27abb19c2e54 from qemu
 2020-04-30 21:06:51 -04:00
Alistair Francis fa04e7ea45 target/riscv: Rename the H irqs to VS irqs 
Backports commit 205377f8940898e4c53d1b44350a3d4934a2da72 from qemu
 2020-03-22 01:09:04 -04:00
Alistair Francis 0198a09698 target/riscv: Add support for the new execption numbers 
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.

Backports commit ab67a1d07a4f6f1b4d577c5c47013273b9804551 from qemu
 2020-03-22 01:07:23 -04:00
Alex Bennée 14b401f0bf
target/riscv: rationalise softfloat includes 
We should avoid including the whole of softfloat headers in cpu.h and
explicitly include it only where we will be calling softfloat
functions. We can use the -types.h and -helpers.h in cpu.h for the few
bits that are global.

Backports commit 135b03cb9defbd080b8834b30e3d45bed00c6137 from qemu
 2019-11-18 21:17:03 -05:00
Joel Sing 14c6ed2cca
RISC-V: Clear load reservations on context switch and SC 
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.

Backports commit c13b169f1a3dd158d6c75727cdc388f95988db39 from qemu
 2019-08-08 17:15:45 -04:00
Alistair Francis e006204543
target/riscv: Set privledge spec 1.11.0 as default 
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.

Backports commit e3147506b02edcdd7c14ebb41a10fcc3027dcc5c from qemu
 2019-08-08 17:05:40 -04:00
Alistair Francis 9241c2c842
target/riscv: Restructure deprecatd CPUs 
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.

Backports commit c1fb65e63cfca4506a14b084afd0eca2dc464fe8 from qemu
 2019-08-08 17:01:22 -04:00
Michael Clark 6ab36ed89e
target/riscv: Implement riscv_cpu_unassigned_access 
This patch adds support for the riscv_cpu_unassigned_access call
and will raise a load or store access fault.

Backports commit cbf5827693addaff4e4d2102afedbf078a204eb2 from qemu
 2019-08-08 16:48:02 -04:00
Richard Henderson a672b89e3b
cpu: Introduce cpu_set_cpustate_pointers 
Consolidate some boilerplate from foo_cpu_initfn.

Backports commit 7506ed902eb97fe4e2a1dd16766c621d32ecc40d from qemu
 2019-06-12 12:27:16 -04:00
Alistair Francis ea2fee2d4d
target/riscv: Add a base 32 and 64 bit CPU 
At the same time deprecate the ISA string CPUs.

It is dobtful anyone specifies the CPUs, but we are keeping them for the
Spike machine (which is about to be depreated) so we may as well just
mark them as deprecated.

Backports commit 8903bf6e6d73d03b988b4a8197132de2ad681ff5 from qemu
 2019-05-28 19:11:12 -04:00
Richard Henderson 9c1212f627
target/riscv: Remove spaces from register names 
These extra spaces make the "-d op" dump look weird.

Backports commit 7f9188e210aff6522a960d9669a583a3a752ddc0 from qemu
 2019-05-28 19:08:50 -04:00
Richard Henderson e98c731550
target/riscv: Convert to CPUClass::tlb_fill 
Note that env->pc is removed from the qemu_log as that value is garbage.
The PC isn't recovered until cpu_restore_state, called from
cpu_loop_exit_restore, called from riscv_raise_exception.

Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
 2019-05-16 17:24:01 -04:00
Alistair Francis a9cc62cb23
target/riscv: Remove unused struct 
Backports commit 6b745d4fada5c73db44f596a62e29a5dbe3fc53f from qemu
 2019-03-19 23:58:31 -04:00
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target 
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
 2019-03-08 21:46:10 -05:00