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Peter Maydell 0d89bce217
target/arm: Execute Thumb instructions when their condbits are 0xf 
Thumb instructions in an IT block are set up to be conditionally
executed depending on a set of condition bits encoded into the IT
bits of the CPSR/XPSR. The architecture specifies that if the
condition bits are 0b1111 this means "always execute" (like 0b1110),
not "never execute"; we were treating it as "never execute". (See
the ConditionHolds() pseudocode in both the A-profile and M-profile
Arm ARM.)

This is a bit of an obscure corner case, because the only legal
way to get to an 0b1111 set of condbits is to do an exception
return which sets the XPSR/CPSR up that way. An IT instruction
which encodes a condition sequence that would include an 0b1111 is
UNPREDICTABLE, and for v8A the CONSTRAINED UNPREDICTABLE choices
for such an IT insn are to NOP, UNDEF, or treat 0b1111 like 0b1110.
Add a comment noting that we take the latter option.

Backports commit 5529de1e5512c05276825fa8b922147663fd6eac from qemu
2019-08-08 18:07:57 -04:00
..
accel Revert "cputlb: Filter flushes on already clean tlbs" 2019-06-30 19:21:20 -04:00
crypto crypto: Clean up includes 2018-02-19 00:47:40 -05:00
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs docs/devel/memory.txt: Document _with_attrs accessors 2018-10-04 04:46:26 -04:00
fpu qemu/fpu: Synchronize with Qemu 2019-03-09 18:27:31 -05:00
hw target/i386: Use env_cpu, env_archcpu 2019-06-12 11:46:35 -04:00
include Revert "cputlb: Filter flushes on already clean tlbs" 2019-06-30 19:21:20 -04:00
qapi qapi: Rewrite string-input-visitor's integer and list parsing 2018-12-18 04:57:25 -05:00
qobject qstring: Move qstring_from_substr()'s @end one to the right 2018-08-02 21:24:19 -04:00
qom cpu: Move icount_decr to CPUNegativeOffsetState 2019-06-13 15:34:28 -04:00
scripts decodetree: Fix comparison of Field 2019-06-13 16:17:56 -04:00
target target/arm: Execute Thumb instructions when their condbits are 0xf 2019-08-08 18:07:57 -04:00
tcg cpu: Move icount_decr to CPUNegativeOffsetState 2019-06-13 15:34:28 -04:00
util util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64 2019-05-09 17:43:27 -04:00
aarch64.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
aarch64eb.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
accel.c clean-up: removed duplicate #includes 2018-02-28 08:51:56 -05:00
arm.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
armeb.h target/arm: Declare some M-profile functions publicly 2019-08-08 15:37:01 -04:00
CODING_STYLE import 2015-08-21 15:04:50 +08:00
configure Deprecate Python 2 support 2019-08-08 17:16:26 -04:00
COPYING import 2015-08-21 15:04:50 +08:00
COPYING.LIB import 2015-08-21 15:04:50 +08:00
cpus.c Include qapi/error.h exactly where needed 2018-03-07 12:26:38 -05:00
exec.c exec.c: refactor function flatview_add_to_dispatch() 2019-03-11 17:00:46 -04:00
gen_all_header.sh arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
glib_compat.c target/arm/translate: Synchronize with Qemu 2019-04-27 10:13:01 -04:00
HACKING HACKING: document preference for g_new instead of g_malloc 2018-05-22 00:30:50 -04:00
header_gen.py target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
ioport.c hw: remove pio_addr_t 2018-02-24 02:43:16 -05:00
LICENSE import 2015-08-21 15:04:50 +08:00
m68k.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
Makefile Makefile: Rename targets for make recursion 2019-08-08 17:26:49 -04:00
Makefile.objs qapi: Move qapi-schema.json to qapi/, rename generated files 2018-03-09 11:35:11 -05:00
Makefile.target configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012] 2018-12-18 03:52:36 -05:00
memory.c cputlb: Synchronize with qemu 2019-04-26 15:48:45 -04:00
memory_ldst.inc.c exec: Fix MAP_RAM for cached access 2018-07-03 01:11:12 -04:00
memory_mapping.c include/qemu/osdep.h: Don't include qapi/error.h 2018-02-21 23:08:18 -05:00
mips.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
mips64.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
mips64el.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
mipsel.h target/mips: Refactor and fix INSERT.<B|H|W|D> instructions 2019-05-28 19:42:28 -04:00
powerpc.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
qemu-timer.c timer/cpus: fix some typos and update some comments 2018-02-25 23:21:57 -05:00
riscv32.h target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
riscv64.h target/riscv: Implement riscv_cpu_unassigned_access 2019-08-08 16:48:02 -04:00
rules.mak build-sys: silence make by default or V=0 2018-03-06 08:58:03 -05:00
sparc.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
sparc64.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00
unicorn_common.h unicorn_common: Fix unicorn memory functions failing 2018-09-03 10:40:14 -04:00
VERSION Open 4.1 development tree 2019-04-24 11:59:00 -04:00
vl.c Use cpu_create(type) instead of cpu_init(cpu_model) 2018-03-20 14:20:30 -04:00
vl.h import 2015-08-21 15:04:50 +08:00
x86_64.h tcg: Add support for vector compare select 2019-05-24 18:21:13 -04:00