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										insn_trans
									
								
							
						
					
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							target/riscv: vector single-width integer multiply instructions
						
					
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				2021-02-26 10:46:26 -05:00 | 
			
		
			
			
			
			
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								cpu-param.h
							
						
					
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							tcg: Split out target/arch/cpu-param.h
						
					
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				2019-06-10 19:35:46 -04:00 | 
			
		
			
			
			
			
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								cpu.c
							
						
					
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							target/riscv: implementation-defined constant parameters
						
					
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				2021-02-26 02:23:28 -05:00 | 
			
		
			
			
			
			
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								cpu.h
							
						
					
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							target/riscv: add vector configure instruction
						
					
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				2021-02-26 02:37:59 -05:00 | 
			
		
			
			
			
			
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								cpu_bits.h
							
						
					
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							target/riscv: support vector extension csr
						
					
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				2021-02-26 02:25:58 -05:00 | 
			
		
			
			
			
			
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								cpu_helper.c
							
						
					
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							target/riscv: Report errors validating 2nd-stage PTEs
						
					
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				2021-02-25 11:55:53 -05:00 | 
			
		
			
			
			
			
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								cpu_user.h
							
						
					
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							Supply missing header guards
						
					
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				2019-06-12 10:59:10 -04:00 | 
			
		
			
			
			
			
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								csr.c
							
						
					
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							target/riscv: support vector extension csr
						
					
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				2021-02-26 02:25:58 -05:00 | 
			
		
			
			
			
			
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								fpu_helper.c
							
						
					
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							target/riscv: rationalise softfloat includes
						
					
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				2019-11-18 21:17:03 -05:00 | 
			
		
			
			
			
			
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								helper.h
							
						
					
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							target/riscv: vector single-width integer multiply instructions
						
					
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				2021-02-26 10:46:26 -05:00 | 
			
		
			
			
			
			
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								insn16-32.decode
							
						
					
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							target/riscv: Split RVC32 and RVC64 insns into separate files
						
					
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				2019-05-28 19:00:23 -04:00 | 
			
		
			
			
			
			
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								insn16-64.decode
							
						
					
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							target/riscv: Add checks for several RVC reserved operands
						
					
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				2019-05-28 19:20:36 -04:00 | 
			
		
			
			
			
			
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								insn16.decode
							
						
					
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							target/riscv: Add checks for several RVC reserved operands
						
					
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				2019-05-28 19:20:36 -04:00 | 
			
		
			
			
			
			
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								insn32-64.decode
							
						
					
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							target/riscv: add vector amo operations
						
					
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				2021-02-26 09:47:32 -05:00 | 
			
		
			
			
			
			
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								insn32.decode
							
						
					
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							target/riscv: vector single-width integer multiply instructions
						
					
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				2021-02-26 10:46:26 -05:00 | 
			
		
			
			
			
			
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								instmap.h
							
						
					
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							Supply missing header guards
						
					
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				2019-06-12 10:59:10 -04:00 | 
			
		
			
			
			
			
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								internals.h
							
						
					
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							target/riscv: add vector amo operations
						
					
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				2021-02-26 09:47:32 -05:00 | 
			
		
			
			
			
			
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								Makefile.objs
							
						
					
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							target/riscv: add vector configure instruction
						
					
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				2021-02-26 02:37:59 -05:00 | 
			
		
			
			
			
			
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								op_helper.c
							
						
					
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							target/riscv: Implement checks for hfence
						
					
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				2021-02-25 12:03:57 -05:00 | 
			
		
			
			
			
			
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								pmp.c
							
						
					
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							RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off
						
					
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				2019-08-08 16:55:52 -04:00 | 
			
		
			
			
			
			
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								pmp.h
							
						
					
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							RISC-V: Check for the effective memory privilege mode during PMP checks
						
					
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				2019-08-08 16:52:57 -04:00 | 
			
		
			
			
			
			
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								translate.c
							
						
					
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							target/riscv: add vector stride load and store instructions
						
					
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				2021-02-26 02:55:14 -05:00 | 
			
		
			
			
			
			
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								unicorn.c
							
						
					
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							target/riscv: Add the virtulisation mode
						
					
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				2020-03-22 01:15:06 -04:00 | 
			
		
			
			
			
			
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								unicorn.h
							
						
					
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							target/riscv: Initial introduction of the RISC-V target
						
					
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				2019-03-08 21:46:10 -05:00 | 
			
		
			
			
			
			
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								vector_helper.c
							
						
					
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							target/riscv: vector single-width integer multiply instructions
						
					
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				2021-02-26 10:46:26 -05:00 |