Alistair Francis 5973588ac0 target/riscv: fpu_helper: Match function defs in HELPER macros ... Update the function definitions generated in helper.h to match the actual function implementations. Also remove all compile time XLEN checks when building. Backports 5b6c291b8db8effff625db321be232e0c4dcdb6c		2021-03-08 15:25:30 -05:00
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insn_trans	target/riscv: Split the Hypervisor execute load helpers	2021-03-08 15:14:47 -05:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2021-03-08 14:56:14 -05:00
cpu.c	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
cpu.h	target/riscv: Add a TYPE_RISCV_CPU_BASE CPU	2021-03-08 15:18:00 -05:00
cpu_bits.h	target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR	2021-03-08 15:16:50 -05:00
cpu_helper.c	target/riscv: Fix the bug of HLVX/HLV/HSV	2021-03-08 15:16:06 -05:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	target/riscv/csr.c : add space before the open parenthesis '('	2021-03-08 14:54:03 -05:00
fpu_helper.c	target/riscv: fpu_helper: Match function defs in HELPER macros	2021-03-08 15:25:30 -05:00
helper.h	target/riscv: fpu_helper: Match function defs in HELPER macros	2021-03-08 15:25:30 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
internals.h	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
Makefile.objs	target/riscv: add vector configure instruction	2021-02-26 02:37:59 -05:00
op_helper.c	target/riscv: Split the Hypervisor execute load helpers	2021-03-08 15:14:47 -05:00
pmp.c	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
pmp.h	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
translate.c	target/riscv: Remove the hyp load and store functions	2021-03-08 15:11:11 -05:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2021-03-08 12:18:39 -05:00