Anup Patel d47390ade4 target/riscv: Emulate TIME CSRs for privileged mode ... Currently, TIME CSRs are emulated only for user-only mode. This patch add TIME CSRs emulation for privileged mode. For privileged mode, the TIME CSRs will return value provided by rdtime callback which is registered by QEMU machine/platform emulation (i.e. CLINT emulation). If rdtime callback is not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu		2020-03-22 02:22:17 -04:00
..
insn_trans	target/riscv: Remove the hret instruction	2020-03-22 01:44:55 -04:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: Rename the H irqs to VS irqs	2020-03-22 01:09:04 -04:00
cpu.h	target/riscv: Emulate TIME CSRs for privileged mode	2020-03-22 02:22:17 -04:00
cpu_bits.h	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-03-22 02:18:02 -04:00
cpu_helper.c	target/riscv: Emulate TIME CSRs for privileged mode	2020-03-22 02:22:17 -04:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	target/riscv: Emulate TIME CSRs for privileged mode	2020-03-22 02:22:17 -04:00
fpu_helper.c	target/riscv: rationalise softfloat includes	2019-11-18 21:17:03 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: Remove the hret instruction	2020-03-22 01:44:55 -04:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
op_helper.c	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-03-22 02:18:02 -04:00
pmp.c	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-08-08 16:55:52 -04:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-08-08 16:52:57 -04:00
translate.c	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-03-22 02:18:02 -04:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00