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aecf7b05dc
Implement some corner cases of the behaviour of the NSACR register on ARMv8: * if EL3 is AArch64 then accessing the NSACR from Secure EL1 with AArch32 should trap to EL3 * if EL3 is not present or is AArch64 then reads from NS EL1 and NS EL2 return constant 0xc00 It would in theory be possible to implement all these with a single reginfo definition, but for clarity we use three separate definitions for the three cases and install the right one based on the CPU feature flags. Backports commit 2f027fc52d4b444a47cb05a9c96697372a6b57d2 from qemu |
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arm_ldst.h | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
cpu64.c | ||
crypto_helper.c | ||
helper-a64.c | ||
helper-a64.h | ||
helper.c | ||
helper.h | ||
internals.h | ||
iwmmxt_helper.c | ||
kvm-consts.h | ||
Makefile.objs | ||
neon_helper.c | ||
op_addsub.h | ||
op_helper.c | ||
psci.c | ||
translate-a64.c | ||
translate.c | ||
translate.h | ||
unicorn.h | ||
unicorn_aarch64.c | ||
unicorn_arm.c |