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unicorn/qemu/target/arm
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Peter Maydell 0718459fb3 target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64 
When a coprocessor instruction in an AArch32 guest traps to AArch32
Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields
which are simply copies of the Rt and Rt2 fields from the trapped
instruction. However, if the instruction is trapped from AArch32 to
an AArch64 higher exception level, the Rt and Rt2 fields in the
syndrome register (ESR_ELx) must be the AArch64 view of the register.
This makes a difference if the AArch32 guest was in a mode other than
User or System and it was using r13 or r14, or if it was in FIQ mode
and using r8-r14.

We don't know at translate time which AArch32 CPU mode we are in, so
we leave the values we generate in our prototype syndrome register
value at translate time as the raw Rt/Rt2 from the instruction, and
instead correct them to the AArch64 view when we find we need to take
an exception from AArch32 to AArch64 with one of these syndrome
values.

Fixes: https://bugs.launchpad.net/qemu/+bug/1879587

Backports commit a65dabf71a9f9b949d556b1b57fd72595df92398 from qemu
2021-02-25 23:50:18 -05:00
..
a32-uncond.decode target/arm: Convert Unallocated memory hint 2019-11-28 02:47:41 -05:00
a32.decode target/arm: Convert SVC 2019-11-28 02:46:55 -05:00
arm-powerctl.c arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() 2020-01-07 18:10:29 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2018-03-02 00:20:11 -05:00
cpu-param.h target/arm: Don't use a TLB for ARMMMUIdx_Stage2 2020-05-07 08:40:06 -04:00
cpu-qom.h target/arm: Make cpu_register() available for other files 2020-04-30 21:38:42 -04:00
cpu.c target/arm: Create tagged ram when MTE is enabled 2021-02-25 22:51:23 -05:00
cpu.h target/arm: Create tagged ram when MTE is enabled 2021-02-25 22:51:23 -05:00
cpu64.c target/arm: Enable MTE 2021-02-25 23:00:27 -05:00
crypto_helper.c target/arm: Split helper_crypto_sm3tt 2020-06-14 23:24:21 -04:00
debug_helper.c target/arm: Stop assuming DBGDIDR always exists 2020-03-21 18:26:24 -04:00
helper-a64.c target/arm: Simplify DC_ZVA 2021-02-25 15:55:46 -05:00
helper-a64.h target/arm: Add helper_mte_check_zva 2021-02-25 17:17:54 -05:00
helper-sve.h target/arm: Add mte helpers for sve scatter/gather memory ops 2021-02-25 22:34:24 -05:00
helper.c target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64 2021-02-25 23:50:18 -05:00
helper.h target/arm: Implement LDG, STG, ST2G instructions 2021-02-25 15:08:44 -05:00
internals.h target/arm: Always pass cacheattr to get_phys_addr 2021-02-25 22:46:00 -05:00
iwmmxt_helper.c target/arm: Untabify iwmmxt_helper.c 2018-08-25 04:33:44 -04:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
m_helper.c target/arm: Always pass cacheattr to get_phys_addr 2021-02-25 22:46:00 -05:00
Makefile.objs target/arm: Implement the IRG instruction 2021-02-25 14:36:11 -05:00
mte_helper.c target/arm: Add allocation tag storage for system mode 2021-02-25 22:58:56 -05:00
neon-dp.decode target/arm: Convert Neon VTRN to decodetree 2021-02-25 13:12:28 -05:00
neon-ls.decode target/arm: Convert Neon 'load/store single structure' to decodetree 2020-05-07 09:32:17 -04:00
neon-shared.decode target/arm: Convert VFM[AS]L (scalar) to decodetree 2020-05-07 09:20:35 -04:00
neon_helper.c target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree 2020-05-15 23:26:51 -04:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c target/arm: Implement LDG, STG, ST2G instructions 2021-02-25 15:08:44 -05:00
pauth_helper.c target/arm: Fix AddPAC error indication 2021-02-25 23:44:28 -05:00
psci.c fix WFI/WFE length in syndrome register 2018-03-05 11:21:51 -05:00
sve.decode target/arm: Sychronize with qemu 2019-04-18 04:49:11 -04:00
sve_helper.c target/arm: Complete TBI clearing for user-only for SVE 2021-02-25 22:37:12 -05:00
t16.decode target/arm: Convert T16, long branches 2019-11-28 02:53:54 -05:00
t32.decode target/arm: Use a non-overlapping group for misc control 2020-06-15 12:52:48 -04:00
tlb_helper.c target/arm: Cache the Tagged bit for a page in MemTxAttrs 2021-02-25 22:48:04 -05:00
translate-a64.c target/arm: Fix decode of LDRA[AB] instructions 2021-02-25 23:47:25 -05:00
translate-a64.h target/arm: Fix temp double-free in sve ldr/str 2021-02-25 23:10:37 -05:00
translate-neon.inc.c target/arm: Move some functions used only in translate-neon.inc.c to that file 2021-02-25 13:15:23 -05:00
translate-sve.c target/arm: Fix bad rebase within do_mem_zpz 2021-02-25 23:43:16 -05:00
translate-vfp.inc.c target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT 2021-02-25 14:02:46 -05:00
translate.c target/arm: Add DISAS_UPDATE_NOCHAIN 2021-02-25 14:08:08 -05:00
translate.h target/arm: Implement the LDGM, STGM, STZGM instructions 2021-02-25 16:00:50 -05:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
unicorn_arm.c arm/translate: Do not tracecode when in an IT block 2021-02-07 19:14:32 +00:00
vec_helper.c target/arm: Convert aes and sm4 to gvec helpers 2020-06-14 22:41:33 -04:00
vec_internal.h arm: Add missing file vec_internal.h 2020-06-20 00:12:09 +01:00
vfp-uncond.decode target/arm: Split VMINMAXNM decode 2020-03-22 00:09:53 -04:00
vfp.decode target/arm: Split VFM decode 2020-03-22 00:07:53 -04:00
vfp_helper.c softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00