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6645 commits

Author SHA1 Message Date
Richard Henderson 9dfc0479ff target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub}
Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Backports commit c7715b6b51a6f7a5412c5fcb40a4c8586105e597 from qemu
2020-05-15 21:25:06 -04:00
Richard Henderson 4abfe5156d target/arm: Create gen_gvec_{cmtst,ushl,sshl}
Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Backports commit 8161b75357095fef54c76b1a6ed1e54d0e8655e0 from qemu
2020-05-15 21:15:49 -04:00
Richard Henderson 15b2850f4d target/arm: Swap argument order for VSHL during decode
Rather than perform the argument swap during code generation,
perform it during decode. This means it doesn't have to be
special cased later, and we can share code with aarch64 code
generation. Hopefully the decode comment addresses any confusion
that might arise in between.

Backports commit e9eee5316ffec5f37643de806b2e5577c5c189cf from qemu
2020-05-15 21:07:59 -04:00
Richard Henderson 546db9089c target/arm: Create gen_gvec_{mla,mls}
Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Backports commit 271063206a46062a45fc6bab8dabe45f0b88159d from qemu
2020-05-15 21:06:06 -04:00
Richard Henderson 340f97bf4c target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0
Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Macro-ize the 5 nearly identical comparisons.

Backports commit 69d5e2bf8c3cefedbfa1c1670137e636dbd7faa5 from qemu
2020-05-15 20:57:33 -04:00
Richard Henderson e08c2b8ece target/arm: Tidy handle_vec_simd_shri
Now that we've converted all cases to gvec, there is quite a bit
of dead code at the end of the function. Remove it.

Sink the call to gen_gvec_fn2i to the end, loading a function
pointer within the switch statement.

Backports commit 3f08f0bce841e7857ec98ce7909629d0c335005e from qemu
2020-05-15 20:47:47 -04:00
Richard Henderson 7a1750d691 target/arm: Remove unnecessary range check for VSHL
In 1dc8425e551, while converting to gvec, I added an extra range check
against the shift count. This was unnecessary because the encoding of
the shift count produces 0 to the element size - 1.

Backports commit 2f27c5244db300387f15d9ffa5067a204ffd625d from qemu
2020-05-15 20:42:12 -04:00
Richard Henderson 6190be3191 target/arm: Create gen_gvec_{sri,sli}
The functions eliminate duplication of the special cases for
this operation. They match up with the GVecGen2iFn typedef.

Add out-of-line helpers. We got away with only having inline
expanders because the neon vector size is only 16 bytes, and
we know that the inline expansion will always succeed.
When we reuse this for SVE, tcg-gvec-op may decide to use an
out-of-line helper due to longer vector lengths.

Backports commit 893ab0542aa385a287cbe46d5535c8b9e95ce699 from qemu
2020-05-15 20:39:28 -04:00
Richard Henderson 2609e6f319 target/arm: Create gen_gvec_{u,s}{rshr,rsra}
Create vectorized versions of handle_shri_with_rndacc
for shift+round and shift+round+accumulate. Add out-of-line
helpers in preparation for longer vector lengths from SVE.

Backports commit 6ccd48d4ea244c1c46a24dfa50bfb547f11422dd from qemu
2020-05-15 20:28:44 -04:00
Richard Henderson 5d7c46204d target/arm: Create gen_gvec_[us]sra
The functions eliminate duplication of the special cases for
this operation. They match up with the GVecGen2iFn typedef.

Add out-of-line helpers. We got away with only having inline
expanders because the neon vector size is only 16 bytes, and
we know that the inline expansion will always succeed.
When we reuse this for SVE, tcg-gvec-op may decide to use an
out-of-line helper due to longer vector lengths.

Backports commit 631e565450c483e0622eec3d8b61d7fa41d16bca from qemu
2020-05-15 20:10:32 -04:00
Richard Henderson 4be4ca57b1 target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
DUP (indexed) can duplicate 128-bit elements, so using esz
unconditionally can assert in tcg_gen_gvec_dup_imm.

Fixes: 8711e71f9cbb

Backports commit 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694 from qemu
2020-05-11 17:22:52 -04:00
Lioncash 5c03efd5d6 arm/helper: Amend sign conversion warning 2020-05-11 17:21:25 -04:00
Lioncash 08cc2c6dcc arm/cpu64: Remove unused variable 2020-05-11 17:18:13 -04:00
Richard Henderson f93deb0786 target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
Now that we can pass 7 parameters, do not encode register
operands within simd_data.

Backports commit 08975da9f0bfcfa654628cae71201a351ba5449a from qemu
2020-05-11 17:17:17 -04:00
Thomas Huth dfe548117e target/arm: Make set_feature() available for other files
Move the common set_feature() and unset_feature() functions
from cpu.c and cpu64.c to cpu.h.

Backports commit 5fda95041d7237ab35733ceb66e0cb89f6107169 from qemu
2020-05-11 17:02:21 -04:00
Philippe Mathieu-Daudé cfe94f63f3 target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
the cpu_count variable and only iterate when it is non-zero.

Backports commit 92b6a659388ab3735e5fbb17ac486923b681f57f from qemu
2020-05-11 16:59:54 -04:00
Richard Henderson 4016b667f3 accel/tcg: Add block comment for probe_access
Backports commit 857129b34190a4c2e782006dc255352a6cd3934b from qemu
2020-05-11 16:42:10 -04:00
Edgar E. Iglesias 91dbd53f77 target/arm: Drop access_el3_aa32ns_aa64any()
Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.

Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
and only use the latter.

Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")

Backports commit 93dd1e6140e2652347cfe7208591d4cd32762d08 from qemu
2020-05-11 16:39:40 -04:00
Mat M 8626c1c69c
Merge pull request #25 from MerryMage/add_reg_for_lit
target/arm: Introduce add_reg_for_lit (fixup)
2020-05-10 14:47:31 -04:00
MerryMage 9255fbce96 target/arm: Introduce add_reg_for_lit (fixup)
Backports commit 16e0d8234ef9291747332d2c431e46808a060472 from qemu

Missed from original backporting commit a2e60445de
2020-05-10 12:30:52 +01:00
Richard Henderson 742301a7c1 tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32,64}
For the benefit of compatibility of function pointer types,
we have standardized on int32_t and int64_t as the integral
argument to tcg expanders.

We converted most of them in 474b2e8f0f7, but missed the rotates.

Backports commit 07dada0336a83002dfa8673a9220a88e13d9a45c from qemu
2020-05-07 10:41:01 -04:00
Richard Henderson 0bcd0ca93d tcg: Add load_dest parameter to GVecGen2
We have this same parameter for GVecGen2i, GVecGen3,
and GVecGen3i. This will make some SVE2 insns easier
to parameterize.

Backports commit ac09ae627e9a2c65c8a452b69c3dac33c29d0719 from qemu
2020-05-07 10:35:47 -04:00
Richard Henderson f02f71f38f tcg: Improve vector tail clearing
Better handling of non-power-of-2 tails as seen with Arm 8-byte
vector operations.

Backports commit f47db80cc073c0a7a22136c8296b5eca20c0e199 from qemu
2020-05-07 10:24:00 -04:00
Richard Henderson 549b0ec3c5 tcg: Add tcg_gen_gvec_dup_tl
For use when a target needs to pass a configure-specific
target_ulong value to duplicate.

Backports commit 0f039e3ad9131966d9fe509c231b756868b015e2 from qemu
2020-05-07 10:12:09 -04:00
Richard Henderson e65806c356 tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i
These interfaces are now unused.

Backports commit 398f21412aeec158338963e3f71c9313bc126a71 form qemu
2020-05-07 10:11:00 -04:00
Richard Henderson 43a72b0540 tcg: Use tcg_gen_gvec_dup_imm in logical simplifications
Replace the outgoing interface.

Backports commit 03ddb6f315ca6d02dfdba0aecc43aa97c728c428 from qemu
2020-05-07 10:09:53 -04:00
Richard Henderson b0f6374149 target/arm: Use tcg_gen_gvec_dup_imm
In a few cases, we're able to remove some manual replication.

Backports commit 8711e71f9cbb692d614e6ecf5d51222372f7b77e from qemu
2020-05-07 10:05:49 -04:00
Richard Henderson 07f622e57d tcg: Add tcg_gen_gvec_dup_imm
Add a version of tcg_gen_dup_* that takes both immediate and
a vector element size operand. This will replace the set of
tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element
size within the function name.

Backports commit 44c94677febd15488f9190b11eaa4a08e8ac696b from qemu
2020-05-07 09:55:25 -04:00
Peter Maydell d350125eab target/arm: Move gen_ function typedefs to translate.h
We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.

Backports commit 9aefc6cf9b73f66062d2f914a0136756e7a28211 from qemu
2020-05-07 09:51:52 -04:00
Peter Maydell 652165d671 target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.

Backports commit 0de34fd48ad4e44bf5caa2330657ebefa93cea7d from qemu
2020-05-07 09:50:44 -04:00
Peter Maydell 17bd8930fc target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
to decodetree.

Backports commit 7a9497f1cf73667a4744d09673b808c20e067915 from qemu
2020-05-07 09:47:18 -04:00
Peter Maydell d52b830ce3 target/arm: Convert Neon 3-reg-same comparisons to decodetree
Convert the Neon comparison ops in the 3-reg-same grouping
to decodetree.

Backports commit 02bd0cdb64b3e79419ba3a8746cb86430883b3ae from qemu
2020-05-07 09:45:03 -04:00
Peter Maydell c6f9fb54fd target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.

Backports commit 36b59310c38d45213bf860affa90618aa5eeca93 from qemu
2020-05-07 09:42:04 -04:00
Peter Maydell d30f99ca79 target/arm: Convert Neon 3-reg-same logic ops to decodetree
Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.

Backports commit 35a548edb6f5043386183b9f6b4139d99d1f130a from qemu
2020-05-07 09:40:10 -04:00
Peter Maydell eae3ce9899 target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.

Note that we don't need the neon_3r_sizes[op] check here because all
size values are OK for VADD and VSUB; we'll add this when we convert
the first insn that has size restrictions.

For this we need one of the GVecGen*Fn typedefs currently in
translate-a64.h; move them all to translate.h as a block so they
are visible to the 32-bit decoder.

Backports commit a4e143ac5b9185f670d2f17ee9cc1a430047cb65 from qemu
2020-05-07 09:36:28 -04:00
Peter Maydell c7a31355fc target/arm: Convert Neon 'load/store single structure' to decodetree
Convert the Neon "load/store single structure to one lane" insns to
decodetree.

As this is the last set of insns in the neon load/store group,
we can remove the whole disas_neon_ls_insn() function.

Backports commit 123ce4e3daba26b760b472687e1fb1ad82cf1993 from qemu
2020-05-07 09:32:17 -04:00
Peter Maydell 302506f2f6 target/arm: Convert Neon 'load single structure to all lanes' to decodetree
Convert the Neon "load single structure to all lanes" insns to
decodetree.

Backports commit 3698747c48db871d876a398592c5a23d7580ed4a from qemu
2020-05-07 09:29:03 -04:00
Peter Maydell 7aad825fa6 target/arm: Convert Neon load/store multiple structures to decodetree
Convert the Neon "load/store multiple structures" insns to decodetree.

Backports commit a27b46304352a0eced45e560e96515dbe3cc174f from qemu
2020-05-07 09:25:51 -04:00
Peter Maydell 9814c1722f target/arm: Convert VFM[AS]L (scalar) to decodetree
Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.

Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.

Backports commit d27e82f7d02f35e5919bd9cbbcb157f3537069a0 from qemu
2020-05-07 09:20:35 -04:00
Peter Maydell 49cdb7e2db target/arm: Convert V[US]DOT (scalar) to decodetree
Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
to decodetree.

Backports commit 35f5d4d1747558c6af2d914bcd848dcc30c3b531 from qemu
2020-05-07 09:17:32 -04:00
Peter Maydell 73dbfbe4d7 target/arm: Convert VCMLA (scalar) to decodetree
Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.

Backports commit 7e1b5d615361bb0038cda0e08af41e350e42d081 from qemu
2020-05-07 09:15:30 -04:00
Peter Maydell 1ab06d3eb5 target/arm: Convert VFM[AS]L (vector) to decodetree
Convert the VFM[AS]L (vector) insns to decodetree. This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.

Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.

Backports commit 9a107e7b8a3c87ab63ec830d3d60f319fc577ff7 from qemu
2020-05-07 09:13:36 -04:00
Peter Maydell c06bdf4cc2 target/arm: Convert V[US]DOT (vector) to decodetree
Convert the V[US]DOT (vector) insns to decodetree.

Backports commit 32da0e330d3e5218b669079826496751fb52c1ca from qemu
2020-05-07 09:09:24 -04:00
Peter Maydell 1d4dba1e5a target/arm: Convert VCADD (vector) to decodetree
Convert the VCADD (vector) insns to decodetree.

Backports commit 94d5eb7b3f72fbbdee55d7908e9cb6de95949f4b from qemu
2020-05-07 09:05:55 -04:00
Peter Maydell d8287755b2 target/arm: Convert VCMLA (vector) to decodetree
Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.

Backports commit afff8de0d4d55b4ce7c36eb9cdfafe477a35dd75 from qemu
2020-05-07 09:02:52 -04:00
Peter Maydell c2c628eb71 target/arm: Add stubs for AArch32 Neon decodetree
Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 Neon encodings. At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.

We follow the same pattern we did for the VFP decodetree conversion
(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
with Neon will be moving gradually out to translate-neon.vfp.inc,
which we #include into translate.c.

In order to share the decode files between A32 and T32, we
split Neon into 3 parts:
* data-processing
* load-store
* 'shared' encodings

The first two groups of instructions have similar but not identical
A32 and T32 encodings, so we need to manually transform the T32
encoding into the A32 one before calling the decoder; the third group
covers the Neon instructions which are identical in A32 and T32.

Backports commit 625e3dd44a15dfbe9532daa6454df3f86cf04d3e from qemu
2020-05-07 08:59:42 -04:00
Peter Maydell 518d18062f target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
We were accidentally permitting decode of Thumb Neon insns even if
the CPU didn't have the FEATURE_NEON bit set, because the feature
check was being done before the call to disas_neon_data_insn() and
disas_neon_ls_insn() in the Arm decoder but was omitted from the
Thumb decoder. Push the feature bit check down into the called
functions so it is done for both Arm and Thumb encodings.

Backports commit d1a6d3b594157425232a1ae5ea7f51b7a1c1aa2e from qemu
2020-05-07 08:55:02 -04:00
Peter Maydell 1964e4b9c9 target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
Somewhere along theline we accidentally added a duplicate
"using D16-D31 when they don't exist" check to do_vfm_dp()
(probably an artifact of a patchseries rebase). Remove it.

Backports commit 0d787cf1f3c88fa29477e054f8523f6d82d91c98 from qemu
2020-05-07 08:52:42 -04:00
Philippe Mathieu-Daudé 8f90b77a6d target/arm: Use uint64_t for midr field in CPU state struct
MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
uint32_t.

This fixes an error when compiling with -Werror=conversion
because we were manipulating the register value using a
local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
628 | cpu->midr = t;
| ^

and future-proofs us against a possible future architecture
change using some of the top 32 bits.

Backports commit e544f80030121040c8932ff1bd4006f390266c0f from qemu
2020-05-07 08:51:28 -04:00
Peter Maydell d28059f4ea target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers. The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register. For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero. Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.

Use the right-sized variable.

Backports commit 5a89dd2385a193aa954a7c9bf4e381f2ba6ae359 from qemu
2020-05-07 08:50:40 -04:00