Commit graph

85 commits

Author SHA1 Message Date
Richard Henderson adf9faf075
target-sparc: Implement swap_asi inline
Backports commit 4fb554bc6c88eb45270a3ad3cf6e6e2ad476aede from qemu
2018-02-28 12:39:55 -05:00
Richard Henderson ebc292c174
target-sparc: Handle more twinx asis
As used by HelenOS, presumably for ultra 2 and 3,
prior to the sun4v platform and the current twinx names.

Backports commit 34a6e13da70b2c798630a8dbd03d09f201c0198f from qemu
2018-02-28 12:28:08 -05:00
Richard Henderson ecbeea7c56
target-sparc: Use MMU_PHYS_IDX for bypass asis
Backports commit 7f87c90527d7363e8cecf1c6b5ad3d4cc85d3d28 from qemu
2018-02-28 12:26:29 -05:00
Richard Henderson 9e60a8e432
target-sparc: Introduce cpu_raise_exception_ra
Several helpers call helper_raise_exception directly, which requires
in turn that their callers have performed save_state. The new function
allows a TCG return address to be passed in so that we can restore
PC + NPC + flags data from that.

This fixes a bug in the usage of helper_check_align, whose callers had
not been calling save_state. It fixes another bug in which the divide
helpers used GETPC at a level other than the direct callee from TCG.

This allows the translator to avoid save_state prior to SAVE, RESTORE,
and FLUSHW instructions.

Backports commit 2f9d35fc4006122bad33f9ae3e2e51d2263e98ee from qemu
2018-02-28 12:15:06 -05:00
Richard Henderson 62ae2a5102
target-sparc: Use overalignment flags for twinx and block asis
This allows us to enforce 16 and 64-byte alignment
without any extra overhead.

Backports commit 808832277af11dafee5a55da2b9e41d019b879ca from qemu
2018-02-28 12:01:50 -05:00
Richard Henderson 1547048a22
tcg: Reorg TCGOp chaining
Instead of using -1 as end of chain, use 0, and link through the 0
entry as a fully circular double-linked list.

Backports commit dcb8e75870e2de199db853697f8839cb603beefe from qemu
2018-02-25 21:44:50 -05:00
Richard Henderson d17dc29d2e
target-sparc: Elide duplicate updates to fprs
Backports commit f9c816c00cf4242542472ae6b2a579b11b7e86f1 from qemu
2018-02-25 19:14:59 -05:00
Richard Henderson 524e4af5ca
target-sparc: Use cpu_fsr in stfsr
Backports commit ba2397d1ca6546e8cf5bd9e2939923546ac3091a from qemu
2018-02-25 19:10:27 -05:00
Richard Henderson 12eecc4939
target-sparc: Use explicit writes to cpu_fsr
By arranging for explicit writes to cpu_fsr after floating point
operations, we are able to mark the helpers as not writing to
tcg globals, which means that we don't need to invalidate the
integer register set across said calls.

Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 18:55:07 -05:00
Richard Henderson 2e24c09db3
target-sparc: Remove helper_ldf_asi, helper_stf_asi
We've now implemented all fp asis inline, except for the no-fault
memory reads. The latter can be passed directly to helper_ld_asi.

Backports commit f2fe396f0fae6b389169f65abf294df9ae6cfee5 from qemu
2018-02-25 18:32:35 -05:00
Richard Henderson a921273a6c
target-sparc: Directly implement block and short ldf/stf asis
Backports commit ca5ce5723fb1ee3445f690004f63c209c15fb813 from qemu
2018-02-25 18:27:52 -05:00
Richard Henderson 333d88c9e6
target-sparc: Directly implement easy ldf/stf asis
Backports commit 7705091ca4a20c8c2d20e2af5d0a1bcb17296657 from qemu
2018-02-25 18:23:45 -05:00
Richard Henderson 9d47cda44c
target-sparc: Pass TCGMemOp constants to helper_ld/st_asi
Reduces the argument count for helper_ld_asi; do helper_st_asi
for consistency.

Backports commit 6850811e7c56403b0d225a1bffd096abf2ff06f9 from qemu
2018-02-25 18:19:42 -05:00
Richard Henderson eb285aa281
target-sparc: Directly implement easy ldd/std asis
Backports commit e4dc0052a40d3e7b00ca0b008f345e2ed644aa20 from qemu
2018-02-25 18:07:51 -05:00
Richard Henderson 1ed7df7720
target-sparc: Introduce gen_check_align
Backports commit 35e94905ce4b39b358a673995f9bee11f46ec8be from qemu
2018-02-25 17:59:47 -05:00
Richard Henderson cef4ae5ca8
target-sparc: Use QT0 to return results from ldda
Also implement a few more twinx asis.

Backports commit 3f4288ebf6fca7b266fa42a74d9d99b961ba6844 from qemu
2018-02-25 17:56:08 -05:00
Richard Henderson 9e402493a9
target-sparc: Directly implement easy ld/st asis
Backports commit f0913be04be13cfb4f9341ae79e035fc8479fd28 from qemu
2018-02-25 17:49:16 -05:00
Richard Henderson e2d0ee1286
target-sparc: Use defines from asi.h
Backports commit 0cc1f4bf76a20c7fee0bab5c9bba9ad7302198b5 from qemu
2018-02-25 17:44:36 -05:00
Richard Henderson c509a5562d
target-sparc: Pass TCGMemOp to gen_ld/st_asi
Backports commit 1d65b0f5bb8f32500bbce09d922d226bb7cf4c68 from qemu
2018-02-25 17:26:34 -05:00
Richard Henderson 4bc53f223c
target-sparc: Introduce get_asi
Replace gen_get_asi, and use it for both 32-bit and 64-bit.
For v8, do supervisor and immediate checks here.

Also, move save_state and TB ending into the respective
subroutines, out of disas_sparc_insn.

Backports commit 7ec1e5ea4bd0700fa48da86bffa2fcc6146c410a from qemu
2018-02-25 17:23:20 -05:00
Richard Henderson 1dcd14d434
target-sparc: Store %asi in TB flags
Knowing the value of %asi at translation time means that we
can handle the common settings without a function call.

The steady state appears to be %asi == ASI_P, so that sparcv9
code can use offset forms of lda/sta. The %asi register gets
pushed and popped on entry to certain functions, but it rarely
takes on values other than ASI_P or ASI_AIUP. Therefore we're
unlikely to be expanding the set of TBs created.

Backports commit a6d567e523ed7e928861f3caa5d49368af3f330d from qemu
2018-02-25 05:17:21 -05:00
Richard Henderson 080281bc9c
target-sparc: Unify asi handling between 32 and 64-bit
We now have a single copy of gen_ld_asi, gen_st_asi,
gen_swap_asi, and everything uses gen_get_asi.

Backports commit 22e700607aeaff5f5e139d0fdc3d861e5502040c from qemu
2018-02-25 05:11:52 -05:00
Richard Henderson 847d65258b
target-sparc: Create gen_exception
This unifies quite a few duplicate code fragments.

Backports commit 4fbe00679000f9fd0c509c2d548d957b08ec6057 from qemu
2018-02-25 04:55:16 -05:00
Richard Henderson 39d1657fc3
target-sparc: Store mmu index in TB flags
Doing this instead of saving the raw PS_PRIV and TL. This means
that all nucleus mode TBs (TL > 0) can be shared. This fixes a
bug in that we didn't include HS_PRIV in the TB flags, and so could
produce incorrect TB matches for hypervisor state.

The LSU and DMMU states were unused by the translator. Including
them in TB flags meant unnecessary mismatches from tb_find_fast.

Backports commit 99a230638a3674e921224dbe628159c867d734b1 from qemu
2018-02-25 04:51:50 -05:00
Richard Henderson 395e00cdc5
target-sparc: Remove softint as a TCG global
The global is only ever read for one insn; we can just as well
use a load from env instead and generate the same code. This
also allows us to indicate the the associated helpers do not
touch TCG globals.

Backports commit e86ceb0d652baa5738e05a59ee0e7989dafbeaa1 from qemu
2018-02-25 04:49:27 -05:00
Lluís Vilanova 2297527755
exec: [tcg] Track which vCPU is performing translation and execution
Information is tracked inside the TCGContext structure, and later used
by tracing events with the 'tcg' and 'vcpu' properties.

The 'cpu' field is used to check tracing of translation-time
events ("*_trans"). The 'tcg_env' field is used to pass it to
execution-time events ("*_exec").

Backports commit 7c2550432abe62f53e6df878ceba6ceaf71f0e7e from qemu
2018-02-24 19:21:39 -05:00
Paolo Bonzini 9485b7c2e1
cpu: move exec-all.h inclusion out of cpu.h
exec-all.h contains TCG-specific definitions. It is not needed outside
TCG-specific files such as translate.c, exec.c or *helper.c.

One generic function had snuck into include/exec/exec-all.h; move it to
include/qom/cpu.h.

Backports commit 63c915526d6a54a95919ebece83fa9ca631b2508 from qemu
2018-02-24 02:39:08 -05:00
Sergey Fedorov ffdc9d6323
tcg: Allow goto_tb to any target PC in user mode
In user mode, there's only a static address translation, TBs are always
invalidated properly and direct jumps are reset when mapping change.
Thus the destination address is always valid for direct jumps and
there's no need to restrict it to the pages the TB resides in.

Backports commit 90aa39a1cc4837360889f0e033ca25cc82100308 from qemu
2018-02-23 23:12:14 -05:00
Artyom Tarasenko 1781d5cfa6
target-sparc: fix register corruption in ldstub if there is no write permission
Backports commit 9566ceeef41ccb5241d340b34776a33450e8f9e5 from qemu
2018-02-23 14:06:38 -05:00
Mark Cave-Ayland 7dcdae9807
target-sparc: fix ldstub sign-extension bug
ldstub [addr], reg incorrectly reads a signed byte from memory which causes
problems in the 32-bit Solaris mutex code. Here the byte value being read is
0xff which is incorrectly sign-extended to 0xffffffff before being written back
to the target register causing lock detection to behave incorrectly.

This fixes the intermittent hangs and MUTEX_HELD warnings issued to the
console when running 32-bit Solaris images under qemu-system-sparc.

With thanks to Joseph Dery for providing a condensed test image to consistently
reproduce the problem on demand, and Martin Husemann for allowing me access to
real hardware for comparison.

Backports commit 4553e10360a0713e31647220ed396942f9a6fca0 from qemu
2018-02-23 13:37:36 -05:00
Lioncash 1c04024688
tcg: Make cpu_regs_sparc a TCGv array 2018-02-21 01:50:28 -05:00
Lioncash db114261e3
target-sparc: Cleanup casts and unnessecary alloc/dealloc 2018-02-21 01:44:51 -05:00
Lioncash c0210ac8a6
tcg: Make cpu_wim a TCGv 2018-02-21 01:41:53 -05:00
Lioncash 58c5a28893
tcg: Make cpu_ver a TCGv 2018-02-21 01:40:30 -05:00
Lioncash 2beea0db0d
tcg: Make cpu_ssr a TCGv 2018-02-21 01:39:15 -05:00
Lioncash b09a8626f0
tcg: Make cpu_hver a TCGv 2018-02-21 01:38:07 -05:00
Lioncash e161e9dcb4
tcg: Make cpu_htba a TCGv 2018-02-21 01:35:40 -05:00
Lioncash 577386b246
tcg: Make cpu_hintp a TCGv 2018-02-21 01:34:13 -05:00
Lioncash 2df9744bdb
tcg: Make cpu_stick_cmpr and cpu_hstick_cmpr TCGv 2018-02-21 01:32:59 -05:00
Lioncash 2d9d8c5e01
tcg: Make cpu_tick_cmpr a TCGv 2018-02-21 01:30:00 -05:00
Lioncash e5401deb09
tcg: Make cpu_npc a TCGv 2018-02-21 01:25:40 -05:00
Lioncash 6ccd4479d7
tcg: Make sparc_cpu_pc a TCGv 2018-02-21 01:23:58 -05:00
Lioncash e5a776b495
tcg: Make cpu_fsr a TCGv 2018-02-21 01:22:16 -05:00
Lioncash b51f920404
tcg: Make cpu_gsr a TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete. Also fixes a leak with sparc
2018-02-21 01:17:01 -05:00
Lioncash 4da2fd6407
tcg: Make cpu_cond a TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 01:12:15 -05:00
Lioncash 2f785b11d2
tcg: Make cpu_tbr a TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 01:12:11 -05:00
Lioncash bbc8517cd2
tcg: Make cpu_y a TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 01:06:36 -05:00
Lluís Vilanova 7db1bffdee
tcg: Add type for vCPU pointers
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The
tracing infrastructure later needs to differentiate between regular
pointers and pointers to vCPUs.

Also changes all targets to use the new 'TCGv_env' type instead of the
generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env'
translates into 'TCGv_ptr'), but that could change in the future to
enforce the difference.

Note that a 'TCGv_env' type (for 'CPUState') is not added, since all
helpers currently receive the architecture-specific
pointer ('CPUArchState').

Backports commit 1bcea73e13b2b059d0cb3301aeaca43e5656ef57 from qemu
2018-02-20 22:53:58 -05:00
Richard Henderson d609ab30c2
target-sparc: Use global registers for the register window
Via indirection off cpu_regwptr.

Backports commit d2dc4069e046deeccc4dca0f73c3077ac22ba43f from qemu
2018-02-20 20:34:42 -05:00
Peter Maydell 139fb637d6
sparc: Clean up includes
Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Backports commit db5ebe5f411833b0ce4b6fa86ee00366e32d3968 from qemu
2018-02-19 00:52:41 -05:00