Commit graph

3683 commits

Author SHA1 Message Date
Emilio G. Cota c1d70758ea
target/i386: move cpu_A0 to DisasContext
Backports commit 6b672b5d6b14422c131969c5725f738751e12847 from qemu
2018-10-04 01:16:35 -04:00
Emilio G. Cota 30c66bcca3
target/i386: move cpu_cc_srcT to DisasContext
Backports commit 93a3e108eb6a9bb781ab7db6e92d91528e482030 from qemu
2018-10-04 00:59:00 -04:00
Daniel P. Berrangé ea64a4629f
configure: preserve various environment variables in config.status
The config.status script is auto-generated by configure upon
completion. The intention is that config.status can be later invoked by
the developer directly, or by make indirectly, to re-detect the same
environment that configure originally used.

The current config.status script, however, only contains a record of the
command line arguments to configure. Various environment variables have
an effect on what configure will find. In particular PKG_CONFIG_LIBDIR &
PKG_CONFIG_PATH vars will affect what libraries pkg-config finds. The
PATH var will affect what toolchain binaries and XXXX-config scripts are
found. The LD_LIBRARY_PATH var will affect what libraries are
found. Most commands have env variables that will override the name/path
of the default version configure finds.

All these key env variables should be recorded in the config.status script.

Autoconf would also preserve CFLAGS, LDFLAGS, LIBS, CPPFLAGS, but QEMU
deals with those differently, expecting extra flags to be set using
configure args, rather than env variables. At the end of the script we
also don't have the original values of those env vars, as we modify them
during configure.

Backports commit e811da7fe229cc17d98b230bdfeaf6d0631ea987 from qemu
2018-10-04 00:46:48 -04:00
Emilio G. Cota f3f22c94e1
atomic: fix comment s/x64_64/x86_64/
Backports commit 119c440c3c599778bfb4f90d8e39fda132925813 from qemu
2018-10-04 00:44:48 -04:00
Roman Kapl 33e69342e3
tcg/i386: fix vector operations on 32-bit hosts
The TCG backend uses LOWREGMASK to get the low 3 bits of register numbers.
This was defined as no-op for 32-bit x86, with the assumption that we have
eight registers anyway. This assumption is not true once we have xmm regs.

Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes
and have overflown into other opcode fields, wreaking havoc.

To trigger these problems, you can try running the "movi d8, #0x0" AArch64
instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated,
but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2".

Fixes: 770c2fc7bb ("Add vector operations")

Backports commit 93bf9a42733321fb632bcb9eafd049ef0e3d9417 from qemu
2018-10-02 04:22:35 -04:00
Peter Maydell 04fead0dcb
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)

Backports commit 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf from qemu
2018-09-25 21:19:44 -04:00
Richard Henderson 994038c817
target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
Not only are the sve-related tb_flags fields unused when SVE is
disabled, but not all of the cpu registers are initialized properly
for computing same. This can corrupt other fields by ORing in -1,
which might result in QEMU crashing.

This bug was not present in 3.0, but this patch is cc'd to
stable because adf92eab90e3f5f34c285 where the bug was
introduced was marked for stable.

Backports commit e79b445d896deb61909be52b61b87c98a9ed96f7 from qemu
2018-09-25 21:17:32 -04:00
Markus Armbruster 8446222237
qapi: Emit a blank line before dummy declaration
We emit a dummy variable in each .c file "to shut up OSX toolchain
warnings about empty .o files" (commit 252dc3105fc). Separate it from
the code preceding it (if any) with a blank line.

Backports commit 5f1450f5444b42cde4b1edc61ea5fdcd57404d3e from qemu
2018-09-25 21:12:16 -04:00
Peter Xu 9c05496958
qapi: Drop qapi_event_send_FOO()'s Error ** argument
The generated qapi_event_send_FOO() take an Error ** argument. They
can't actually fail, because all they do with the argument is passing it
to functions that can't fail: the QObject output visitor, and the
@qmp_emit callback, which is either monitor_qapi_event_queue() or
event_test_emit().

Drop the argument, and pass &error_abort to the QObject output visitor
and @qmp_emit instead.

Backports commit 3ab72385b21d8d66df3f5fea42097ce264dc9d6b from qemu
2018-09-25 21:11:35 -04:00
Markus Armbruster 4a8e094958
qapi: Fix build_params() for empty parameter list
build_params() returns '' instead of 'void' when there are no
parameters. Can't happen now, but the next commit will change that.

Backports commit bdd2d42b890b3a908fa3fbdc9661541e1b57eb15 from qemu
2018-09-25 21:09:42 -04:00
Andrew Dutcher 81f8a1be80
eflags patch
Preserves EFLAGS across basic blocks.

Reapplies commit 3a1f231e8f from qemu
2018-09-07 22:01:24 -04:00
vardyh 8ca718367f
x86::trans: handle illegal case for opc c6/c7
Reference Intel software developer manual vol2 Appendix A Table A-6 for
detailed decoding information.

Re-applies commit ad767abda8 from qemu
2018-09-07 19:28:01 -04:00
Lioncash 48d98a76e7
hw/mips/mips_r4k: Fix initialization of MIPS target CPUs
MIPS emulation is now possible after this basic fix. Still a few kinks
to work out, but at least we hit the translation loop.
2018-09-03 17:40:08 -04:00
Lioncash fa8f566635
target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:36:23 -04:00
Lioncash e81fa596bc
target/arm/cpu: Use type_register instead of type_register_static() in arm_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:34:08 -04:00
Lioncash 34b22968a4
target/i386/cpu: Use type_register instead of type_register_static in x86_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:28:54 -04:00
Lioncash 0a759bf7f3
target/sparc: Fix SPARC target initialization
Brings up the SPARC target so it's able to be used for emulation
purposes.
2018-09-03 17:26:00 -04:00
Lioncash 44ca501cd3
target/m68k: Fix initialization of m68k targets
m68k is now able to be used for emulation again. It just needed to
properly have the unicorn context be set within the base type for the
CPUs
2018-09-03 17:04:42 -04:00
MerryMage 9b87d0f61a unicorn_arm: Allow for read/write of UC_ARM_REG_FPSCR 2018-09-03 21:03:55 +01:00
Lioncash fffc31e7e2
target/i386/translate: Synchronize EIP if read/write callbacks are set
This is another feature that was left by the wayside when upgrading
qemu. It's fairly trivial to restore.
2018-09-03 14:40:46 -04:00
Lioncash 0d0d8b6db9
target/i386/translate: Report proper instruction size in code hooks
This was intentionally broken to make updating qemu as quick as possible
when it was woefully out of date, particularly because the interface of
qemu's TCG changed quite a bit, so this code would have needed to be
changed anyways.

Now that qemu is up to date for this variant of Unicorn, we can repair
this functionality and also--and I put massive emphasis on this, since
this wasn't done in the original Unicorn repo--*actually document what
the heck we're doing in this case*, so it's not a pain to change in the
future if we actually need to do that. It makes it much, much, simpler
for people not involved with qemu to understand what is going on in this
case.
2018-09-03 14:09:05 -04:00
Lioncash dce6dde483
target/i386/translate: Remove unnecessary (and incorrect) pointer casts from some gen_op functions
These used to be necessary, as the relevant variables used to be void*,
thus making the casts necessary. Given they were changed to concrete
types over the course of backporting, these are unnecessary.
2018-09-03 10:44:55 -04:00
Lioncash 73c7c9aadc
unicorn_common: Fix unicorn memory functions failing
These functions, over the course of backporting qemu's newer changes,
were altered to return non-zero in the case of success, so we need to
update the cpu read/write functions as necessary.
2018-09-03 10:40:14 -04:00
Lioncash a97d643944
qemu/int128: Disable assert in int128.h
This mirrors the int128_get64() variant for the case when CONFIG_INT128
is not defined as 1, which was pre-existing in unicorn.
2018-09-03 09:54:59 -04:00
Lioncash 2beb139304
i386: Fix initialization of x86 targets 2018-09-03 09:14:35 -04:00
Nguyen Anh Quynh d149648f2f
x86: fix #968. also fix potential bug of not clearing high bytes when updateing EIP
Backports commit 4d0157eb4a4891fe9101ac84accbd11cd4277794 from qemu
2018-09-03 07:58:16 -04:00
Alex von Gluck IV 80b94a546f
Haiku support patches (#989)
* Haiku: fix broken gcc strong stack protector

* qemu: Backport minor Haiku fix

We need to push this fix upstream to qemu. If we don't
get it upstreamed, i'll circle back and patch it if
Unicorn updates its qemu version.

Backports commit c7be4a2160e15089563f207752fb346a38db18ec from unicorn
2018-09-03 07:55:51 -04:00
toshiMSFT b4bb7edfe8
Makes SYSENTER hookable again on x86
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing

Fixes unicorn-engine/unicorn#995

Backports commit 0f14c473445661a633ca5bda3a91ba1a87c35c64 from unicorn
2018-09-03 07:53:48 -04:00
Mat M e87df070d9
Merge pull request #11 from MerryMage/arm-aa32_vfp_dreg
Unicorn VFP access patches
2018-09-03 07:25:47 -04:00
MerryMage a13d51f756 unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
MerryMage 896a8e1320 unicorn_arm: Use ARM offset not ARM64 offset
Was introduced by 5439b4a542
2018-09-03 07:44:29 +01:00
Lioncash f419c5f554
hw/arm/tosa: Enable all CPU features by using the max target for A-class CPUs
This mirrors the current behavior for the AArch64 CPUs, where we also
use the max target.
2018-09-02 16:19:28 -04:00
Lioncash 0ad97c7ee3
hw/tosa: Fix initialization of AArch32 CPUs
We have to ensure that we pass the proper formatted name into cpu_new()
2018-09-02 16:02:26 -04:00
Stefan Markovic c870339a10
target/mips: Add definition of nanoMIPS I7200 CPU
Add definition of the first nanoMIPS processor in QEMU.

Backports commit d45942d908edee175a90f915ab92ac302eedf33a from qemu
2018-08-27 15:08:12 -04:00
Yongbok Kim d53c021cea
target/mips: Fix ERET/ERETNC behavior related to ADEL exception
Fix ERET/ERETNC so that ADEL exception can be raised.

Backports commit 26324ded91a5ad08a5de8f32b8ed5e5e243154cf from qemu
2018-08-27 15:00:59 -04:00
Stefan Markovic 7473e6dbe6
target/mips: Add updating BadInstr and BadInstrX for nanoMIPS
Update BadInstr and BadInstrX registers for nanoMIPS. The same
support for pre-nanoMIPS remains unimplemented.

Backports commit 7a5f784aa215df6bf5d674b4003f8df43bf3b2d4 from qemu
2018-08-27 15:00:05 -04:00
Dimitrije Nikolic 7e0342c9f6
target/mips: Add availability control via bit NMS
A set of nanoMIPS instructions is not available if Config5 bit NMS
is set.

Backports commit fb32f8c8560be7ca4e323cee1b839701126401d1 from qemu
2018-08-27 14:59:15 -04:00
Stefan Markovic 38f2640a34
target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
Add emulation of DSP ASE instructions for nanoMIPS - part 6.

Backports commit 0b591184a2d0686b8f2c5fb27cc9fe2f60752d57 from qemu
2018-08-27 06:47:59 -04:00
Stefan Markovic ba7d8bc0ab
target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
Add emulation of DSP ASE instructions for nanoMIPS - part 5.

Backports commit 4c75c985d9b4d2ac7e0183083e31c243b06a3f2b from qemu
2018-08-27 06:45:25 -04:00
Stefan Markovic 73a5efd599
target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
Add emulation of DSP ASE instructions for nanoMIPS - part 4.

Backports commit 8b3698b2947610e0645a65ace4822164d55dd76b from qemu
2018-08-27 06:43:34 -04:00
Stefan Markovic b6602fff1f
target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
Add emulation of DSP ASE instructions for nanoMIPS - part 3.

Backports commit 2ed42efaae9516b71b7edf669b120cad718ba37b from qemu
2018-08-27 06:34:14 -04:00
Stefan Markovic 33dee2e5f3
target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
Add emulation of DSP ASE instructions for nanoMIPS - part 2.

Backports commit 6d033ca7513d85562f1b6bbb002a38b1c2541e5d from qemu
2018-08-27 05:53:17 -04:00
Stefan Markovic 49f448af3c
target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
Add emulation of DSP ASE instructions for nanoMIPS - part 1.

Backports commit 3285a3e4445be70d5f2dbdd29249e1e2627a5216 from qemu
2018-08-27 05:52:12 -04:00
Stefan Markovic 795d903f1c
target/mips: Implement MT ASE support for nanoMIPS
Add emulation of MT ASE instructions for nanoMIPS.

Backports commit 0a1a6ed78ae13a87f23810899a838f8d0c0fa2a5 from qemu
2018-08-27 05:39:15 -04:00
Aleksandar Rikalo 8c0248696a
target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
This is done by adding a field in hflags for MT bit, and adding
functions check_mt() and check_cp0_mt().

Backports commit 9affc1c59279f482ff145e0371926f79b6448e3e from qemu
2018-08-27 05:36:38 -04:00
Stefan Markovic 93f7cd2307
target/mips: Add emulation of nanoMIPS 32-bit branch instructions
Add emulation of various flavors of nanoMIPS 32-bit branch
instructions.

Backports commit 11d0fc10b7efe3d0404a71e855c0d9f521ce3d66 from qemu
2018-08-27 05:34:52 -04:00
Aleksandar Rikalo 371bb5a134
target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside
adding core functionality of these instructions, this patch adds
support for availability control via configuration bit XNP.

Backports commit 0b16dcd180bdbe3add9edea42c2374d427882661 from qemu
2018-08-27 05:25:14 -04:00
Dimitrije Nikolic 128bfa00d2
target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.

Backports commit ab77fc611bf004dfd25ecad5b2c11261e32012e9 from qemu
2018-08-27 05:20:26 -04:00
Yongbok Kim e18c921501
target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
Add emulation of various nanoMIPS load and store instructions.

Backports commit 8f1d9b6d63978b80971b15fef16636f454241879 from qemu
2018-08-27 05:18:55 -04:00
James Hogan bcdee16199
target/mips: Implement emulation of nanoMIPS EXTW instruction
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).

Backports commit 821f2008c3c708e0e33158039ab55673a0f04519 from qemu
2018-08-27 05:14:54 -04:00