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1760 commits

Author SHA1 Message Date
Richard Henderson dec55633dc
target/arm: Convert T16, Conditional branches, Supervisor call 
Backports commit 629fcaa71ca9a5d6695d1664257b6a5327f38bd6 from qemu
 2019-11-28 02:53:01 -05:00
Richard Henderson 336d6b3625
target/arm: Convert T16, push and pop 
Backports commit 564b125fb9dec77e5bca9b4590786985ccc3d6cb from qemu
 2019-11-28 02:52:44 -05:00
Richard Henderson 25d1de9005
target/arm: Split gen_nop_hint 
Now that all callers pass a constant value, split the switch
statement into the individual trans_* functions.

Backports commit 279de61a21a1622cb875ead82d6e78c989ba2966 from qemu
 2019-11-28 02:52:37 -05:00
Richard Henderson a45db7fcd1
target/arm: Convert T16, nop hints 
Backports commit 56e6250ede81b4e4b4ddb623874d6c3cdad4a96d from qemu
 2019-11-28 02:52:29 -05:00
Richard Henderson 676f1c8783
target/arm: Convert T16, Reverse bytes 
Backports commit ae3002b0218a90f2088817c70b35d3832ec91c18 from qemu
 2019-11-28 02:52:19 -05:00
Richard Henderson 692ad18e62
target/arm: Convert T16, Change processor state 
Add a check for ARMv6 in trans_CPS. We had this correct in
the T16 path, but had previously forgotten the check on the
A32 and T32 paths.

Backports commit 20556e7bd6111266fbf1d81e4ff7a89bfa5795a7 from qemu
 2019-11-28 02:52:13 -05:00
Richard Henderson cc7d3fe9da
target/arm: Convert T16, extract 
Backports commit e6f69612cc79e2acc05dafda8695f791a916946f from qemu
 2019-11-28 02:52:06 -05:00
Richard Henderson 40282af492
target/arm: Convert T16 adjust sp (immediate) 
Backports commit 2e6a646d7b1304d9106baad73c655132e2736c6c from qemu
 2019-11-28 02:51:54 -05:00
Richard Henderson 927fb85b51
target/arm: Convert T16 add, compare, move (two high registers) 
Backports commit 90aa042115a0fe39fe4cb3bcae4c4f728e2f3fdb from qemu
 2019-11-28 02:51:46 -05:00
Richard Henderson 7ca1b3f817
target/arm: Convert T16 branch and exchange 
Backports commit a0ef07740425b679d010fac7d9954ae003c1b191 from qemu
 2019-11-28 02:51:39 -05:00
Richard Henderson c690f562c4
target/arm: Convert T16 one low register and immediate 
Backports commit 6c6d237a865041972ec5b226657398f3b3018561 from qemu
 2019-11-28 02:51:31 -05:00
Richard Henderson d9184b16a9
target/arm: Convert T16 add/sub (3 low, 2 low and imm) 
Backports commit c4d3095bb62bdac0b4f9cb180bd7aa0b40c2c270 from qemu
 2019-11-28 02:51:24 -05:00
Richard Henderson c52cfb9aa6
target/arm: Convert T16 load/store multiple 
Backports commit 6e8514ba408f3cc758cd47e2da5475d8684507ec from qemu
 2019-11-28 02:51:16 -05:00
Richard Henderson 10c8008266
target/arm: Convert T16 add pc/sp (immediate) 
Backports commit 1cb1323433dca657a42483b2291c1ae923a91726 from qemu
 2019-11-28 02:51:08 -05:00
Richard Henderson 7f79c0f2a1
target/arm: Convert T16 load/store (immediate offset) 
Backports commit 07afd747f9fdd79fabf3a51416c7d795f873d297 from qemu
 2019-11-28 02:51:01 -05:00
Richard Henderson 0ed7d59e35
target/arm: Convert T16 load/store (register offset) 
Backports commit d1d229179c6b011cc3fa124d4b6b649866470530 from qemu
 2019-11-28 02:50:48 -05:00
Richard Henderson e30f636e8a
target/arm: Convert T16 data-processing (two low regs) 
Backports commit 080c4eadcbbaf95a6fcc4668cf16e4580f2bfe11 from qemu
 2019-11-28 02:50:40 -05:00
Richard Henderson 0b2f37afaf
target/arm: Add skeleton for T16 decodetree 
Backports commit f97b454e9e7f5d018d34b5ea85a66cff016bd3b7 from qemu
 2019-11-28 02:50:27 -05:00
Richard Henderson 19f1da260f
target/arm: Simplify disas_arm_insn 
Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.

Backports commit 590057d969a54de5d97261701c5702b3bebc9c07 from qemu
 2019-11-28 02:50:03 -05:00
Richard Henderson e402eef2f0
target/arm: Simplify disas_thumb2_insn 
Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.

Backports commit f843e77144c9334e244a422848177f2fbef5eb05 from qemu
 2019-11-28 02:48:20 -05:00
Richard Henderson 1b5c72935d
target/arm: Convert TT 
Backports commit d449f174e820b15ca1a1f5f3ec19999eeb7da14c from qemu
 2019-11-28 02:48:06 -05:00
Richard Henderson 0e03a1f59c
target/arm: Convert SG 
Backports commit 35d240acf1b6a89558e74b490feb13267415b236 from qemu
 2019-11-28 02:47:57 -05:00
Richard Henderson 0afb6ab7af
target/arm: Convert Table Branch 
Backports commit 808092bbe356eef0897476be50193d0778596877 from qemu
 2019-11-28 02:47:48 -05:00
Richard Henderson e6b4480ca9
target/arm: Convert Unallocated memory hint 
Backports commit 610f4e1764aa2049fa1711893ff62faf777813f3 from qemu
 2019-11-28 02:47:41 -05:00
Richard Henderson 4593c67444
target/arm: Convert PLI, PLD, PLDW 
Backports commit beb595f657d615856fee904f1e0f74f5e1e299a3 from qemu
 2019-11-28 02:47:33 -05:00
Richard Henderson 5a23a1f020
target/arm: Convert SETEND 
Backports commit 48c04a5dfaf2c08e00b659a22c502ec098999cf1 from qemu
 2019-11-28 02:47:26 -05:00
Richard Henderson 55390520d6
target/arm: Convert CPS (privileged) 
Backports commit 52f83b9c68bdde8d3da5f49292d3561bd474651d from qemu
 2019-11-28 02:47:19 -05:00
Richard Henderson 15558cfa7e
target/arm: Convert Clear-Exclusive, Barriers 
Backports commit 519b84711ea36bb8a339096e207b6b9b65cd2051 from qemu
 2019-11-28 02:47:11 -05:00
Richard Henderson eff475c9a9
target/arm: Convert RFE and SRS 
Backports commit 885782a78c6d05932c5d8f463dc50fc8312e3eb9 from qemu
 2019-11-28 02:47:04 -05:00
Richard Henderson 87ff6a8bdf
target/arm: Convert SVC 
Backports commit 542f5188a14758d64f7504580a9bd3cae973f546 from qemu
 2019-11-28 02:46:55 -05:00
Richard Henderson a119870e57
target/arm: Convert B, BL, BLX (immediate) 
Backports commit 360144f3b99f9a626ffcc6b9d76537e3a3e0e708 from qemu
 2019-11-28 02:46:47 -05:00
Richard Henderson ed9b8ad2ea
target/arm: Diagnose base == pc for LDM/STM 
We have been using store_reg and not store_reg_for_load when writing
back a loaded value into the base register. At first glance this is
incorrect when base == pc, however that case is UNPREDICTABLE.

Backports commit b0e382b8cf365fed8b8c43482029ac7655961a85 from qemu
 2019-11-28 02:46:40 -05:00
Richard Henderson 1a0986ee25
target/arm: Diagnose too few registers in list for LDM/STM 
This has been a TODO item for quite a while. The minimum bit
count for A32 and T16 is 1, and for T32 is 2.

Backports commit 4b222545dbf30b60c033e1cd6eddda612575fd8c from qemu
 2019-11-28 02:46:33 -05:00
Richard Henderson fc81b12631
target/arm: Diagnose writeback register in list for LDM for v7 
Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN
value back to the base register. Starting in v7 this is UNPREDICTABLE.

Backports commit 3949f4675d13c587078f8f423845a3a537a22595 from qemu
 2019-11-28 02:46:24 -05:00
Richard Henderson a501800ba6
target/arm: Convert LDM, STM 
This includes a minor bug fix to LDM (user), which requires
bit 21 to be 0, which means no writeback.

Backports commit c5c426d4c680f908a1e262091a17b088b5709200 from qemu
 2019-11-28 02:46:04 -05:00
Richard Henderson e4ca88f9d6
target/arm: Convert MOVW, MOVT 
Backports commit 8f4451274b7010c1f50e0baa5bb608f19f02b90f from qemu
 2019-11-28 02:46:04 -05:00
Richard Henderson b35749e239
target/arm: Convert Signed multiply, signed and unsigned divide 
Backports commit 2c7c4e090409189488149869797da4acf895bad0 from qemu
 2019-11-28 02:45:33 -05:00
Richard Henderson 987641cf10
target/arm: Convert packing, unpacking, saturation, and reversal 
Backports commit 46497f6af73bb33c1064d43a28a48cbb4d233a23 from qemu
 2019-11-28 02:44:55 -05:00
Richard Henderson 83cced6170
target/arm: Convert Parallel addition and subtraction 
Backports commit adf1a5662a47d5b5b96f4f1e440e34c26b14a154 from qemu
 2019-11-28 02:44:20 -05:00
Richard Henderson 21df423e47
target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF 
In op_bfx, note that tcg_gen_{,s}extract_i32 already checks
for width == 32, so we don't need to special case that here.

Backports commit 86d21e4b509a2835ed79f234f476a4c5191d435b from qemu
 2019-11-28 02:44:20 -05:00
Richard Henderson dbcc67ab20
target/arm: Diagnose UNPREDICTABLE ldrex/strex cases 
Backports commit af2882289951e58363d714afd16f80050685fa29 from qemu
 2019-11-28 02:44:20 -05:00
Richard Henderson 3ac019eb98
target/arm: Convert Synchronization primitives 
Backports commit 1efdd407a25f617129e2e0d5c009c07cbe847990 from qemu
 2019-11-28 02:44:18 -05:00
Richard Henderson c794962c42
target/arm: Convert load/store (register, immediate, literal) 
Backports commit 5e291fe16846d216d5a69569b1c59f497dff96e4 from qemu
 2019-11-28 02:42:01 -05:00
Richard Henderson d5d98450f3
target/arm: Convert T32 ADDW/SUBW 
Backports commit 145952e87fb86aaa9434d768c31eedbd323f7157 from qemu
 2019-11-28 02:42:01 -05:00
Richard Henderson 7b9025910d
target/arm: Convert the rest of A32 Miscelaneous instructions 
Backports commit 2cde9ea57dbc4cdee3677a1a335574537810fe2e from qemu
 2019-11-28 02:42:01 -05:00
Richard Henderson be2a259d3c
target/arm: Convert ERET 
Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path
to make it clear exactly what's happening -- we hit ALUExceptionReturn
along that path.

Backports commit ef11bc3c461e2c650e8bef552146a4b08f81884e from qemu
 2019-11-28 02:42:00 -05:00
Richard Henderson 74040da34c
target/arm: Convert CLZ 
Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour.
This matches the undocumented choice made by the legacy decoder.

Backports commit 4c97f5b2f0fa9b37f9ff497f15411d809e6fd098 from qemu
 2019-11-28 02:42:00 -05:00
Richard Henderson 94968602b8
target/arm: Convert BX, BXJ, BLX (register) 
Backports commit 4ed95abd700e43dee8e032f754b53bec2b047f75 from qemu
 2019-11-28 02:42:00 -05:00
Richard Henderson 831e17d970
target/arm: Convert Cyclic Redundancy Check 
Backports commit 6c35d53f1bde7fe327c074473c3048d6e6f15e95 from qemu
 2019-11-28 02:42:00 -05:00
Richard Henderson fdd135c7d2
target/arm: Convert MRS/MSR (banked, register) 
The m-profile and a-profile decodings overlap. Only return false
for the case of wrong profile; handle UNDEFINED for permission failure
directly. This ensures that we don't accidentally pass an insn that
applies to the wrong profile.

Backports commit d0b26644502103ca97093ef67749812dc1df7eea from qemu
 2019-11-28 02:42:00 -05:00