LIU Zhiwei
f9c9716534
target/riscv: vector floating-point classify instructions
...
Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c
2021-03-07 11:55:45 -05:00
LIU Zhiwei
b859be12b9
target/riscv: vector floating-point compare instructions
...
Backports 2a68e9e568faddf4d689a37fa6895bcb8404a677
2021-03-07 11:47:51 -05:00
LIU Zhiwei
31978f270b
target/riscv: vector floating-point sign-injection instructions
...
Backports 1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
2021-03-07 11:43:47 -05:00
LIU Zhiwei
f7f0425a4d
target/riscv: vector floating-point min/max instructions
...
Backports 230b53ddd706c8b18a6d9beed1a0153b276d7037
2021-03-07 11:42:05 -05:00
LIU Zhiwei
69c73cfc4e
target/riscv: vector floating-point square-root instruction
...
Backports d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
2021-03-07 11:40:04 -05:00
LIU Zhiwei
95a6d78121
target/riscv: vector widening floating-point fused multiply-add instructions
...
Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
2021-03-07 11:37:23 -05:00
LIU Zhiwei
42116609f0
target/riscv: vector single-width floating-point fused multiply-add instructions
...
Backports 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
2021-03-07 11:34:56 -05:00
LIU Zhiwei
14cbabde4f
target/riscv: vector widening floating-point multiply
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Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
2021-03-07 11:32:19 -05:00
LIU Zhiwei
5e4b142c31
target/riscv: vector single-width floating-point multiply/divide instructions
...
Backports 0e0057cbe2169195a08ae8247504e69f9b80542b
2021-03-07 11:30:14 -05:00
LIU Zhiwei
0de56731ae
target/riscv: vector widening floating-point add/subtract instructions
...
eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
2021-03-07 11:27:33 -05:00
LIU Zhiwei
06092b88b9
target/riscv: vector single-width floating-point add/subtract instructions
...
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
2021-03-05 09:50:56 -05:00
LIU Zhiwei
5fb589cdd7
target/riscv: vector narrowing fixed-point clip instructions
...
Backports 9ff3d28739b760970f5e542c74a033470dca3f9b
2021-03-05 09:34:11 -05:00
LIU Zhiwei
241deddb50
target/riscv: vector single-width scaling shift instructions
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Backports 04a614062dd5fb43f00bd955f44f7a2c3def016d
2021-03-05 09:32:15 -05:00
LIU Zhiwei
e7582a5d74
target/riscv: vector widening saturating scaled multiply-add
...
Backports 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
2021-03-05 09:29:42 -05:00
LIU Zhiwei
e27aadfa4f
target/riscv: vector single-width fractional multiply with rounding and saturation
...
Backports 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
2021-03-05 09:26:56 -05:00
LIU Zhiwei
2343892c2e
target/riscv: vector single-width averaging add and subtract
...
Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
2021-03-05 09:25:09 -05:00
LIU Zhiwei
87db3eb130
target/riscv: vector single-width saturating add and subtract
...
Backports eb2650e35ec1ed60ff302ce3330bd6c770640833
2021-03-05 09:23:17 -05:00
LIU Zhiwei
025aa6fd39
target/riscv: vector integer merge and move instructions
...
Backports f020a7a14505d6996497693e63331ab609847d93
2021-03-05 09:20:34 -05:00
LIU Zhiwei
9d14cc8d35
target/riscv: vector widening integer multiply-add instructions
...
Backports 2b587b335050dbc0cb3823758341f145c0375312
2021-03-05 09:13:03 -05:00
LIU Zhiwei
58891e213d
target/riscv: vector single-width integer multiply-add instructions
...
Backports 54df813a331d3badfb83604c36bef7cb1de4315a
2021-03-05 09:11:33 -05:00
LIU Zhiwei
436e092e36
target/riscv: vector widening integer multiply instructions
...
Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428
2021-03-05 09:09:08 -05:00
LIU Zhiwei
d144afdc45
target/riscv: vector integer divide instructions
...
Backports 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
2021-03-05 09:05:00 -05:00
LIU Zhiwei
9b7f4b72fc
target/riscv: vector single-width integer multiply instructions
2021-02-26 10:46:26 -05:00
LIU Zhiwei
ab81642440
target/riscv: vector integer min/max instructions
...
558fa7797c919c4f21ac10980f3ed28160d6d3cb
2021-02-26 10:43:13 -05:00
LIU Zhiwei
965af9986a
target/riscv: vector integer comparison instructions
...
1366fc79be04fa56a0e3f078ba4f26c27ac67e89
2021-02-26 10:40:33 -05:00
LIU Zhiwei
244793c4e8
target/riscv: vector single-width bit shift instructions
...
Backports 3277d955d21d8943d80062b4cfd8547f831dbd51
2021-02-26 10:37:09 -05:00
LIU Zhiwei
56c0e253c2
target/riscv: vector bitwise logical instructions
...
Backports d3842924cf93d104f691c5ea9090d6700ccef281
2021-02-26 10:30:33 -05:00
LIU Zhiwei
05153c6d7c
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
...
3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448
2021-02-26 10:19:48 -05:00
LIU Zhiwei
b9814de4c3
target/riscv: vector widening integer add and subtract
...
Backports 8fcdf77630290591a6068c2d82ca2935338c3b0c
2021-02-26 10:05:43 -05:00
LIU Zhiwei
f564388e89
target/riscv: vector single-width integer add and subtract
...
Backports 43740e3a3b3bb66456103684e622ba4e9baae297
2021-02-26 09:58:31 -05:00
LIU Zhiwei
7d0d7338c2
target/riscv: add vector amo operations
...
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Backports 268fcca66bde62257960ec8d859de374315a5e3d
2021-02-26 09:47:32 -05:00
LIU Zhiwei
152934bade
target/riscv: add fault-only-first unit stride load
...
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Backports commit 022b4ecf775ffeff522eaea4f0d94edcfe00a0a9 from qemu
2021-02-26 09:28:19 -05:00
LIU Zhiwei
887c29bc79
target/riscv: add vector index load and store instructions
...
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Backports f732560e3551c0823cee52efba993fbb8f689a36
2021-02-26 03:00:45 -05:00
LIU Zhiwei
c7a17d04a2
target/riscv: add vector stride load and store instructions
...
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.
Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.
Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 02:55:14 -05:00
LIU Zhiwei
9db3b70869
target/riscv: add vector configure instruction
...
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu
2021-02-26 02:37:59 -05:00
