unicorn/qemu/target/arm
Peter Maydell 62178626e4 target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
Our current usage of the isar_feature feature tests almost always
uses an _aa32_ test when the code path is known to be AArch32
specific and an _aa64_ test when the code path is known to be
AArch64 specific. There is just one exception: in the vfp_set_fpscr
helper we check aa64_fp16 to determine whether the FZ16 bit in
the FP(S)CR exists, but this code is also used for AArch32.
There are other places in future where we're likely to want
a general "does this feature exist for either AArch32 or
AArch64" check (typically where architecturally the feature exists
for both CPU states if it exists at all, but the CPU might be
AArch32-only or AArch64-only, and so only have one set of ID
registers).

Introduce a new category of isar_feature_* functions:
isar_feature_any_foo() should be tested when what we want to
know is "does this feature exist for either AArch32 or AArch64",
and always returns the logical OR of isar_feature_aa32_foo()
and isar_feature_aa64_foo().

Backports commit 6e61f8391cc6cb0846d4bf078dbd935c2aeebff5 from qemu
2020-03-21 18:12:02 -04:00
..
a32-uncond.decode target/arm: Convert Unallocated memory hint 2019-11-28 02:47:41 -05:00
a32.decode target/arm: Convert SVC 2019-11-28 02:46:55 -05:00
arm-powerctl.c arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() 2020-01-07 18:10:29 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2018-03-02 00:20:11 -05:00
cpu-param.h target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled 2020-03-21 17:12:16 -04:00
cpu-qom.h target/arm: Add the hypervisor virtual counter 2020-03-21 15:35:36 -04:00
cpu.c target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers 2020-03-21 18:08:23 -04:00
cpu.h target/arm: Add isar_feature_any_fp16 and document naming/usage conventions 2020-03-21 18:12:02 -04:00
cpu64.c target/arm: Implement ARMv8.1-VMID16 extension 2020-03-21 17:52:43 -04:00
crypto_helper.c target/arm/cpu and crypto_helper: Correct bad merge and adjust to qemu code style 2018-03-12 11:57:24 -04:00
debug_helper.c target/arm: Add CONTEXTIDR_EL2 2020-03-21 13:39:20 -04:00
helper-a64.c target/arm: Introduce aarch64_pstate_valid_mask 2020-03-21 17:26:00 -04:00
helper-a64.h target/arm: check CF_PARALLEL instead of parallel_cpus 2019-05-04 22:44:32 -04:00
helper-sve.h target/arm: Rewrite vector gather first-fault loads 2018-10-08 14:15:15 -04:00
helper.c target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan 2020-03-21 18:09:27 -04:00
helper.h target/arm: Handle trapping to EL2 of AArch32 VMRS instructions 2020-01-07 18:04:16 -05:00
internals.h target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers 2020-03-21 18:08:23 -04:00
iwmmxt_helper.c target/arm: Untabify iwmmxt_helper.c 2018-08-25 04:33:44 -04:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
m_helper.c target/arm: only update pc after semihosting completes 2020-01-14 08:28:25 -05:00
Makefile.objs target/arm: Add skeleton for T16 decodetree 2019-11-28 02:50:27 -05:00
neon_helper.c target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs 2019-05-16 16:43:02 -04:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c target/arm: Remove CPSR_RESERVED 2020-03-21 17:24:21 -04:00
pauth_helper.c target/arm: Use bit 55 explicitly for pauth 2020-03-21 17:59:06 -04:00
psci.c fix WFI/WFE length in syndrome register 2018-03-05 11:21:51 -05:00
sve.decode target/arm: Sychronize with qemu 2019-04-18 04:49:11 -04:00
sve_helper.c tcg: Use tlb_fill probe from tlb_vaddr_to_host 2019-05-16 18:27:03 -04:00
t16.decode target/arm: Convert T16, long branches 2019-11-28 02:53:54 -05:00
t32.decode target/arm: Convert TT 2019-11-28 02:48:06 -05:00
tlb_helper.c target/arm: Return correct IL bit in merge_syn_data_abort 2020-03-21 12:08:05 -04:00
translate-a64.c target/arm: Flush high bits of sve register after AdvSIMD INS 2020-03-21 17:58:09 -04:00
translate-a64.h tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
translate-sve.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
translate-vfp.inc.c target/arm: Handle trapping to EL2 of AArch32 VMRS instructions 2020-01-07 18:04:16 -05:00
translate.c target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers 2020-03-21 18:08:23 -04:00
translate.h target/arm: Update get_a64_user_mem_index for VHE 2020-03-21 16:33:52 -04:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
unicorn_arm.c Add implementation of access to the ARM SPSR register. (#1178) 2020-01-14 09:57:55 -05:00
vec_helper.c target/arm: Add helpers for FMLAL 2019-02-28 15:31:48 -05:00
vfp-uncond.decode target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree 2019-06-13 16:54:42 -04:00
vfp.decode target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm 2019-06-25 18:20:19 -05:00
vfp_helper.c target/arm: Add isar_feature_any_fp16 and document naming/usage conventions 2020-03-21 18:12:02 -04:00