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unicorn/qemu/target/riscv/insn32.decode

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target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
target/riscv: Convert RV32F insns to decodetree Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 20:33:32 +00:00
%rs3 27:5
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
%rs2 20:5
%rs1 15:5
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
%rd 7:5
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 20:04:46 +00:00
%sh10 20:10
target/riscv: Convert RVXI csr insns to decodetree Backports commit 771fbe156a2a2be964a4fbe6251339a5570a26c4 from qemu
2019-03-18 20:16:32 +00:00
%csr 20:12
target/riscv: Convert RV32F insns to decodetree Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 20:33:32 +00:00
%rm 12:3
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 07:44:17 +00:00
%nf 29:3 !function=ex_plus_1
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 20:04:46 +00:00
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
# immediates:
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
%imm_i 20:s12
target/riscv: Convert RV32I load/store insns to decodetree Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 19:59:40 +00:00
%imm_s 25:s7 7:5
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
%imm_u 12:s20 !function=ex_shift_12
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
# Argument sets:
target/riscv: Name the argument sets for all of insn32 formats Backports commit e761799796ac2211b9706753c459e117e7be58fa from qemu
2019-05-28 22:36:44 +00:00
&empty
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
&b imm rs2 rs1
target/riscv: Move gen_arith_imm() decoding into trans_* functions gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Backports commit 7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130 from qemu
2019-03-19 09:13:26 +00:00
&i imm rs1 rd
target/riscv: Name the argument sets for all of insn32 formats Backports commit e761799796ac2211b9706753c459e117e7be58fa from qemu
2019-05-28 22:36:44 +00:00
&j imm rd
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu
2019-03-19 09:17:50 +00:00
&r rd rs1 rs2
target/riscv: Name the argument sets for all of insn32 formats Backports commit e761799796ac2211b9706753c459e117e7be58fa from qemu
2019-05-28 22:36:44 +00:00
&s imm rs1 rs2
&u imm rd
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 20:04:46 +00:00
&shift shamt rs1 rd
target/riscv: Convert RV32A insns to decodetree Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu
2019-03-18 20:25:46 +00:00
&atomic aq rl rs2 rs1 rd
target/riscv: vector single-width integer add and subtract Backports 43740e3a3b3bb66456103684e622ba4e9baae297
2021-02-26 14:56:47 +00:00
&rmrr vm rd rs1 rs2
target/riscv: add vector amo operations Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d
2021-02-26 14:47:27 +00:00
&rwdvm vm wd rd rs1 rs2
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 07:44:17 +00:00
&r2nfvm vm rd rs1 nf
&rnfvm vm rd rs1 rs2 nf
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
# Formats 32:
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu
2019-03-19 09:17:50 +00:00
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
target/riscv: Move gen_arith_imm() decoding into trans_* functions gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Backports commit 7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130 from qemu
2019-03-19 09:13:26 +00:00
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
target/riscv: Name the argument sets for all of insn32 formats Backports commit e761799796ac2211b9706753c459e117e7be58fa from qemu
2019-05-28 22:36:44 +00:00
@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 20:04:46 +00:00
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
target/riscv: Convert RVXI csr insns to decodetree Backports commit 771fbe156a2a2be964a4fbe6251339a5570a26c4 from qemu
2019-03-18 20:16:32 +00:00
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 20:04:46 +00:00
target/riscv: Convert RV32A insns to decodetree Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu
2019-03-18 20:25:46 +00:00
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
target/riscv: Convert RV32F insns to decodetree Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 20:33:32 +00:00
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 07:44:17 +00:00
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
target/riscv: vector single-width integer add and subtract Backports 43740e3a3b3bb66456103684e622ba4e9baae297
2021-02-26 14:56:47 +00:00
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions 3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448
2021-02-26 15:19:44 +00:00
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
target/riscv: add vector amo operations Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d
2021-02-26 14:47:27 +00:00
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu
2021-02-26 07:35:14 +00:00
@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
target/riscv: Convert RV32F insns to decodetree Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 20:33:32 +00:00
target/riscv: Add hfence instructions Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu
2020-03-22 05:43:51 +00:00
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
target/riscv: Move the hfence instructions to the rvh decode Also correct the name of the VVMA instruction. Backports commit b8429ded723ec52568e05f6a24ed78c93224687c from qemu
2021-02-25 16:59:24 +00:00
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
target/riscv: Add hfence instructions Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu
2020-03-22 05:43:51 +00:00
target/riscv: Convert RV priv insns to decodetree Backports commit 4ba79c47a205b3af4b62b9b1b6090dee678a1069 from qemu
2019-03-19 08:40:17 +00:00
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
# *** Privileged Instructions ***
target/riscv: Add hfence instructions Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu
2020-03-22 05:43:51 +00:00
ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
target/riscv: Convert RV priv insns to decodetree Backports commit 4ba79c47a205b3af4b62b9b1b6090dee678a1069 from qemu
2019-03-19 08:40:17 +00:00
target/riscv: Activate decodetree and implemnt LUI & AUIPC for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 19:41:19 +00:00
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
target/riscv: Convert RVXI branch insns to decodetree Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 19:56:49 +00:00
auipc .................... ..... 0010111 @u
jal .................... ..... 1101111 @j
jalr ............ ..... 000 ..... 1100111 @i
beq ....... ..... ..... 000 ..... 1100011 @b
bne ....... ..... ..... 001 ..... 1100011 @b
blt ....... ..... ..... 100 ..... 1100011 @b
bge ....... ..... ..... 101 ..... 1100011 @b
bltu ....... ..... ..... 110 ..... 1100011 @b
bgeu ....... ..... ..... 111 ..... 1100011 @b
target/riscv: Convert RV32I load/store insns to decodetree Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 19:59:40 +00:00
lb ............ ..... 000 ..... 0000011 @i
lh ............ ..... 001 ..... 0000011 @i
lw ............ ..... 010 ..... 0000011 @i
lbu ............ ..... 100 ..... 0000011 @i
lhu ............ ..... 101 ..... 0000011 @i
sb ....... ..... ..... 000 ..... 0100011 @s
sh ....... ..... ..... 001 ..... 0100011 @s
sw ....... ..... ..... 010 ..... 0100011 @s
target/riscv: Convert RVXI arithmetic insns to decodetree we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 20:04:46 +00:00
addi ............ ..... 000 ..... 0010011 @i
slti ............ ..... 010 ..... 0010011 @i
sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
slli 00.... ...... ..... 001 ..... 0010011 @sh
srli 00.... ...... ..... 101 ..... 0010011 @sh
srai 01.... ...... ..... 101 ..... 0010011 @sh
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
slt 0000000 ..... ..... 010 ..... 0110011 @r
sltu 0000000 ..... ..... 011 ..... 0110011 @r
xor 0000000 ..... ..... 100 ..... 0110011 @r
srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
target/riscv: Convert RVXI fence insns to decodetree Backports commit 0c865e856a7e97d37c4dea4cf2ff875faa6e72ed from qemu
2019-03-18 20:06:49 +00:00
fence ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i ---- ---- ---- ----- 001 ----- 0001111
target/riscv: Convert RVXI csr insns to decodetree Backports commit 771fbe156a2a2be964a4fbe6251339a5570a26c4 from qemu
2019-03-18 20:16:32 +00:00
csrrw ............ ..... 001 ..... 1110011 @csr
csrrs ............ ..... 010 ..... 1110011 @csr
csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
target/riscv: Convert RVXM insns to decodetree Backports commit d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1 from qemu
2019-03-18 20:19:50 +00:00
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
mulhu 0000001 ..... ..... 011 ..... 0110011 @r
div 0000001 ..... ..... 100 ..... 0110011 @r
divu 0000001 ..... ..... 101 ..... 0110011 @r
rem 0000001 ..... ..... 110 ..... 0110011 @r
remu 0000001 ..... ..... 111 ..... 0110011 @r
target/riscv: Convert RV32A insns to decodetree Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu
2019-03-18 20:25:46 +00:00
# *** RV32A Standard Extension ***
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
target/riscv: Convert RV32F insns to decodetree Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 20:33:32 +00:00
# *** RV32F Standard Extension ***
flw ............ ..... 010 ..... 0000111 @i
fsw ....... ..... ..... 010 ..... 0100111 @s
fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
feq_s 1010000 ..... ..... 010 ..... 1010011 @r
flt_s 1010000 ..... ..... 001 ..... 1010011 @r
fle_s 1010000 ..... ..... 000 ..... 1010011 @r
fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
target/riscv: Convert RV32D insns to decodetree Backports commit 97f8b49372d73aab4d172df4ea297d7f3ce4e02e from qemu
2019-03-18 20:45:12 +00:00
# *** RV32D Standard Extension ***
fld ............ ..... 011 ..... 0000111 @i
fsd ....... ..... ..... 011 ..... 0100111 @s
fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
feq_d 1010001 ..... ..... 010 ..... 1010011 @r
flt_d 1010001 ..... ..... 001 ..... 1010011 @r
fle_d 1010001 ..... ..... 000 ..... 1010011 @r
fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
target/riscv: Move the hfence instructions to the rvh decode Also correct the name of the VVMA instruction. Backports commit b8429ded723ec52568e05f6a24ed78c93224687c from qemu
2021-02-25 16:59:24 +00:00
# *** RV32H Base Instruction Set ***
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu
2021-02-26 07:35:14 +00:00
# *** RV32V Extension ***
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 07:44:17 +00:00
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
target/riscv: add fault-only-first unit stride load The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Backports commit 022b4ecf775ffeff522eaea4f0d94edcfe00a0a9 from qemu
2021-02-26 14:27:07 +00:00
vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 07:44:17 +00:00
vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
target/riscv: add vector index load and store instructions Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Backports f732560e3551c0823cee52efba993fbb8f689a36
2021-02-26 07:59:41 +00:00
vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
# Vector ordered-indexed and unordered-indexed store insns.
vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
target/riscv: add vector amo operations Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d
2021-02-26 14:47:27 +00:00
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
target/riscv: add vector stride load and store instructions Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7
2021-02-26 07:44:17 +00:00
# *** new major opcode OP-V ***
target/riscv: vector single-width integer add and subtract Backports 43740e3a3b3bb66456103684e622ba4e9baae297
2021-02-26 14:56:47 +00:00
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector widening integer add and subtract Backports 8fcdf77630290591a6068c2d82ca2935338c3b0c
2021-02-26 15:05:40 +00:00
vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions 3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448
2021-02-26 15:19:44 +00:00
vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
target/riscv: vector bitwise logical instructions Backports d3842924cf93d104f691c5ea9090d6700ccef281
2021-02-26 15:30:30 +00:00
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector single-width bit shift instructions Backports 3277d955d21d8943d80062b4cfd8547f831dbd51
2021-02-26 15:37:07 +00:00
vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector integer comparison instructions 1366fc79be04fa56a0e3f078ba4f26c27ac67e89
2021-02-26 15:40:31 +00:00
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
target/riscv: vector single-width integer add and subtract Backports 43740e3a3b3bb66456103684e622ba4e9baae297
2021-02-26 14:56:47 +00:00
target/riscv: add vector configure instruction vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu
2021-02-26 07:35:14 +00:00
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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