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23 commits

Author SHA1 Message Date
LIU Zhiwei 0554e79ad1 target/riscv: support vector extension csr 
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.

Backports 8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a from qemu
 2021-02-26 02:25:58 -05:00
Zong Li 001d2e6a29 target/riscv: Fix the range of pmpcfg of CSR funcion table 
Backports commit 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d from qemu
 2021-02-25 23:35:21 -05:00
Alistair Francis 2584ab8ee5 target/riscv: Drop support for ISA spec version 1.09.1 
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Backports commit 1a9540d1f1a9c5022d9273d0244e5809679dd33b from qemu
 2020-06-14 22:23:26 -04:00
Anup Patel d47390ade4 target/riscv: Emulate TIME CSRs for privileged mode 
Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.

For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.

We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.

Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu
 2020-03-22 02:22:17 -04:00
Alistair Francis 835b025692 target/riscv: Add support for the 32-bit MSTATUSH CSR 
Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu
 2020-03-22 02:16:13 -04:00
Alistair Francis 4e7aaee31a target/riscv: Extend the SIP CSR to support virtulisation 
Backports commit a2e9f57d06279220b1834eca2494e52adae121b8 from qemu
 2020-03-22 01:35:11 -04:00
Alistair Francis 1fd49ac6f0 target/riscv: Extend the MIE CSR to support virtulisation 
Backports commit d0e53ce33ec8f66ffa597c634d50be73264aeadb from qemu
 2020-03-22 01:33:17 -04:00
Alistair Francis 6aabd67ef8 target/riscv: Set VS bits in mideleg for Hyp extension 
Backports commit 713d8363deb3774db14fb88a9fcd99687dcef114 from qemu
 2020-03-22 01:32:12 -04:00
Alistair Francis 042e3df075 target/riscv: Add Hypervisor machine CSRs accesses 
Backports commit 34cfb5f61842d495c6f6fc3eeb4197b5b44fd570 from qemu
 2020-03-22 01:26:47 -04:00
Alistair Francis dd356201a6 target/riscv: Add Hypervisor virtual CSRs accesses 
Backports commit 8747c9eeb2aaec8441d0900b198725ab33af4951 from qemu
 2020-03-22 01:24:42 -04:00
Alistair Francis 221c427fc3 target/riscv: Add Hypervisor CSR access functions 
Backports commit ff2cc1294cd8179d87de299b8e7a16bdb1e69523 from qemu
 2020-03-22 01:22:58 -04:00
Alistair Francis e4e41d3d87 target/riscv: Fix CSR perm checking for HS mode 
Update the CSR permission checking to work correctly when we are in
HS-mode.

Backports commit 0a42f4c4408824dc7cb9ff60c9bdce6dcc0d24a5 from qemu
 2020-03-22 01:19:04 -04:00
Alistair Francis 0198a09698 target/riscv: Add support for the new execption numbers 
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.

Backports commit ab67a1d07a4f6f1b4d577c5c47013273b9804551 from qemu
 2020-03-22 01:07:23 -04:00
Palmer Dabbelt 4a3d8417ca
RISC-V: Add support for the Zicsr extension 
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.

Backports commit 591bddea8d874e1500921de0353818e5586618f5 from qemu
 2019-08-08 17:10:34 -04:00
Alistair Francis 2ed6459e98
target/riscv: Add the mcountinhibit CSR 
1.11 defines mcountinhibit, which has the same numeric CSR value as
mucounteren from 1.09.1 but has different semantics. This patch enables
the CSR for 1.11-based targets, which is trivial to implement because
the counters in QEMU never tick (legal according to the spec).

Backports commit 747a43e818dc36bd50ef98c2b11a7c31ceb810fa from qemu
 2019-08-08 17:04:52 -04:00
Richard Henderson 47b797f1bb
target/riscv: Use env_cpu, env_archcpu 
Cleanup in the boilerplate that each target must define.
Replace riscv_env_get_cpu with env_archcpu. The combination
CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu
 2019-06-12 12:06:19 -04:00
Jonathan Behrens 1d6acaa604
target/riscv: Only flush TLB if SATP.ASID changes 
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Backports commit 1e0d985fa9136a563168a3da66f3d17820404ee2 from qemu
 2019-05-28 19:22:51 -04:00
Jonathan Behrens 7922aa54c0
target/riscv: More accurate handling of CSR 
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.

Backports commit 087b051a51a0c2a5bc1e8d435a484a8896b4176b from qemu
 2019-05-28 19:22:04 -04:00
Alistair Francis 47e4e047bc
target/riscv: Allow setting mstatus virtulisation bits 
Backports commit 1f0419cb0475eebdbefea67483e85287f3af07a7 from qemu
 2019-05-28 19:17:18 -04:00
Michael Clark d3dbcb6dfc
RISC-V: Add support for vectored interrupts 
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
 2019-03-19 23:58:31 -04:00
Michael Clark 2e0c040062
RISC-V: Allow interrupt controllers to claim interrupts 
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.

This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.

This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.

Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu
 2019-03-19 23:48:12 -04:00
Jim Wilson 65903cf9a4
RISC-V: Add debug support for accessing CSRs. 
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.

Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
 2019-03-19 23:42:48 -04:00
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target 
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
 2019-03-08 21:46:10 -05:00