Commit graph

5674 commits

Author SHA1 Message Date
Jonas d27ad4df1b
Added x86Msr functions for the go bindings (#986)
Backports commit d6d413187324e8d9dc852f62016863a44b240a7e from unicorn.
2019-03-08 02:28:37 -05:00
Nguyen Anh Quynh 7cad644235
bindings: update for latest ARM registers addition
Backports commit 07cafff76a3093376755e61124124f6f593d64c9 from unicorn
2019-03-08 02:27:24 -05:00
yhql 1723cb1015
Add ARM MSP, PSP and CONTROL register access (#1071)
Necessary for NVIC exception emulation from user.

Backports commit 31851280316d37305f412fff42f45bb375999074 from unicorn
2019-03-08 02:24:49 -05:00
Lioncash 8f688748c4
translate/i386: Restore Qemu's ordering of CPU and cache definitions
Like the previous two changes, this restores the layout of Qemu's
designated initializers.
2019-03-08 01:51:27 -05:00
Lioncash 1ddbb253e2
target/mips: Restore Qemu's organization of CPU definitions
Like 5075a0158a, this restores Qemu's
formatting of the processor tables to make it significantly less
annoying to maintain.
2019-03-08 01:40:50 -05:00
Lioncash 5075a0158a
target/arm: Restore Qemu's organization of coprocessor registers
These changes were mostly made in upstream unicorn for what I can guess,
was to support old versions of MSVC's compiler.

This is also a pain to maintain, since everything needs to be done
manually and can be a source of errors. It also makes it take more work
than it needs to, to backport changes from qemu.

Because of that, this change restores Qemu's organization of the
coprocessor registers.
2019-03-08 01:32:47 -05:00
Richard Henderson f116560d2c
target/arm: Implement ARMv8.5-FRINT
Backports 6bea25631af92531027d3bf3ef972a4d51d62e7c from qemu.
2019-03-05 23:17:33 -05:00
Richard Henderson f855ac073d
target/arm: Restructure handle_fp_1src_{single, double}
This will allow sharing code that adjusts rmode beyond
the existing users.

Backports commit 0e4db23d1fdbfed4fc1ec19b6e59820209600358 from qemu
2019-03-05 23:09:48 -05:00
Richard Henderson 94b5aab8f8
target/arm: Implement ARMv8.5-CondM
Backports commit 5ef84f111483e3f7b57efc690e22081ca8f99544 from qemu
2019-03-05 23:04:06 -05:00
Richard Henderson 1dfa15a683
target/arm: Implement ARMv8.4-CondM
Backports commit b89d9c988a988d5547c73e2bc43f59b0c07420a5 from qemu
2019-03-05 22:59:51 -05:00
Richard Henderson 65a3f3be5b
target/arm: Rearrange disas_data_proc_reg
This decoding more closely matches the ARMv8.4 Table C4-6,
Encoding table for Data Processing - Register Group.

In particular, op2 == 0 is now more than just Add/sub (with carry).

Backports commit 2fba34f70d9a81bab56e61bb99a4d6632bdfe531 from qemu
2019-03-05 22:55:27 -05:00
Richard Henderson 45c297c99b
target/arm: Add set/clear_pstate_bits, share gen_ss_advance
We do not need an out-of-line helper for manipulating bits in pstate.
While changing things, share the implementation of gen_ss_advance.

Backports commit 22ac3c49641f6eed93dca5b852030b4d3eacf6c4 from qemu
2019-03-05 22:55:22 -05:00
Richard Henderson 60742608f5
target/arm: Split helper_msr_i_pstate into 3
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
the unconditional write to pc and use raise_exception_ra to unwind.

Backports commit ff730e9666a716b669ac4a8ca7c521177d1d2b15 from qemu
2019-03-05 22:45:11 -05:00
Richard Henderson 5d42ca6a65
target/arm: Implement ARMv8.0-PredInv
Backports commit cb570bd318beb2ecce83cabf8016dacceb824dce from qemu
2019-03-05 22:37:57 -05:00
Richard Henderson 1721e429c2
target/arm: Implement ARMv8.0-SB
Backports commit 9888bd1e20425dfe4dcca5dcd1ca2fac8e90ad19 from qemu
2019-03-05 22:35:16 -05:00
Richard Henderson a552a7b2e0
target/arm: Split out arm_sctlr
Minimize the number of places that will need updating when
the virtual host extensions are added.

Backports commit 64e40755cd41fbe8cd266cf387e42ddc57a449ef from qemu
2019-03-05 22:29:25 -05:00
Richard Henderson fa70a2bc69
target/arm: Fix PC test for LDM (exception return)
Found by inspection: Rn is the base register against which the
load began; I is the register within the mask being processed.
The exception return should of course be processed from the loaded PC.

Backports commit 9d090d17234058f55c3c439d285db78c94d7d4de from qemu
2019-03-05 22:27:38 -05:00
Lioncash 7a6f61057b
target/m68k: Correct instruction emulation
Previously we weren't even initializing the instruction table, so any
attempt at emulation would cause a segmentation fault.

This also moves the end address check after the decoding to correctly
perform exiting behavior with the new translator model.
2019-02-28 19:21:49 -05:00
Lioncash 0868015992
target/arm: Move TCGContext variable within arm_post_translate_insn into a narrower scope
This is only used within the scope of the if statement, so we can just
move it there.
2019-02-28 18:53:33 -05:00
Lioncash 15440a83c5
target/arm: Fix execution of ARM instructions
Previously we'd be checking prior to the actual decoding if we were at
the ending address. This worked fine using the old model of the
translation process in qemu. However, this causes the wrong behavior to
occur in both ARM and Thumb/Thumb-2 modes using the newer translator
model.

Given the translator itself checks for the end address already, this
needs to be placed within arm_post_translate_insn().

This prevents the emulation process being off-by-one as well when it
comes to actually executing the instructions.
2019-02-28 18:49:22 -05:00
Lioncash dcc9420555
Add missing x86_vec regression test
This was initially supposed to be bundled with the changes in the
backported commit: 5bf6d77e4ee258c67c2d7ead94cf266a7b9773e7
2019-02-28 17:08:19 -05:00
dmarxn 7164ab5ff4
changed cpu_compue_eflags to use the updated eflags variable. Otherwise, cli/sti and popfl may break, as we get the non-updated eflags (#1057)
Backports commit 360e9c60e1feb4a93e7e43f30858e38eac2d35f2 from unicorn
2019-02-28 17:05:13 -05:00
nanoric 245d2070fe
[Fix] Add feature support for CMPXCHG16B instruction. (#983)
Backports commit 2a240079d8fa4f1c77208379338c676ac6bf18ce from unicorn
2019-02-28 17:03:08 -05:00
Guillaume Sottas b7628f215c
fix invalid script path (#975) (#976)
* fix invalid script path (#975)

* expose target_page_align and target_page_size to public API.

* add newly exposed values to python binding.

* Revert "expose target_page_align and target_page_size to public API."

This reverts commit 38145bbaba26900118809c6179164d060b8e73e5.

* Revert "add newly exposed values to python binding."

This reverts commit 0884e06527155799494138733557adaf2f4fe71c.

* add python2-setuptools in required cygwin packages.

* Revert "fix invalid script path (#975)"

This reverts commit 8c55ca7d3447824fb672ab83ff4af5aee9ec089d

Backports commit cf0bcb82b465ec521235ba819a8eba5c46748ddd from unicorn
2019-02-28 17:02:06 -05:00
Disconnect3d 68e17c03dc
Fix naming in Python sample_x86.py (#961)
Backports commit 19ffa83d4353af8834c4c55590ca2ecd357a6bbe from unicorn.
2019-02-28 17:01:10 -05:00
Duncan Ogilvie 8bbe074251
Update dotnet bindings (#973)
Backports commit 0b3cd70e67ef8cd564e86f502a411d4e98b9f752 from unicorn.
2019-02-28 17:00:25 -05:00
Jeremy Sears c3c6e250e4
Fix Java Makefile on Darwin (#936)
* Fixes the logic for Dylib extensions on macOS.
* Adds an uninstall task and documentation.

Backports commit 94b116877670ed9bbe38b71e3b9ad28f10cb3775 from unicorn
2019-02-28 16:58:03 -05:00
Brian McKenna 07f315af47
Haskell bindings: use ExceptT instead of deprecated EitherT (#1034)
Backports commit 873fffc505b29c6179a8aece18b7e331e5f879e8 from unicorn.
2019-02-28 16:54:02 -05:00
nanoric 9e8e5645fc
[Fix] Fix a problem that use uc_reg_write to write fs, gs has no effets in x86 64-bit mode. (#984)
Backports commit a2493a0d4121b671fe9d16e41a9bdd3307b7b1ef from unicorn.
2019-02-28 16:52:54 -05:00
BrunoPujos 1d4bfd9aca
i386: set MSR IA32_EFER to correct value at init for IA32e Mode (#1047)
Backports commit 536c4e77c4350fac3e5c2b9b57d8c16f69b934d3 from unicorn.
2019-02-28 16:49:31 -05:00
Diego Argueta 50a570e126
Add Lua binding to README (#1050)
Closes https://github.com/dargueta/unicorn-lua/issues/1

Backports commit f2438188069e31d637666e72dcddd13cef0e684e from qemu
2019-02-28 16:48:20 -05:00
kj.xwings.l 15d52aefbe
update python binding samples, shellcode.py with 64bit syscall (#1052)
* update python binding samples, shellcode.py with 64bit syscall

* fix with quynh comments

* fix with more q comments

* reformatted

* reformatted and moved file

* reformatted and moved file

* delete file

* delete dead code

* deleted more dead code

* deleted more dead code / fix bugs

* fix 64bit eip intno eax

* rearrage rip

* Inconsistent print

Backports commit 8c6cbe3f3cabed57b23b721c29f937dd5baafc90 from unicorn.
2019-02-28 16:47:23 -05:00
Nguyen Anh Quynh 7bb8554242
bindings: update after recent addition of ARM_REG_IPSR
Backports 6d47b38b7f8b6de0ee96a93a91180fafe2f01525 from unicorn
2019-02-28 16:44:43 -05:00
cfrantz 5ad3a0ea82
Add support for the ARM IPSR register. (#1067)
1. Create an enum name for the IPSR register.
2. Implement read and write of the IPSR via the xpsr helper functions.

Fixes #1065

Backports commit 6c319941a5462ee3a4af4593c371f5674394d6ce from unicorn.
2019-02-28 16:40:54 -05:00
Coldzer0 c1267811e2
Pascal/Delphi binding
* Pascal/Delphi binding

Pascal/Delphi language binding

* update credits

Backports commit 84220d83601ba929c56b9e1fadd1686e02cbb93c from unicorn.
2019-02-28 16:36:56 -05:00
Nguyen Anh Quynh 8c8852b914
bindings: add newly added register MXCSR
Backports commit 738d10298952d195799ce16721feffe5cb8f07bb from unicorn.
2019-02-28 16:34:51 -05:00
dmarxn cdcd026413
target/i386: Added MXCSR register, fixed writing to FPUCW. (#1059)
* Added MXCSR register for reading and writing
* Changed writing for fpucw register, now the qemu rounding status is updated as well

Backports commit 256e7782ceafb1f8915da167040d5368c38f9585 from unicorn
2019-02-28 16:31:22 -05:00
Lioncash 2b5d424ded
target/mips: Amend botched rename 2019-02-28 16:21:09 -05:00
Mateja Marjanovic d50a1fef6b
target/mips: Preparing for adding MMI instructions
Set up MMI code to be compiled only for TARGET_MIPS64. This is
needed so that GPRs are 64 bit, and combined with MMI registers,
they will form full 128 bit registers.

Backports commit 37b9aae2e6e005e6df206a0b4804972460806166 from qemu
2019-02-28 16:15:47 -05:00
Richard Henderson fbe1ee25ff
target/arm: Enable ARMv8.2-FHM for -cpu max
Backports commit 991c05995a7bbafbebc1e4d405e947f2edcee063 from qemu
2019-02-28 15:47:03 -05:00
Richard Henderson 4ae3ff8e61
target/arm: Implement VFMAL and VFMSL for aarch32
Backports commit 87732318c5d68a366fc2d6fc394d9c20412099fa from qemu
2019-02-28 15:44:59 -05:00
Richard Henderson 625d3f3cfb
target/arm: Implement FMLAL and FMLSL for aarch64
Backports commit 0caa5af802ff622c854ff4ee2e2b8cdd135b4d73 from qemu
2019-02-28 15:36:41 -05:00
Richard Henderson 5473c3603f
target/arm: Add helpers for FMLAL
Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected. Thus float16_to_float32_by_bits.

Backports commit a4e943a716d5fac923d82df3eabc65d1e3624019 from qemu
2019-02-28 15:31:48 -05:00
Peter Maydell 82b8e97f76
target/arm: Gate "miscellaneous FP" insns by ID register field
There is a set of VFP instructions which we implement in
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
These were all first introduced in v8 for A-profile, but in
M-profile they appeared in v7M. Gate them on the MVFR2
FPMisc field instead, and rename the function appropriately.

Backports commit c0c760afe800b60b48c80ddf3509fec413594778 from qemu
2019-02-28 15:26:27 -05:00
Peter Maydell 118a2bde5c
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.

This change doesn't alter behaviour for any of our CPUs.

Backports commit 602f6e42cfbfe9278be34e9b91d2ceb695837e02 from qemu
2019-02-28 15:23:51 -05:00
Lioncash 4f210d0731
header_gen: Add float128_to_uint32 to the list
Avoids multiple definition errors.
2019-02-28 15:19:44 -05:00
Richard Henderson 11679ff3cf
softfloat: Support float_round_to_odd more places
Previously this was only supported for roundAndPackFloat64.

New support in round_canonical, round_to_int, float128_round_to_int,
roundAndPackFloat32, roundAndPackInt32, roundAndPackInt64,
roundAndPackUint64. This does not include any of the floatx80 routines,
as we do not have users for that rounding mode there.

Backports commit 5d64abb32ffe558e616545819f3e53dd66335994 from qemu
2019-02-28 15:17:38 -05:00
David Hildenbrand 7373819b1a
softfloat: Implement float128_to_uint32
Handling it just like float128_to_uint32_round_to_zero, that hopefully
is free of bugs :)

Documentation basically copied from float128_to_uint64

Backports commit e45de9922e43c1ce4f4739b62142314a13029d5c from qemu
2019-02-28 15:13:09 -05:00
David Hildenbrand 24a2bd702c
softfloat: add float128_is_{normal,denormal}
Needed on s390x, to test for the data class of a number. So it will
gain soon a user.

A number is considered normal if the exponent is neither 0 nor all 1's.
That can be checked by adding 1 to the exponent, and comparing against
>= 2 after dropping an eventual overflow into the sign bit.

While at it, convert the other floatXX_is_normal functions to use a
similar, less error prone calculation, as suggested by Richard H.

Backports commit 47393181604d507f4fe2a15a65b1eede0f974d6a from qemu
2019-02-28 15:11:50 -05:00
Lioncash b9da32241b
header_gen: Correct multiple definition errors 2019-02-27 17:03:28 -05:00