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unicorn/qemu/target/arm
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Dongjiu Geng 4dc3d59fd3
target/arm: change arch timer registers access permission 
Some generic arch timer registers are Config-RW in the EL0,
which means the EL0 exception level can have write permission
if it is appropriately configured.

When VM access registers, QEMU firstly checks whether they have RW
permission, then check whether it is appropriately configured.
If they are defined to read only in EL0, even though they have been
appropriately configured, they still do not have write permission.
So need to add the write permission according to ARMV8 spec when
define it.

Backports commit daf1dc5f82cefe2a57f184d5053e8b274ad2ba9a from qemu
2019-03-19 05:40:44 -04:00
..
arm-powerctl.c arm: Clarify the logic of set_pc() 2019-02-03 17:55:30 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2018-03-02 00:20:11 -05:00
cpu-qom.h target/arm: Add "-cpu max" support 2018-03-12 10:11:49 -04:00
cpu.c target/arm: Implement ARMv8.0-PredInv 2019-03-05 22:37:57 -05:00
cpu.h target/arm: Implement ARMv8.5-FRINT 2019-03-05 23:17:33 -05:00
cpu64.c target/arm: Restore Qemu's organization of coprocessor registers 2019-03-08 01:32:47 -05:00
crypto_helper.c target/arm/cpu and crypto_helper: Correct bad merge and adjust to qemu code style 2018-03-12 11:57:24 -04:00
helper-a64.c target/arm: Split helper_msr_i_pstate into 3 2019-03-05 22:45:11 -05:00
helper-a64.h target/arm: Split helper_msr_i_pstate into 3 2019-03-05 22:45:11 -05:00
helper-sve.h target/arm: Rewrite vector gather first-fault loads 2018-10-08 14:15:15 -04:00
helper.c target/arm: change arch timer registers access permission 2019-03-19 05:40:44 -04:00
helper.h target/arm: Implement ARMv8.5-FRINT 2019-03-05 23:17:33 -05:00
internals.h target/arm: Split helper_msr_i_pstate into 3 2019-03-05 22:45:11 -05:00
iwmmxt_helper.c target/arm: Untabify iwmmxt_helper.c 2018-08-25 04:33:44 -04:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
Makefile.objs target/arm: Split out vfp_helper.c 2019-02-22 18:48:44 -05:00
neon_helper.c target/arm: Split out FPSCR.QC to a vector field 2019-02-15 18:04:13 -05:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c target/arm: Add set/clear_pstate_bits, share gen_ss_advance 2019-03-05 22:55:22 -05:00
pauth_helper.c target/arm: Implement pauth_computepac 2019-01-22 16:35:07 -05:00
psci.c fix WFI/WFE length in syndrome register 2018-03-05 11:21:51 -05:00
sve.decode target/arm: SVE brk[ab] merging does not have s bit 2019-01-13 19:39:34 -05:00
sve_helper.c sve_helper: Use the QEMU_FLATTEN macro instead of the compiler attribute directly 2018-10-23 13:05:02 -04:00
translate-a64.c target/arm: Implement ARMv8.5-FRINT 2019-03-05 23:17:33 -05:00
translate-a64.h arm: Take DisasContext as a parameter instead of TCGContext where applicable 2018-10-06 04:17:12 -04:00
translate-sve.c target/arm: Rely on optimization within tcg_gen_gvec_or 2019-02-15 17:50:28 -05:00
translate.c target/arm: Add set/clear_pstate_bits, share gen_ss_advance 2019-03-05 22:55:22 -05:00
translate.h target/arm: Add set/clear_pstate_bits, share gen_ss_advance 2019-03-05 22:55:22 -05:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
unicorn_arm.c Add ARM MSP, PSP and CONTROL register access (#1071) 2019-03-08 02:24:49 -05:00
vec_helper.c target/arm: Add helpers for FMLAL 2019-02-28 15:31:48 -05:00
vfp_helper.c target/arm: Implement ARMv8.5-FRINT 2019-03-05 23:17:33 -05:00