Commit graph

3305 commits

Author SHA1 Message Date
Sergey Sorokin 4a904baaf5
target-arm: Add missed AArch32 TLBI sytem registers
Some PL2 related TLBI system registers are missed in AArch32
implementation. The patch fixes it.

Backports commit 541ef8c2e73fb99d173b125bef7c262fdd2fe33c from qemu
2018-02-25 19:59:15 -05:00
Peter Lieven 799bf1c3a5
exec: avoid realloc in phys_map_node_reserve
this is the first step in reducing the brk heap fragmentation
created by the map->nodes memory allocation. Since the introduction
of RCU the freeing of the PhysPageMaps is delayed so that sometimes
several hundred are allocated at the same time.

Even worse the memory for map->nodes is allocated and shortly
afterwards reallocated. Since the number of nodes it grows
to in the end is the same for all PhysPageMaps remember this value
and at least avoid the reallocation.

The large number of simultaneous allocations (about 450 x 70kB in
my configuration) has to be addressed later.

Backports commit 101420b886eec36990419bc9ed5b503622af8a0d from qemu
2018-02-25 19:32:40 -05:00
Paolo Bonzini a47c68164d
compiler: never omit assertions if using a static analysis tool
Assertions help both Coverity and the clang static analyzer avoid
false positives, but on the other hand both are confused when
the condition is compiled as (void)(x != FOO). Always expand
assertion macros when using Coverity or clang, through a new
QEMU_STATIC_ANALYSIS preprocessor symbol.

This fixes a couple false positives in TCG.

Backports commit 8bff06a0bbf257a2083223534c1607bf87d913e6 from qemu
2018-02-25 19:19:28 -05:00
Vijay 5608b53b6f
target-arm: Use Neon for zero checking
Use Neon instructions to perform zero checking of
buffer. This is helps in reducing total migration time.

Use case: Idle VM live migration with 4 VCPUS and 8GB ram
running CentOS 7.

Without Neon, the Total migration time is 3.5 Sec

Migration status: completed
total time: 3560 milliseconds
downtime: 33 milliseconds
setup: 5 milliseconds
transferred ram: 297907 kbytes
throughput: 685.76 mbps
remaining ram: 0 kbytes
total ram: 8519872 kbytes
duplicate: 2062760 pages
skipped: 0 pages
normal: 69808 pages
normal bytes: 279232 kbytes
dirty sync count: 3

With Neon, the total migration time is 2.9 Sec

Migration status: completed
total time: 2960 milliseconds
downtime: 65 milliseconds
setup: 4 milliseconds
transferred ram: 299869 kbytes
throughput: 830.19 mbps
remaining ram: 0 kbytes
total ram: 8519872 kbytes
duplicate: 2064313 pages
skipped: 0 pages
normal: 70294 pages
normal bytes: 281176 kbytes
dirty sync count: 3

Backports commit 7069532e3b944c25707d4f69998e68a739eabff9 from qemu
2018-02-25 19:17:38 -05:00
Richard Henderson d17dc29d2e
target-sparc: Elide duplicate updates to fprs
Backports commit f9c816c00cf4242542472ae6b2a579b11b7e86f1 from qemu
2018-02-25 19:14:59 -05:00
Richard Henderson 2215ef7e21
target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptions
This avoids needing to save state before every FP operation.

Backports commit 02c79d78853f07d519b3272d06e43041eb4a4105 from qemu
2018-02-25 19:12:36 -05:00
Richard Henderson 524e4af5ca
target-sparc: Use cpu_fsr in stfsr
Backports commit ba2397d1ca6546e8cf5bd9e2939923546ac3091a from qemu
2018-02-25 19:10:27 -05:00
Lioncash 17c54e2702
header_gen: alphabetize general symbols 2018-02-25 19:07:20 -05:00
Lioncash 4b8cae3f61
header_gen: alphabetize ARM symbols 2018-02-25 19:00:31 -05:00
Lioncash fa10382007
header_gen: alphabetize aarch64 symbols 2018-02-25 19:00:01 -05:00
Lioncash 3f8802fcf5
header_gen: alphabetize MIPS symbols 2018-02-25 18:59:49 -05:00
Richard Henderson 12eecc4939
target-sparc: Use explicit writes to cpu_fsr
By arranging for explicit writes to cpu_fsr after floating point
operations, we are able to mark the helpers as not writing to
tcg globals, which means that we don't need to invalidate the
integer register set across said calls.

Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
2018-02-25 18:55:07 -05:00
Richard Henderson 2e24c09db3
target-sparc: Remove helper_ldf_asi, helper_stf_asi
We've now implemented all fp asis inline, except for the no-fault
memory reads. The latter can be passed directly to helper_ld_asi.

Backports commit f2fe396f0fae6b389169f65abf294df9ae6cfee5 from qemu
2018-02-25 18:32:35 -05:00
Richard Henderson a921273a6c
target-sparc: Directly implement block and short ldf/stf asis
Backports commit ca5ce5723fb1ee3445f690004f63c209c15fb813 from qemu
2018-02-25 18:27:52 -05:00
Richard Henderson 333d88c9e6
target-sparc: Directly implement easy ldf/stf asis
Backports commit 7705091ca4a20c8c2d20e2af5d0a1bcb17296657 from qemu
2018-02-25 18:23:45 -05:00
Richard Henderson 9d47cda44c
target-sparc: Pass TCGMemOp constants to helper_ld/st_asi
Reduces the argument count for helper_ld_asi; do helper_st_asi
for consistency.

Backports commit 6850811e7c56403b0d225a1bffd096abf2ff06f9 from qemu
2018-02-25 18:19:42 -05:00
Richard Henderson 950aa89c7a
target-sparc: Fix obvious error in ASI_M_BFILL
Backports commit c095b83f9836cef80f64b32603fea240762a824b from qemu
2018-02-25 18:08:40 -05:00
Richard Henderson eb285aa281
target-sparc: Directly implement easy ldd/std asis
Backports commit e4dc0052a40d3e7b00ca0b008f345e2ed644aa20 from qemu
2018-02-25 18:07:51 -05:00
Richard Henderson 1ed7df7720
target-sparc: Introduce gen_check_align
Backports commit 35e94905ce4b39b358a673995f9bee11f46ec8be from qemu
2018-02-25 17:59:47 -05:00
Richard Henderson cef4ae5ca8
target-sparc: Use QT0 to return results from ldda
Also implement a few more twinx asis.

Backports commit 3f4288ebf6fca7b266fa42a74d9d99b961ba6844 from qemu
2018-02-25 17:56:08 -05:00
Richard Henderson 9e402493a9
target-sparc: Directly implement easy ld/st asis
Backports commit f0913be04be13cfb4f9341ae79e035fc8479fd28 from qemu
2018-02-25 17:49:16 -05:00
Richard Henderson e2d0ee1286
target-sparc: Use defines from asi.h
Backports commit 0cc1f4bf76a20c7fee0bab5c9bba9ad7302198b5 from qemu
2018-02-25 17:44:36 -05:00
Richard Henderson bd3b7a2537
target-sparc: Add UA2005 defines to asi.h
Backports commit 1d854963ea340855efe3f8a5b99c95a75bd717ae from qemu
2018-02-25 17:32:46 -05:00
Richard Henderson b9a65e0e79
target-sparc: Import linux/arch/sparc/include/uapi/asm/asi.h
Copied from tag v4.2, 64291f7db5bd8150a74ad2036f1037e6a0428df2.

Backports commit 68a03b8c8853c66724c6f200af3f821ae0d7e934 from qemu
2018-02-25 17:29:51 -05:00
Richard Henderson c509a5562d
target-sparc: Pass TCGMemOp to gen_ld/st_asi
Backports commit 1d65b0f5bb8f32500bbce09d922d226bb7cf4c68 from qemu
2018-02-25 17:26:34 -05:00
Richard Henderson 4bc53f223c
target-sparc: Introduce get_asi
Replace gen_get_asi, and use it for both 32-bit and 64-bit.
For v8, do supervisor and immediate checks here.

Also, move save_state and TB ending into the respective
subroutines, out of disas_sparc_insn.

Backports commit 7ec1e5ea4bd0700fa48da86bffa2fcc6146c410a from qemu
2018-02-25 17:23:20 -05:00
Richard Henderson 1dcd14d434
target-sparc: Store %asi in TB flags
Knowing the value of %asi at translation time means that we
can handle the common settings without a function call.

The steady state appears to be %asi == ASI_P, so that sparcv9
code can use offset forms of lda/sta. The %asi register gets
pushed and popped on entry to certain functions, but it rarely
takes on values other than ASI_P or ASI_AIUP. Therefore we're
unlikely to be expanding the set of TBs created.

Backports commit a6d567e523ed7e928861f3caa5d49368af3f330d from qemu
2018-02-25 05:17:21 -05:00
Richard Henderson 080281bc9c
target-sparc: Unify asi handling between 32 and 64-bit
We now have a single copy of gen_ld_asi, gen_st_asi,
gen_swap_asi, and everything uses gen_get_asi.

Backports commit 22e700607aeaff5f5e139d0fdc3d861e5502040c from qemu
2018-02-25 05:11:52 -05:00
Richard Henderson 847d65258b
target-sparc: Create gen_exception
This unifies quite a few duplicate code fragments.

Backports commit 4fbe00679000f9fd0c509c2d548d957b08ec6057 from qemu
2018-02-25 04:55:16 -05:00
Richard Henderson 39d1657fc3
target-sparc: Store mmu index in TB flags
Doing this instead of saving the raw PS_PRIV and TL. This means
that all nucleus mode TBs (TL > 0) can be shared. This fixes a
bug in that we didn't include HS_PRIV in the TB flags, and so could
produce incorrect TB matches for hypervisor state.

The LSU and DMMU states were unused by the translator. Including
them in TB flags meant unnecessary mismatches from tb_find_fast.

Backports commit 99a230638a3674e921224dbe628159c867d734b1 from qemu
2018-02-25 04:51:50 -05:00
Richard Henderson 395e00cdc5
target-sparc: Remove softint as a TCG global
The global is only ever read for one insn; we can just as well
use a load from env instead and generate the same code. This
also allows us to indicate the the associated helpers do not
touch TCG globals.

Backports commit e86ceb0d652baa5738e05a59ee0e7989dafbeaa1 from qemu
2018-02-25 04:49:27 -05:00
Richard Henderson dcd1d6f8ce
target-sparc: Mark more flags for helpers
Quite a few helpers do not modify tcg globals but did not so indicate.

Backports commit be72f9fcca742c5e9a949f5eac901ed6cc26a2a0 from qemu
2018-02-25 04:28:54 -05:00
Markus Armbruster c2ffbc575d
Clean up decorations and whitespace around header guards
Cleaned up with scripts/clean-header-guards.pl.

Backports commit 175de52487ce0b0c78daa4cdf41a5a465a168a25 from qemu
2018-02-25 04:26:02 -05:00
Markus Armbruster 1275b9b459
Clean up ill-advised or unusual header guards
Cleaned up with scripts/clean-header-guards.pl.

Backports commit 2a6a4076e117113ebec97b1821071afccfdfbc96 from qemu
2018-02-25 04:22:46 -05:00
Markus Armbruster 9ae2fc4d9e
Clean up header guards that don't match their file name
Header guard symbols should match their file name to make guard
collisions less likely. Offenders found with
scripts/clean-header-guards.pl -vn.

Cleaned up with scripts/clean-header-guards.pl, followed by some
renaming of new guard symbols picked by the script to better ones.

Backports commit 121d07125bb6d7079c7ebafdd3efe8c3a01cc440 from qemu
2018-02-25 04:18:42 -05:00
Markus Armbruster 25ec9ab016
tcg: Clean up tcg-target.h header guards
These use guard symbols like TCG_TARGET_$target.
scripts/clean-header-guards.pl doesn't like them because they don't
match their file name (they should, to make guard collisions less
likely).

Clean them up: use guard symbol $target_TCG_TARGET_H for
tcg/$target/tcg-target.h.

Backports commit 14e54f8ecfe9c5e17348f456781344737ed10b3b from qemu
2018-02-25 04:15:08 -05:00
Markus Armbruster 2b65f98538
target-*: Clean up cpu.h header guards
Most of them use guard symbols like CPU_$target_H, but we also have
__MIPS_CPU_H__ and __TRICORE_CPU_H__. They all upset
scripts/clean-header-guards.pl.

The script dislikes CPU_$target_H because they don't match their file
name (they should, to make guard collisions less likely). The others
are reserved identifiers.

Clean them all up: use guard symbol $target_CPU_H for
target-$target/cpu.h.

Backports commit 07f5a258750b3b9a6e10fd5ec3e29c9a943b650e from qemu
2018-02-25 04:12:46 -05:00
Markus Armbruster 60e8836b74
Use #include "..." for our own headers, <...> for others
Tracked down with an ugly, brittle and probably buggy Perl script.

Also move includes converted to <...> up so they get included before
ours where that's obviously okay.

Backports commit a9c94277f07d19d3eb14f199c3e93491aa3eae0e from qemu
2018-02-25 04:10:33 -05:00
Peter Maydell f6f843b4d4
bswap.h: Document cpu_to_* and *_to_cpu conversion functions
Add a documentation comment describing the functions for
converting between the cpu and little or bigendian formats.

Backports commit 7d820b766a2049f33ca7e078aa51018f2335f8c5 from qemu
2018-02-25 04:06:28 -05:00
Peter Maydell 1d7f813942
bswap.h: Remove unused cpu_to_*w() and *_to_cpup()
Now that all uses of cpu_to_*w() and *_to_cpup() have been replaced
with either ld*_p()/st*_p() or by doing direct dereferences and
using the cpu_to_*()/*_to_cpu() byteswap functions, we can remove
the unused implementations.

Backports commit f76bde702916d0230bf359d478bcac8d7f3b30ae from qemu
2018-02-25 04:04:46 -05:00
Sergey Sorokin d1e4ac0451
Fix confusing argument names in some common functions
There are functions tlb_fill(), cpu_unaligned_access() and
do_unaligned_access() that are called with access type and mmu index
arguments. But these arguments are named 'is_write' and 'is_user' in their
declarations. The patches fix the arguments to avoid a confusion.

Backports commit b35399bb4e9968296a12303b00f9f2066470e987 from qemu
2018-02-25 03:58:27 -05:00
Leon Alrae a465707a47
target-mips: enable 10-bit ASIDs in I6400 CPU
Backports commit cdc46fab07a122dfcc8a1054510a68d936ae3440 from qemu
2018-02-25 03:50:58 -05:00
Paul Burton 002b392a15
target-mips: support CP0.Config4.AE bit
The read-only Config4.AE bit set denotes extended 10 bits ASID.

Backports commit a0c8060841f2d56fb3504292c18522b957972e4c from qemu
2018-02-25 03:49:36 -05:00
Paul Burton ba4dcc8c2f
target-mips: change ASID type to hold more than 8 bits
ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.

Backports commit 2d72e7b047d800c9f99262466f65a98684ecca14 from qemu
2018-02-25 03:48:10 -05:00
Paul Burton ac27c881ff
target-mips: add ASID mask field and replace magic values
Backports commit 6ec98bd7b64ad75870c8e9d87a90fcd1a64b4942 from qemu
2018-02-25 03:44:26 -05:00
Leon Alrae 7e589c117b
target-mips: replace MIPS64R6-generic with the real I6400 CPU model
MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename
it to make it clear which MIPS processor it is supposed to emulate.

Backports commit 8f95ad1c79b4166350b982a6defe0e21faa04dac from qemu
2018-02-25 03:35:55 -05:00
Leon Alrae c0b3938b88
target-mips: add exception base to MIPS CPU
Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.

Backports commit 89777fd10fc3dd573c3b4d1b2efdd10af823c001 from qemu
2018-02-25 03:22:10 -05:00
Stanislav Shmarov 6f20d35cd1
translate-all: Fix user-mode self-modifying code in 2 page long TB
In user-mode emulation Translation Block can consist of 2 guest pages.
In that case QEMU also mprotects 2 host pages that are dedicated for
guest memory, containing instructions. QEMU detects self-modifying code
with SEGFAULT signal processing.

In case if instruction in 1st page is modifying memory of 2nd
page (or vice versa) QEMU will mark 2nd page with PAGE_WRITE,
invalidate TB, generate new TB contatining 1 guest instruction and
exit to CPU loop. QEMU won't call mprotect, and new TB will cause
same SEGFAULT. Page will have both PAGE_WRITE_ORG and PAGE_WRITE
flags, so QEMU will handle the signal as guest binary problem,
and exit with guest SEGFAULT.

Solution is to do following: In case if current TB was invalidated
continue to invalidate TBs from remaining guest pages and mark pages
as PAGE_WRITE. After that disable host page protection with mprotect.
If current tb was invalidated longjmp to main loop. That is more
efficient, since we won't get SEGFAULT when executing new TB.

Backports commit 7399a337e4126f7c8c8af3336726f001378c4798 from qemu
2018-02-25 03:14:22 -05:00
Samuel Damashek 670d81367b
cputlb: Fix for self-modifying writes across page boundaries
As it currently stands, QEMU does not properly handle self-modifying code
when the write is unaligned and crosses a page boundary. The procedure
for handling a write to the current translation block is to write-protect
the current translation block, catch the write, split up the translation
block into the current instruction (which remains write-protected so that
the current instruction is not modified) and the remaining instructions
in the translation block, and then restore the CPU state to before the
write occurred so the write will be retried and successfully executed.
However, since unaligned writes across pages are split into one-byte
writes for simplicity, writes to the second page (which is not the
current TB) may succeed before a write to the current TB is attempted,
and since these writes are not invalidated before resuming state after
splitting the TB, these writes will be performed a second time, thus
corrupting the second page. Credit goes to Patrick Hulin for
discovering this.

In recent 64-bit versions of Windows running in emulated mode, this
results in either being very unstable (a BSOD after a couple minutes of
uptime), or being entirely unable to boot. Windows performs one or more
8-byte unaligned self-modifying writes (xors) which intersect the end
of the current TB and the beginning of the next TB, which runs into the
aforementioned issue. This commit fixes that issue by making the
unaligned write loop perform the writes in forwards order, instead of
reverse order. This way, QEMU immediately tries to write to the current
TB, and splits the TB before any write to the second page is executed.
The write then proceeds as intended. With this patch applied, I am able
to boot and use Windows 7 64-bit and Windows 10 64-bit in QEMU without
KVM.

Per Richard Henderson's input, this patch also ensures the second page
is in the TLB before executing the write loop, to ensure the second
page is mapped.

The original discussion of the issue is located at
http://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg02161.html.

Backports commit 81daabaf7a572f138a8b88ba6eea556bdb0cce46 from qemu
2018-02-25 03:12:11 -05:00
Samuel Damashek 04c423b081
cputlb: Add address parameter to VICTIM_TLB_HIT
Backports commit a390284b80d2b6581143cdb40666674e60e635ae from qemu
2018-02-25 03:03:36 -05:00