Commit graph

115 commits

Author SHA1 Message Date
Paul Burton 002b392a15
target-mips: support CP0.Config4.AE bit
The read-only Config4.AE bit set denotes extended 10 bits ASID.

Backports commit a0c8060841f2d56fb3504292c18522b957972e4c from qemu
2018-02-25 03:49:36 -05:00
Paul Burton ac27c881ff
target-mips: add ASID mask field and replace magic values
Backports commit 6ec98bd7b64ad75870c8e9d87a90fcd1a64b4942 from qemu
2018-02-25 03:44:26 -05:00
Leon Alrae c0b3938b88
target-mips: add exception base to MIPS CPU
Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.

Backports commit 89777fd10fc3dd573c3b4d1b2efdd10af823c001 from qemu
2018-02-25 03:22:10 -05:00
Aleksandar Markovic 4a540f88de
target-mips: Implement FCR31's R/W bitmask and related functionalities
This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:

- Add fields that will keep FCR31's R/W bitmask in procesor
definitions and processor float_status structure.

- Add appropriate value for FCR31's R/W bitmask for each supported
processor.

- Add function for setting snan_bit_is_one, and integrate it in
appropriate places.

- Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
bitmask.

- Modify handling user mode executables for Mips, in relation to the
bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
reading and writing to FCR31.

- Modify gdb behavior in relation to FCR31.

Backports commit 599bc5e89c46f95f86ccad0d747d041c89a28806 from qemu
2018-02-24 21:30:24 -05:00
Aleksandar Markovic 84b516d9db
target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
New set of helpers for handling nan2008-syle versions of instructions
<CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, for Mips R6.

All involved instructions have float operand and integer result. Their
core functionality is implemented via invocations of appropriate SoftFloat
functions. The problematic cases are when the operand is a NaN, and also
when the operand (float) is out of the range of the result.

Here one can distinguish three cases:

CASE MIPS-A: (FCR31.NAN2008 == 1)

1. Operand is a NaN, result should be 0;
2. Operand is larger than INT_MAX, result should be INT_MAX;
3. Operand is smaller than INT_MIN, result should be INT_MIN.

CASE MIPS-B: (FCR31.NAN2008 == 0)

1. Operand is a NaN, result should be INT_MAX;
2. Operand is larger than INT_MAX, result should be INT_MAX;
3. Operand is smaller than INT_MIN, result should be INT_MAX.

CASE SoftFloat:

1. Operand is a NaN, result is INT_MAX;
2. Operand is larger than INT_MAX, result is INT_MAX;
3. Operand is smaller than INT_MIN, result is INT_MIN.

Current implementation of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
implements case MIPS-B. This patch relates to case MIPS-A. For case
MIPS-A, only return value for NaN-operands should be corrected after
appropriate SoftFloat library function is called.

Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.

Backports commit 87552089b62fa229d2ff86906e4e779177fb5835 from qemu
2018-02-24 21:14:04 -05:00
Aleksandar Markovic a411a12170
target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always and only changing the sign bit, even
for NaN-like operands. Details on these instructions are documented
in [1] p. 35 and 359.

Implementation-wise, abs2008 versions are implemented without helpers,
for simplicity and performance sake.

[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015

Backports commit 6be77480052b1a71557081896e7080363a8a2f95 from qemu
2018-02-24 20:45:06 -05:00
Aleksandar Markovic 6eb4fa54f6
softfloat: Implement run-time-configurable meaning of signaling NaN bit
This patch modifies SoftFloat library so that it can be configured in
run-time in relation to the meaning of signaling NaN bit, while, at the
same time, strictly preserving its behavior on all existing platforms.

Background:

In floating-point calculations, there is a need for denoting undefined or
unrepresentable values. This is achieved by defining certain floating-point
numerical values to be NaNs (which stands for "not a number"). For additional
reasons, virtually all modern floating-point unit implementations use two
kinds of NaNs: quiet and signaling. The binary representations of these two
kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally,
the first bit of mantissa).

Up to 2008, standards for floating-point did not specify all details about
binary representation of NaNs. More specifically, the meaning of the bit
that is used for distinguishing between signaling and quiet NaNs was not
strictly prescribed. (IEEE 754-2008 was the first floating-point standard
that defined that meaning clearly, see [1], p. 35) As a result, different
platforms took different approaches, and that presented considerable
challenge for multi-platform emulators like QEMU.

Mips platform represents the most complex case among QEMU-supported
platforms regarding signaling NaN bit. Up to the Release 6 of Mips
architecture, "1" in signaling NaN bit denoted signaling NaN, which is
opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture
adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of
that, Mips architecture for SIMD (also known as MSA, or vector instructions)
also specifies signaling bit in accordance to IEEE standard. MSA unit can be
implemented with both pre-Release 6 and Release 6 main processor units.

QEMU uses SoftFloat library to implement various floating-point-related
instructions on all platforms. The current QEMU implementation allows for
defining meaning of signaling NaN bit during build time, and is implemented
via preprocessor macro called SNAN_BIT_IS_ONE.

On the other hand, the change in this patch enables SoftFloat library to be
configured in run-time. This configuration is meant to occur during CPU
initialization, at the moment when it is definitely known what desired
behavior for particular CPU (or any additional FPUs) is.

The change is implemented so that it is consistent with existing
implementation of similar cases. This means that structure float_status is
used for passing the information about desired signaling NaN bit on each
invocation of SoftFloat functions. The additional field in float_status is
called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE.

IMPORTANT:

This change is not meant to create any change in emulator behavior or
functionality on any platform. It just provides the means for SoftFloat
library to be used in a more flexible way - in other words, it will just
prepare SoftFloat library for usage related to Mips platform and its
specifics regarding signaling bit meaning, which is done in some of
subsequent patches from this series.

Further break down of changes:

1) Added field snan_bit_is_one to the structure float_status, and
correspondent setter function set_snan_bit_is_one().

2) Constants <float16|float32|float64|floatx80|float128>_default_nan
(used both internally and externally) converted to functions
<float16|float32|float64|floatx80|float128>_default_nan(float_status*).
This is necessary since they are dependent on signaling bit meaning.
At the same time, for the sake of code cleanup and simplicity, constants
<floatx80|float128>_default_nan_<low|high> (used only internally within
SoftFloat library) are removed, as not needed.

3) Added a float_status* argument to SoftFloat library functions
XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_),
XXX_maybe_silence_nan(XXX a_). This argument must be present in
order to enable correct invocation of new version of functions
XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128>
here)

4) Updated code for all platforms to reflect changes in SoftFloat library.
This change is twofolds: it includes modifications of SoftFloat library
functions invocations, and an addition of invocation of function
set_snan_bit_is_one() during CPU initialization, with arguments that
are appropriate for each particular platform. It was established that
all platforms zero their main CPU data structures, so snan_bit_is_one(0)
in appropriate places is not added, as it is not needed.

[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.

Backports commit af39bc8c49224771ec0d38f1b693ea78e221d7bc from qemu
2018-02-24 20:27:12 -05:00
Lluís Vilanova 2297527755
exec: [tcg] Track which vCPU is performing translation and execution
Information is tracked inside the TCGContext structure, and later used
by tracing events with the 'tcg' and 'vcpu' properties.

The 'cpu' field is used to check tracing of translation-time
events ("*_trans"). The 'tcg_env' field is used to pass it to
execution-time events ("*_exec").

Backports commit 7c2550432abe62f53e6df878ceba6ceaf71f0e7e from qemu
2018-02-24 19:21:39 -05:00
Paolo Bonzini 9485b7c2e1
cpu: move exec-all.h inclusion out of cpu.h
exec-all.h contains TCG-specific definitions. It is not needed outside
TCG-specific files such as translate.c, exec.c or *helper.c.

One generic function had snuck into include/exec/exec-all.h; move it to
include/qom/cpu.h.

Backports commit 63c915526d6a54a95919ebece83fa9ca631b2508 from qemu
2018-02-24 02:39:08 -05:00
Sergey Fedorov ffdc9d6323
tcg: Allow goto_tb to any target PC in user mode
In user mode, there's only a static address translation, TBs are always
invalidated properly and direct jumps are reset when mapping change.
Thus the destination address is always valid for direct jumps and
there's no need to restrict it to the pages the TB resides in.

Backports commit 90aa39a1cc4837360889f0e033ca25cc82100308 from qemu
2018-02-23 23:12:14 -05:00
Leon Alrae 224cbb008a
target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs
MIPS Release 6 and MIPS SIMD Architecture make it mandatory to have IEEE
754-2008 FPU which is indicated by CP1 FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008 bits set to 1.

In QEMU we still keep these bits cleared as there is no 2008-NaN support.
However, this now causes problems preventing from running R6 Linux with
the v4.5 kernel. Kernel refuses to execute 2008-NaN ELFs on a CPU
whose FPU does not support 2008-NaN encoding:

(...)
VFS: Mounted root (ext4 filesystem) readonly on device 8:0.
devtmpfs: mounted
Freeing unused kernel memory: 256K (ffffffff806f0000 - ffffffff80730000)
request_module: runaway loop modprobe binfmt-464c
Starting init: /sbin/init exists but couldn't execute it (error -8)
request_module: runaway loop modprobe binfmt-464c
Starting init: /bin/sh exists but couldn't execute it (error -8)
Kernel panic - not syncing: No working init found. Try passing init= option to kernel. See Linux Documentation/init.txt for guidance.

Therefore always indicate presence of 2008-NaN support in R6 as well as in
R5+MSA CPUs, even though this feature is not yet supported by MIPS in QEMU.

Backports commit ba5c79f26221c0fd7139c883a34a4e75d993f732 from qemu
2018-02-22 11:30:08 -05:00
Yongbok Kim 6602163087
target-mips: add MAAR, MAARI register
The MAAR register is a read/write register included in Release 5
of the architecture that defines the accessibility attributes of
physical address regions. In particular, MAAR defines whether an
instruction fetch or data load can speculatively access a memory
region within the physical address bounds specified by MAAR.

As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.

Backports commit f6d4dd810983fdf3d1c9fb81838167efef63d1c8 from qemu
2018-02-22 11:00:17 -05:00
Yongbok Kim 15e0109162
target-mips: use CP0_CHECK for gen_m{f|t}hc0
Reuse CP0_CHECK macro for gen_m{f|t}hc0.

Backports commit c98d3d79ee387ea6e8fb091299f8562b20022f10 from qemu
2018-02-22 10:49:55 -05:00
Leon Alrae 0c5ebbd096
target-mips: check CP0 enabled for CACHE instruction also in R6
Backports commit 40d48212f934d4deab40ffe84a0f9c4c553d4742 from qemu
2018-02-22 10:47:54 -05:00
Yongbok Kim d65583df80
target-mips: add CMGCRBase register
Physical base address for the memory-mapped Coherency Manager Global
Configuration Register space.
The MIPS default location for the GCR_BASE address is 0x1FBF_8.
This register only exists if Config3 CMGCR is set to one.

Backports commit c870e3f52cac0c8a4a1377398327c4ff20d49d41 from qemu
2018-02-22 10:43:26 -05:00
Lioncash a913b3e468
tcg: Make cpu_gpr a TCGv array
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 01:02:46 -05:00
Lioncash 1defc70341
tcg: Make cpu_PC a TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 00:47:13 -05:00
Lioncash 372e3307c5
tcg: Make bcond, btarget and cpu_dspctrl TCGv
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 00:45:59 -05:00
Lioncash baf25644dd
tcg: Make cpu_HI and cpu_LO a TCGv array
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
2018-02-21 00:34:49 -05:00
Yongbok Kim 46284f1a41
target-mips: implement R6 multi-threading
MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.

Backports commit 01bc435b44b8802cc4697faa07d908684afbce4e from qemu
2018-02-20 22:02:40 -05:00
Peter Maydell 00cf2aaef2
mips: Clean up includes
Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Backports commit c684822ad29968af09735148f03a511bc514589d from qemu
2018-02-19 00:45:08 -05:00
Miodrag Dinic 63dad98564
target-mips: Fix ALIGN instruction when bp=0
If executing ALIGN with shift count bp=0 within mips64 emulation,
the result of the operation should be sign extended.

Taken from the official documentation (pseudo code) :

ALIGN:
tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
tmp = tmp_rt_hi || tmp_rt_lo
GPR[rd] = sign_extend.32(tmp)

Backports commit 51243852af322f0a1103a90c936c43db84def82f from qemu
2018-02-19 00:42:13 -05:00
Yongbok Kim d4213b6389
target-mips: add SIGRIE instruction
Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and
microMIPS.
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.

Backports commit bb238210bb096534b68dab15a87c6ff0bef43672 from qemu
2018-02-17 15:24:13 -05:00
Yongbok Kim 4a9cd8ec0b
target-mips: add PC, XNP reg numbers to RDHWR
Add Performance Counter (4) and XNP (5) register numbers to RDHWR.
Add check_hwrena() to simplify access control checkings.
Add RDHWR support to microMIPS R6.

Backports commit b00c72180c36510bf9b124e190bd520e3b7e1358 from qemu
2018-02-17 15:24:13 -05:00
Yongbok Kim 3b000e4eb3
target-mips: Add enum for BREAK32
Add enum for BREAK32

Backports commit dbd8af9824d0ddc4400f859c2af77543461cba0d from qemu
2018-02-17 15:24:13 -05:00
Richard Henderson c01a6dab0a
target-*: Advance pc after recognizing a breakpoint
Some targets already had this within their logic, but make sure
it's present for all targets.

Backports commit 522a0d4e3c0d397ffb45ec400d8cbd426dad9d17 from qemu
2018-02-17 15:24:11 -05:00
Richard Henderson 3ec0adcc07
target-*: Introduce and use cpu_breakpoint_test
Reduce the boilerplate required for each target. At the same time,
move the test for breakpoint after calling tcg_gen_insn_start.

Note that arm and aarch64 do not use cpu_breakpoint_test, but still
move the inline test down after tcg_gen_insn_start.

Backports commit b933066ae03d924a92b2616b4a24e7d91cd5b841 from qemu
2018-02-17 15:24:10 -05:00
Richard Henderson a5ac288135
tcg: Remove gen_intermediate_code_pc
It is no longer used, so tidy up everything reached by it.
This includes the gen_opc_* arrays, the search_pc parameter
and the inline gen_intermediate_code_internal functions.

Backports commit 4e5e1215156662b2b153255c49d4640d82c5568b from qemu
2018-02-17 15:23:59 -05:00
Paolo Bonzini 268275f04b
translate: check cflags instead of use_icount global
Backports applicable parts of commit bd79255d2571a3c68820117caf94ea9afe1d527e
2018-02-17 15:23:59 -05:00
Richard Henderson 1cbd175736
tcg: Pass data argument to restore_state_to_opc
The gen_opc_* arrays are already redundant with the data stored in
the insn_start arguments. Transition restore_state_to_opc to use
data from the latter.

Backports commit bad729e272387de7dbfa3ec4319036552fc6c107 from qemu
2018-02-17 15:23:58 -05:00
Lioncash b115c5509d
tcg: Add TCG_MAX_INSNS
Adjust all translators to respect it.

Backports commit 190ce7fbc79fd0883a6170d7f30da59d366e6830 from qemu
2018-02-17 15:23:58 -05:00
Richard Henderson 500e116581
target-mips: Add delayed branch state to insn_start
Backports commit c20d594e45bc8c4b21be1a7637cba0f279f72879 from qemu
2018-02-17 15:23:56 -05:00
Pavel Dovgaluk 011861cd0e
target-mips: improve exception handling
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current
translation block. Implementation of the exceptions handling does not
correctly restore icount for the instruction which caused the exception.
In most cases icount will be decreased by the value equal to the size of
TB. This patch passes pointer to the translation block internals to the
exception handler. It allows correct restoring of the icount value.

Backports commit 9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc from qemu
2018-02-17 15:23:53 -05:00
Leon Alrae 2a968bb547
target-mips: correct MTC0 instruction on MIPS64
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Backports commit d54a299b83a07642c85a22bfe19b69ca4def9ec4 from qemu
2018-02-17 15:23:53 -05:00
Leon Alrae 18dcbc7a64
target-mips: add missing restriction in DAUI instruction
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Backports commit db77d8523909b32d798cd2c80de422b68f9e5c42 from qemu
2018-02-17 15:23:53 -05:00
Aurelien Jarno 1a441096c0
target-mips: get rid of MIPS_DEBUG
MIPS_DEBUG is a define used to dump the instruction disassembling. It
has to be defined at compile time. In practice I believe it's more
efficient to just look at the instruction disassembly and op dump using
-d in_asm,op. This patch therefore removes the corresponding code, which
clutters translate.c.

Backports commit 9d68ac14dab3f5af33a6b23458941dc6fb261fce from qemu
2018-02-17 15:23:52 -05:00
Aurelien Jarno 0045d99f38
target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.

Backports commit b307446e04232b3a87e9da04886895a8e5a4a407 from qemu
2018-02-17 15:23:52 -05:00
Petar Jovanovic dfa3d51a0f
target-mips: remove wrong checks for recip.fmt and rsqrt.fmt
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Backports commit ca6c7803d2beae43299a80f4549d36579881fc0b from qemu
2018-02-17 15:23:52 -05:00
Aurelien Jarno 88f7e01d44
target-mips: simplify LWL/LDL mask generation
The LWL/LDL instructions mask the GPR with a mask depending on the
address alignement. It is currently computed by doing:

mask = 0x7fffffffffffffffull >> (t1 ^ 63)

It's simpler to generate it by doing:

mask = ~(-1 << t1)

It uses one TCG instruction less, and it avoids a 32/64-bit constant
loading which can take a few instructions on RISC hosts.

Backports commit eb02cc3f89013612cb05df23b5441741e902bbd2 from qemu
2018-02-17 15:23:27 -05:00
Leon Alrae f0bf3c2e3b
target-mips: fix semihosting for microMIPS R6
In semihosting mode the SDBBP 1 instructions should trigger UHI syscall,
but in QEMU this does not happen for recently added microMIPS R6.
Consequently bare metal microMIPS R6 programs supporting UHI will not run.

Backports commit 060ebfef1a09b58fb219b3769b72efb407515bf1 from qemu
2018-02-17 15:23:24 -05:00
Aurelien Jarno 3cc6b5251e
target-mips: fix page fault address for LWL/LWR/LDL/LDR
When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU
currently reports the aligned address in CP0 BadVAddr, while the Windows
NT kernel expects the unaligned address.

This patch adds a byte access with the unaligned address at the
beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page
fault and fill the QEMU TLB.

Backports commit 908680c6441ac468f4871d513f42be396ea0d264 from qemu
2018-02-17 15:23:22 -05:00
Leon Alrae b045c2c99a
target-mips: fix logically dead code reported by Coverity
Make use of CMPOP in floating-point compare instructions.

Backports commit 47ada0ad3431b39863918dc80386634693d317b5 from qemu
2018-02-17 15:23:22 -05:00
Yongbok Kim 76ab1f17fb
target-mips: microMIPS32 R6 POOL16{A, C} instructions
microMIPS32 Release 6 POOL16A/ POOL16C instructions

Backports commit ed7ce6c0f9d4370826557ce33d652beb88ccb3e6 from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim 6e6ca4dbd4
target-mips: microMIPS32 R6 Major instructions
Add new microMIPS32 Release 6 Major opcode instructions

Backports commit ab39ee452d74855adec91056812b8e1e5166302c from qemu
2018-02-17 15:23:13 -05:00
Yongbok Kim c2550bc28a
target-mips: microMIPS32 R6 POOL32{I, C} instructions
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions

Backports commit 3b4a5489447e7ed17cc504572cf729833853e7ab from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim fe7e49dc20
target-mips: microMIPS32 R6 POOL32F instructions
Add new microMIPS32 Release 6 POOL32F instructions

Backports commit 2a24a7badeb6ad3ba72e7984f299623035d564d6 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim f816d6c637
target-mips: microMIPS32 R6 POOL32A{XF} instructions
Add new microMIPS32 Release 6 pool32a/pool32axf instructions.

Backports commit e03320958305a68f2bc6a32c87d7ed48303438f9 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim 697b234864
target-mips: microMIPS32 R6 branches and jumps
Add new microMIPS32 Release 6 branch and jump instructions.

Backports commit 65935f070aa710cf340e96ae7ee36d2c1d5c8d15 from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim de26dc6854
target-mips: add microMIPS32 R6 opcode enum
Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.

Backports commit 3a1f426828cd8ffeec1a4fa8ca6ca3ed4f800edb from qemu
2018-02-17 15:23:12 -05:00
Yongbok Kim 5cca75ca10
target-mips: signal RI for removed instructions in microMIPS R6
Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.

Backports commit 9e8f441a7e094c0dc33a1c8f521d9e5bcfc1b4da from qemu
2018-02-17 15:23:11 -05:00