Commit graph

556 commits

Author SHA1 Message Date
LIU Zhiwei 798c1682f8 target/riscv: vector wideing integer reduction instructions
Backports bba718200b2d2aac6ab5031817f7125571c983a1
2021-03-07 12:09:15 -05:00
LIU Zhiwei 4b1e548fd0 target/riscv: vector single-width integer reduction instructions
Backports fe5c9ab1fc185e96bf7e034954127429ca74d386
2021-03-07 12:07:51 -05:00
LIU Zhiwei e925927e23 target/riscv: narrowing floating-point/integer type-convert instructions
Backports 878d406ec28f945d262af4ffbea50b825d7a0825
2021-03-07 12:05:59 -05:00
LIU Zhiwei 0c80c49b1b target/riscv: widening floating-point/integer type-convert instructions
Backports 4514b7b12390525e59e335e7ca58fd44f6e69272
2021-03-07 12:02:56 -05:00
LIU Zhiwei 8b06759ba4 target/riscv: vector floating-point/integer type-convert instructions
Backports 921009732614fd620c75f05496597796719544cf
2021-03-07 12:00:36 -05:00
LIU Zhiwei fabc8bab77 target/riscv: vector floating-point merge instructions
Backports 64ab5846974140118c64e4d94ff2696932a0a58b
2021-03-07 11:58:41 -05:00
LIU Zhiwei f9c9716534 target/riscv: vector floating-point classify instructions
Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c
2021-03-07 11:55:45 -05:00
LIU Zhiwei b859be12b9 target/riscv: vector floating-point compare instructions
Backports 2a68e9e568faddf4d689a37fa6895bcb8404a677
2021-03-07 11:47:51 -05:00
LIU Zhiwei 31978f270b target/riscv: vector floating-point sign-injection instructions
Backports 1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
2021-03-07 11:43:47 -05:00
LIU Zhiwei f7f0425a4d target/riscv: vector floating-point min/max instructions
Backports 230b53ddd706c8b18a6d9beed1a0153b276d7037
2021-03-07 11:42:05 -05:00
LIU Zhiwei 69c73cfc4e target/riscv: vector floating-point square-root instruction
Backports d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
2021-03-07 11:40:04 -05:00
LIU Zhiwei 95a6d78121 target/riscv: vector widening floating-point fused multiply-add instructions
Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
2021-03-07 11:37:23 -05:00
LIU Zhiwei 42116609f0 target/riscv: vector single-width floating-point fused multiply-add instructions
Backports 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
2021-03-07 11:34:56 -05:00
LIU Zhiwei 14cbabde4f target/riscv: vector widening floating-point multiply
Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
2021-03-07 11:32:19 -05:00
LIU Zhiwei 5e4b142c31 target/riscv: vector single-width floating-point multiply/divide instructions
Backports 0e0057cbe2169195a08ae8247504e69f9b80542b
2021-03-07 11:30:14 -05:00
LIU Zhiwei 0de56731ae target/riscv: vector widening floating-point add/subtract instructions
eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
2021-03-07 11:27:33 -05:00
LIU Zhiwei 06092b88b9 target/riscv: vector single-width floating-point add/subtract instructions
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
2021-03-05 09:50:56 -05:00
LIU Zhiwei 5fb589cdd7 target/riscv: vector narrowing fixed-point clip instructions
Backports 9ff3d28739b760970f5e542c74a033470dca3f9b
2021-03-05 09:34:11 -05:00
LIU Zhiwei 241deddb50 target/riscv: vector single-width scaling shift instructions
Backports 04a614062dd5fb43f00bd955f44f7a2c3def016d
2021-03-05 09:32:15 -05:00
LIU Zhiwei e7582a5d74 target/riscv: vector widening saturating scaled multiply-add
Backports 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
2021-03-05 09:29:42 -05:00
LIU Zhiwei e27aadfa4f target/riscv: vector single-width fractional multiply with rounding and saturation
Backports 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
2021-03-05 09:26:56 -05:00
LIU Zhiwei 2343892c2e target/riscv: vector single-width averaging add and subtract
Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
2021-03-05 09:25:09 -05:00
LIU Zhiwei 87db3eb130 target/riscv: vector single-width saturating add and subtract
Backports eb2650e35ec1ed60ff302ce3330bd6c770640833
2021-03-05 09:23:17 -05:00
LIU Zhiwei 025aa6fd39 target/riscv: vector integer merge and move instructions
Backports 	f020a7a14505d6996497693e63331ab609847d93
2021-03-05 09:20:34 -05:00
LIU Zhiwei 9d14cc8d35 target/riscv: vector widening integer multiply-add instructions
Backports 2b587b335050dbc0cb3823758341f145c0375312
2021-03-05 09:13:03 -05:00
LIU Zhiwei 58891e213d target/riscv: vector single-width integer multiply-add instructions
Backports 54df813a331d3badfb83604c36bef7cb1de4315a
2021-03-05 09:11:33 -05:00
LIU Zhiwei 436e092e36 target/riscv: vector widening integer multiply instructions
Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428
2021-03-05 09:09:08 -05:00
LIU Zhiwei d144afdc45 target/riscv: vector integer divide instructions
Backports 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
2021-03-05 09:05:00 -05:00
Richard Henderson 554a304d3d qemu/compiler: Split out qemu_build_not_reached_always
Provide a symbol that can always be used to signal an error,
regardless of optimization. Usage of this should be protected
by e.g. __builtin_constant_p, which guards for optimization.

Backports c52ea111e0ea2d5368a3ae601baafaae75e3317f
2021-03-04 15:23:27 -05:00
Richard Henderson 419941c3d1 tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.

Backports be986adb35e3594b02ee0d7f1cbec96b08bb29b7
2021-03-04 13:32:32 -05:00
Richard Henderson 6e38e5004f tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders
Backports 88d4005b098427638d7551aa04ebde4fdd06835b
2021-03-04 13:05:25 -05:00
Richard Henderson 8edc9b76dd tcg: Introduce TYPE_CONST temporaries
These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.

Not used yet, this is all infrastructure.

Backports c0522136adf550c7a0ef7c0755c1f9d1560d2757
2021-03-03 21:29:40 -05:00
Richard Henderson a90476c897 tcg/i386: Adjust TCG_TARGET_HAS_MEMORY_BSWAP
Always true when movbe is available, otherwise leave
this to generic code.

Backports d2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5
2021-03-03 19:40:00 -05:00
Peter Maydell d350644817 target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
For AArch32, unlike the VCVT of integer to float, which honours the
rounding mode specified by the FPSCR, VCVT of fixed-point to float is
always round-to-nearest. (AArch64 fixed-point-to-float conversions
always honour the FPCR rounding mode.)

Implement this by providing _round_to_nearest versions of the
relevant helpers which set the rounding mode temporarily when making
the call to the underlying softfloat function.

We only need to change the VFP VCVT instructions, because the
standard- FPSCR value used by the Neon VCVT is always set to
round-to-nearest, so we don't need to do the extra work of saving
and restoring the rounding mode.

Backports commit 61db12d9f9eb36761edba4d9a414cd8dd34c512b
2021-03-01 20:04:31 -05:00
Peter Maydell 8c6affbca4 target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations
Add gvec helpers for doing Neon-style indexed non-fused fp
multiply-and-accumulate operations.

Backports commit c50d8d144098a8261233ca31b47e3bc487e112fe
2021-03-01 17:52:31 -05:00
Peter Maydell 681218b4ab target/arm: Implement fp16 for Neon VRINTX
Convert the Neon VRINTX insn to use gvec, and use this to implement
fp16 support for it.

Backports 23afcdd2511f2a3dc05bed650d27bd25cf9b2a3c
2021-03-01 17:47:25 -05:00
Peter Maydell 53aba9d900 target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode
Convert the Neon VRINT-with-specified-rounding-mode insns to gvec,
and use this to implement the fp16 versions.

Backports 18725916b1438b54d6d6533980833d2251a20b7c
2021-03-01 17:44:49 -05:00
Peter Maydell eb4054d04f target/arm: Implement fp16 for Neon VCVT with rounding modes
Convert the Neon VCVT with-specified-rounding-mode instructions
to gvec, and use this to implement fp16 support for them.

Backports ca88a6efdf4ce96b646a896059f9bd324c2cebc4
2021-03-01 17:40:36 -05:00
Peter Maydell 56fe927d40 target/arm: Implement fp16 for Neon VCVT fixed-point
Implement fp16 for the Neon VCVT insns which convert between
float and fixed-point.

Backports 24018cf3990b692b51e50183c5fbd98d17b3fa40
2021-03-01 17:36:43 -05:00
Peter Maydell 948b01ad01 target/arm: Convert Neon VCVT fixed-point to gvec
Convert the Neon VCVT float<->fixed-point insns to a
gvec style, in preparation for adding fp16 support.

Backports 7b959c5890deb9a6d71bc6800006a0eae0a84c60
2021-03-01 17:33:20 -05:00
Peter Maydell c324c6817e target/arm: Implement fp16 for Neon float-integer VCVT
Convert the Neon float-integer VCVT insns to gvec, and use this
to implement fp16 support for them.

Note that unlike the VFP int<->fp16 VCVT insns we converted
earlier and which convert to/from a 32-bit integer, these
Neon insns convert to/from 16-bit integers. So we can use
the existing vfp conversion helpers for the f32<->u32/i32
case but need to provide our own for f16<->u16/i16.

Backports 7782a9afec81d1efe23572135c1ed777691ccde5
2021-03-01 17:29:02 -05:00
Peter Maydell 82f4a7e135 target/arm: Implement fp16 for Neon pairwise fp ops
Convert the Neon pairwise fp ops to use a single gvic-style
helper to do the full operation instead of one helper call
for each 32-bit part. This allows us to use the same
framework to implement the fp16.

Backports 1dc587ee9bfe804406eb3e0bacf47a80644d8abc
2021-03-01 17:25:19 -05:00
Peter Maydell b08ea84374 target/arm: Implement fp16 for Neon VRSQRTS
Convert the Neon VRSQRTS insn to using a gvec helper,
and use this to implement the fp16 case.

As with VRECPS, we adjust the phrasing of the new implementation
slightly so that the fp32 version parallels the fp16 one.

Backports 40fde72dda2da8d55b820fa6c5efd85814be2023
2021-03-01 17:20:22 -05:00
Peter Maydell f4ebbba9fd target/arm: Implement fp16 for Neon VRECPS
Convert the Neon VRECPS insn to using a gvec helper, and
use this to implement the fp16 case.

The phrasing of the new float32_recps_nf() is slightly different from
the old recps_f32() so that it parallels the f16 version; for f16 we
can't assume that flush-to-zero is always enabled.

Backports ac8c62c4e5a3f24e6d47f52ec1bfb20994caefa5
2021-03-01 17:09:16 -05:00
Peter Maydell 5776c594e4 target/arm: Implement fp16 for Neon fp compare-vs-0
Convert the neon floating-point vector compare-vs-0 insns VCEQ0,
VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to
implement the fp16 case.

Backport 635187aaa92f21ab001e2868e803b3c5460261ca
2021-03-01 17:05:03 -05:00
Peter Maydell 8de258c3cb target/arm: Implement fp16 for Neon VFMA, VMFS
Convert the neon floating-point vector operations VFMA and VFMS
to use a gvec helper, and use this to implement the fp16 case.

This is the last use of do_3same_fp() so we can now delete
that function.

Backports commit cf722d75b329ef3f86b869e7e68cbfb1607b3bde
2021-03-01 17:00:49 -05:00
Peter Maydell 587c3549b7 target/arm: Implement fp16 for Neon VMLA, VMLS operations
Convert the Neon floating-point VMLA and VMLS insns over to using a
gvec helper, and use this to implement the fp16 case.

Backports e5adc70665ecaf4009c2fb8d66775ea718a85abd
2021-03-01 16:57:20 -05:00
Peter Maydell 0068d12355 target/arm: Implement fp16 for Neon VMAXNM, VMINNM
Convert the Neon floating point VMAXNM and VMINNM insns to
using a gvec helper and use this to implement the fp16 case.

Backports e22705bb941d82d6c2a09e8b2031084326902be3
2021-03-01 16:53:57 -05:00
Peter Maydell 465cfb54c4 target/arm: Implement fp16 for Neon VMAX, VMIN
Convert the Neon float-point VMAX and VMIN insns over to using
a gvec helper, and use this to implement the fp16 case.

Backport e43268c54b6cbcb197d179409df7126e81f8cd52
2021-03-01 16:50:23 -05:00
Peter Maydell 6dd4a8e93f target/arm: Implement fp16 for VACGE, VACGT
Convert the neon floating-point vector absolute comparison ops
VACGE and VACGT over to using a gvec hepler and use this to
implement the fp16 case.

Backports bb2741da186ebaebc7d5189372be4401e1ff9972
2021-03-01 16:47:44 -05:00