Commit graph

2128 commits

Author SHA1 Message Date
Markus Armbruster b5841191bc
qerror: Move #include out of qerror.h 2018-02-17 15:23:10 -05:00
Markus Armbruster 15553fc60d
qerror: Finally unused, clean up
Remove it except for two things in qerror.h:

* Two #include to be cleaned up separately to avoid cluttering this
patch.

* The QERR_ macros. Mark as obsolete.

Backports commit 4629ed1e98961bbe678db68ef5f4342ff174a6c3 from qemu
2018-02-17 15:23:10 -05:00
Markus Armbruster 76c16a46c7
qerror: Clean up QERR_ macros to expand into a single string
These macros expand into error class enumeration constant, comma,
string. Unclean. Has been that way since commit 13f59ae.

The error class is always ERROR_CLASS_GENERIC_ERROR since the previous
commit.

* Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and
delete it from the QERR_ macro. No change after preprocessing.

* Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into
error_setg(...). Again, no change after preprocessing.

Backports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu
2018-02-17 15:23:09 -05:00
Markus Armbruster 349447b324
qerror: Eliminate QERR_DEVICE_NOT_FOUND
Error classes other than ERROR_CLASS_GENERIC_ERROR should not be used
in new code. Hiding them in QERR_ macros makes new uses hard to spot.
Fortunately, there's just one such macro left. Eliminate it with this
coccinelle semantic patch:

@@
expression EP, E;
@@
-error_set(EP, QERR_DEVICE_NOT_FOUND, E)
+error_set(EP, ERROR_CLASS_DEVICE_NOT_FOUND, "Device '%s' not found", E)

Backports commit 75158ebbe259f0bd8bf435e8f4827a43ec89c877 from qemu
2018-02-17 15:23:09 -05:00
Eric Blake c749554a75
qobject: Use 'bool' inside qdict
Now that qbool is fixed, let's fix getting and setting a bool
value to a qdict member to also use C99 bool rather than int.

I audited all callers to ensure that the changed return type
will not cause any changed semantics.

Backports commit 34acbc95229f9f841bde83691a5af949c15e105b from qemu
2018-02-17 15:23:09 -05:00
Eric Blake d544d83348
qobject: Use 'bool' for qbool
We require a C99 compiler, so let's use 'bool' instead of 'int'
when dealing with boolean values. There are few enough clients
to fix them all in one pass.

Backports commit fc48ffc39ed1060856475e4320d5896f26c945e8 from qemu
2018-02-17 15:23:09 -05:00
Greg Ungerer 1f6f6b2863
m68k: fix usp processing on interrupt entry and exception exit
The action to potentially switch sp register is not occurring at the correct
point in the interrupt entry or exception exit sequences.

For the interrupt entry case the sp on entry is used to create the stack
exception frame - but this may well be the user stack pointer, since we
haven't done the switch yet. Re-order the flow to switch the sp regs then
use the current sp to create the exception frame.

For the return from exception case the code is unwinding the sp after
switching sp registers. But it should always unwind the supervisor sp
first, then carry out any required sp switch.

Note that these problems don't effect operation unless the user sp bit is
set in the CACR register. Only a single sp is used in the default power up
state. Previously Linux only used this single sp mode. But modern versions
of Linux use the user sp mode now, so we need correct behavior for Linux
to work.

Backports commit 0c8ff723bd29e5c8b2ca989f857ae5c37ec49c4e from qemu
2018-02-17 15:23:09 -05:00
Greg Ungerer 0a0383e2b5
m68k: implement move to/from usp register instruction
Fill out the code support for the move to/from usp instructions. They are
being decoded, but there is no code to support there actions. So add it.

Current versions of Linux running on the ColdFire 5208 use these instructions.

Backports commit 2a8327e8a8288e301a2f01bc3ca2d465a3a4ca78 from qemu
2018-02-17 15:23:09 -05:00
Peter Crosthwaite 63e5f57bb2
target-arm: Add support for Cortex-R5
Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
and both thumb and ARM div instructions.

Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
don't have a lot of meaning in QEMU yet. Raz them so the guest can
proceed if they are read. The TCM registers will return a size of 0,
indicating no TCM.

Backports commit d6a6b13ea1dfeb25c43a648e94cfe4395906f1da from qemu
2018-02-17 15:23:08 -05:00
Peter Crosthwaite 500d37e9b3
target-arm: Implement PMSAv7 MPU
Unified MPU only. Uses ARM architecture major revision to switch
between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains
unsupported and is asserted against.

Backports commit f6bda88ff839e2adefe4959b7def420b90703855 from qemu
2018-02-17 15:23:08 -05:00
Peter Crosthwaite 65f70d7a08
target-arm: Add registers for PMSAv7
Define the arm CP registers for PMSAv7 and their accessor functions.
RGNR serves as a shared index that indexes into arrays storing the
DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd
separately from the CP interface using a new PMSA specific VMSD
subsection.

Backports commit 6cb0b013a1fa421cdfb83257cd33f855cc90649a from qemu
2018-02-17 15:22:43 -05:00
Peter Crosthwaite 7d933a6ba9
target-arm/helper.c: define MPUIR register
Define the MPUIR register for MPU supporting ARMv6 and onwards.
Currently we only support unified MPU.

The size of the unified MPU is defined via the number of "dregions".
So just a single config is added to specify this size. (When split MPU
is implemented we will add an extra iregions config).

Backports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu
2018-02-17 15:22:43 -05:00
Sergey Fedorov 07ead14756
target-arm: Do not reset sysregs marked as ALIAS
cp_reg_reset() is called from g_hash_table_foreach() which does not
define a specific ordering of the hash table iteration. Thus doing reset
for registers marked as ALIAS would give an ambiguous result when
resetvalue is different for original and alias registers. Exit
cp_reg_reset() early when passed an alias register. Then clean up alias
register definitions from needless resetvalue and resetfn.

In particular, this fixes a bug in the handling of the PMCR register,
which had different resetvalues for its 32 and 64-bit views.

Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-17 15:22:43 -05:00
Aurelio C. Remonda 7ca21d4ab4
target-arm: Add the Cortex-M4 CPU
This patch adds the Cortex-M4 CPU. The M4 is basically the same as
the M3, the main differences being the DSP instructions and an
optional FPU. Only no-FPU cortex-M4 is implemented here, cortex-M4F
is not because the core target-arm code doesn't support the M-profile
FPU model yet.

Backports commit ba890a9b2509a0087bb7eafddae02ea5ecbb7bb4 from qemu
2018-02-17 15:22:43 -05:00
Aurelien Jarno 20c2ed80a2
translate-all: fix watchpoints if retranslation not possible
The tb_check_watchpoint function currently assumes that all memory
access is done either directly through the TCG code or through an
helper which knows its return address. This is obviously wrong as the
helpers use cpu_ldxx/stxx_data functions to access the memory.

Instead of aborting in that case, don't try to retranslate the code, but
assume that the CPU state (and especially the program counter) has been
saved before calling the helper. Then invalidate the TB based on this
address.

Backports commit 8d302e76755b8157373073d7107e31b0b13f80c1 from qemu
2018-02-17 15:22:43 -05:00
Aurelien Jarno 93df793d4d
softmmu: provide tlb_vaddr_to_host function for user mode
To avoid to many #ifdef in target code, provide a tlb_vaddr_to_host for
both user and softmmu modes. In the first case the function always
succeed and just call the g2h function.

Backports commit 2e83c496261c799b0fe6b8e18ac80cdc0a5c97ce from qemu
2018-02-17 15:22:43 -05:00
Peter Maydell 13db196792
target-arm: Correct "preferred return address" for cpreg access exceptions
The architecture defines that when taking an exception trying to
access a coprocessor register, the "preferred return address" for
the exception is the address of the instruction that caused the
exception. Correct an off-by-4 error which meant we were returning
the address after the instruction for traps which happened because
of a failure of a runtime access-check function on an AArch32
register. (Traps caused by translate-time checkable permissions
failures had the correct address, as did traps on AArch64 registers.)

This fixes https://bugs.launchpad.net/qemu/+bug/1463338

Backports commit 3977ee5d7a9f2e3664dd8b233f3224694e23b62b from qemu
2018-02-17 15:22:42 -05:00
Peter Crosthwaite c1554dbd06
arm: helper: rename get_phys_addr_mpu
This get_phys_addr is really for pmsav5. Rename it accordingly.

Backports commit 13689d43646482f7305282de1bdd662c0d2b8b77 from qemu
2018-02-17 15:22:42 -05:00
Peter Crosthwaite 0299851aa0
arm: Add has-mpu property
For processors that support MPUs, add a property to de-feature it. This
is similar to the implementation of the EL3 feature.

The processor definition in init sets ARM_FEATURE_MPU if it can support
an MPU. post_init exposes the property, defaulting to true. If cleared
by the instantiator, ARM_FEATURE_MPU is then removed at realize time.

This is to support R profile processors that may or may-not have an MPU
configured.

Backports commit 8f325f568fbd0158cd413e7d637573ba90b3eaab from qemu
2018-02-17 15:22:42 -05:00
Peter Crosthwaite 6f843a5484
arm: Implement uniprocessor with MP config
Add a boolean for indicating uniprocessors with MP extensions. This
drives the U bit in MPIDR. Prepares support for Cortex-R5.

Backports commit a8e81b319d1ae1224cc7059877dcdf04a5aad59d from qemu
2018-02-17 15:22:42 -05:00
Peter Crosthwaite e8499a8f9b
arm: Refactor get_phys_addr FSR return mechanism
Currently, the return code for get_phys_addr is overloaded for both
success/fail and FSR value return. This doesn't handle the case where
there is an error with a 0 FSR. This case exists in PMSAv7.

So rework get_phys_addr and friends to return a success/failure boolean
return code and populate the FSR via a caller provided uint32_t
pointer.

Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-17 15:22:42 -05:00
Peter Crosthwaite 4c204e6f3f
arm: helper: Factor out CP regs common to [pv]msa
V6+ PMSA and VMSA share some common registers that are currently
in the VMSA definition block. Split them out into a new def that can
be shared to PMSA.

Backports commit 8e5d75c950a1241f6e1243c37f28cd58f68fedc9 from qemu
2018-02-17 15:22:31 -05:00
Peter Crosthwaite 62ddaba69f
arm: Don't add v7mp registers in MPU systems
These registers are VMSA specific so they should be conditional on
VMSA (i.e. !MPU).

Backports commit 5e5cf9e35f25f9f932a6ce25107c11b67b426a43 from qemu
2018-02-13 14:37:22 -05:00
Peter Crosthwaite 70fae13253
arm: Do not define TLBTR in PMSA systems
If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP.
The def is done separately from VMSA registers group as it is affected
by both the OMAP/STRONGARM RW errata and the MIDR backgrounding.

Backports commit 8085ce63c5967d200f1241b6c0a189371993c5df from qemu
2018-02-13 14:35:38 -05:00
Pavel Fedin caed2f123d
target-arm: Use the kernel's idea of MPIDR if we're using KVM
When we're using KVM, the kernel's internal idea of the MPIDR
affinity fields must match the values we tell it for the guest
vcpu cluster configuration in the device tree. Since at the moment
the kernel doesn't support letting userspace tell it the correct
affinity fields to use, we must read the kernel's view and
reflect that back in the device tree.

Backports commit eb5e1d3c85dffe677da2550d211f9304a7d5ba3b from qemu
2018-02-13 14:32:46 -05:00
Sergey Fedorov 614ecb2bf2
target-arm: add AArch32 MIDR aliases in ARMv8
According to ARMv8 ARM, there are additional aliases to MIDR system register in
AArch32 state. So add them to the list.

Backports commit ac00c79ff6635ae9fd732ff357ada0d05e795500 from qemu
2018-02-13 14:28:11 -05:00
Sergey Fedorov 113cda90c3
target-arm: Fix REVIDR reset value
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.

Backports commit 13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932 from qemu
2018-02-13 14:24:08 -05:00
Alex Bennée f6d104b33a
target-arm/cpu.h: remove pending_exception
This isn't used by any of the code. In fact it looks like it was never
used as it came in with ARMv7 support.

Backports commit a79e0218e0ae27c9cdd2648bd46e5a916c903cc2 from qemu
2018-02-13 14:24:08 -05:00
Sergey Fedorov 7f53358ec1
target-arm: use extended address bits from supersection short descriptor
Since ARMv7 with LPAE support, a supersection short translation table
descriptor has had extended base address fields which hold bits 39:32 of
translated address. These fields are IMPDEF in ARMv6 and ARMv7 without
LPAE support.

Backports commit 4e42a6ca37e39e56725518851f4388e46bd91129 from qemu
2018-02-13 14:24:08 -05:00
Peter Maydell 84c75286f5
target-arm: Handle "extended small page" descriptors correctly
The old ARMv5-style page table format includes a kind of second level
descriptor named the "extended small page" format, whose primary purpose
is to allow specification of the TEX memory attribute bits on a 4K page.
This exists on ARMv6 and also (as an implementation extension) on XScale
CPUs; it's UNPREDICTABLE on v5.

We were mishandling this in two ways:
(1) we weren't implementing it for v6 (probably never noticed because
Linux will use the new-style v6 page table format there)
(2) we were not correctly setting the page_size, which is 4K, not 1K

The latter bug went unnoticed for years because the only thing which
the page_size affects is which TLB entries get flushed when the guest
does a TLB invalidate on an address in the page, and prior to commit
2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's
habit of writing the SCTLR pointlessly a lot.

(We can assume that after commit 2f0d8631b7 the bug went unnoticed
for a year because nobody's actually using the Zaurus/XScale emulation...)

Report the correct page size for these descriptors, and permit them
on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus
can boot the kernel OK but gets random segfaults when it tries to
run userspace programs.

Backports commit fc1891c74ae122a9dc7854f38bae7db03cd911e6 from qemu
2018-02-13 14:19:53 -05:00
Leon Alrae 3d72ec65bd
target-mips: enable XPA and LPA features
Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.

Backports commit 6773f9b687e0a8ab4b638ef88d075fb233fb7669 from qemu
2018-02-13 14:14:59 -05:00
Leon Alrae aff700ae6d
target-mips: remove misleading comments in translate_init.c
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is
the architectural limit) in QEMU.

Backports commit 28b027d5b63c7550c7390041d6dd50948c8f55b8 from qemu
2018-02-13 14:05:25 -05:00
Leon Alrae 8743ec8b6d
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
upper word of extended to 64-bits CP0 registers.

In MIPS64, when CP0 destination register specified is the EntryLo0 or
EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
EntryLo1. This is to compensate for RI and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.

Backports commit 5204ea79ea739b557f47fc4db96c94edcb33a5d6 from qemu
2018-02-13 14:03:59 -05:00
Leon Alrae 59865351e0
target-mips: add CP0.PageGrain.ELPA support
CP0.PageGrain.ELPA enables support for large physical addresses. This field
is encoded as follows:
0: Large physical address support is disabled.
1: Large physical address support is enabled.

If this bit is a 1, the following changes occur to coprocessor 0 registers:
- The PFNX field of the EntryLo0 and EntryLo1 registers is writable and
concatenated with the PFN field to form the full page frame number.
- Access to optional COP0 registers with PA extension, LLAddr, TagLo is
defined.

P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if
XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode.
In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0).

env->PABITS value is constant and indicates maximum PABITS available on
a core, whereas env->PAMask is calculated from env->PABITS and is also
affected by CP0.PageGrain.ELPA.

Backports commit e117f52636d04502fab28bd3abe93347c29f39a5 from qemu
2018-02-13 13:55:53 -05:00
Leon Alrae a13d401fe8
target-mips: support Page Frame Number Extension field
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.

Backports commit cd0d45c40133ef8b409aede5ad8a99aeaf6a70fe from qemu
2018-02-13 13:49:55 -05:00
Leon Alrae 95ed79d9c2
target-mips: extend selected CP0 registers to 64-bits in MIPS32
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.

Introduce gen_move_low32() function which moves low 32 bits from 64-bit
temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on
MIPS32.

Backports commit 284b731a6ae47b9ebabb9613e753c4d83cf75dd3 from qemu
2018-02-13 13:45:29 -05:00
Leon Alrae 907bb26e5f
target-mips: correct MFC0 for CP0.EntryLo in MIPS64
CP0.EntryLo bits 31:30 have to be cleared.

Backports commit b435f3f3d174721382b55bbd0c785ec50c1796a9 from qemu
2018-02-13 13:36:01 -05:00
Leon Alrae 57f57a9de4
target-mips: add ERETNC instruction and Config5.LLB bit
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.

Presence of ERETNC is denoted by the Config5.LLB.

Backports commit ce9782f40ac16660ea9437bfaa2c9c34d5ed8110 from qemu
2018-02-13 13:33:37 -05:00
Yongbok Kim 922d30c448
target-mips: Misaligned memory accesses for MSA
MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all addresses for a vector store access if it is spanning
into two pages.

Separating helper functions for each data format as format is known in
translation.
To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag.
Removing save_cpu_state() call in translation because it is able to use
cpu_restore_state() on fault as GETRA() is passed.

Backports commit adc370a48fd26b92188fa4848dfb088578b1936c from qemu
2018-02-13 13:27:31 -05:00
Yongbok Kim 6d0766f246
target-mips: Misaligned memory accesses for R6
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).

Backports commit be3a8c53b4f18bcc51a462d977cc61a0f46ebb1c from qemu
2018-02-13 13:11:39 -05:00
Leon Alrae c54458b638
target-mips: add Config5.FRE support allowing Status.FR=0 emulation
This relatively small architectural feature adds the following:

FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
available.

Config5.FRE: When enabled all single-precision FP arithmetic instructions,
LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions
exception.

Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.

Enable the feature in MIPS64R6-generic CPU.

Backports commit 7c979afd11b09a16634699dd6344e3ba10c9677e from qemu
2018-02-13 13:05:22 -05:00
Leon Alrae 428ffed744
target-mips: move group of functions above gen_load_fpr32()
Move the "Tests" group of functions so that gen_load_fpr32() and
gen_store_fpr32() can use generate_exception().

Backports commit eab9944c7801525737626fa45cddaf00932dd2c8 from qemu
2018-02-13 12:45:27 -05:00
Paolo Bonzini 91503663e2
target-i386: create a separate AddressSpace for each CPU
Different CPUs can be in SMM or not at the same time, thus they
will see different things where the chipset places SMRAM.

Backports commit 2001d0cd6d55e5efa9956fa8ff8b89034d6a4329 from qemu
2018-02-13 12:36:26 -05:00
Paolo Bonzini fa57438734
target-i386: wake up processors that receive an SMI
An SMI should definitely wake up a processor in halted state!
This lets OVMF boot with SMM on multiprocessor systems, although
it halts very soon after that with a "CpuIndex != BspIndex"
assertion failure.

Backports commit a9bad65d2c1f61af74ce2ff43238d4b20bf81c3a from qemu
2018-02-13 12:32:24 -05:00
Paolo Bonzini d4621935bb
target-i386: set G=1 in SMM big real mode selectors
Because the limit field's bits 31:20 is 1, G should be 1.
VMX actually enforces this, let's do it for completeness
in QEMU as well.

Backports commit b4854f1384176d897747de236f426d020668fa3c from qemu
2018-02-13 12:31:18 -05:00
Paolo Bonzini 1fed54da89
target-i386: mask NMIs on entry to SMM
QEMU is not blocking NMIs on entry to SMM. Implementing this has to
cover a few corner cases, because:

- NMIs can then be enabled by an IRET instruction and there
is no mechanism to _set_ the "NMIs masked" flag on exit from SMM:
"A special case can occur if an SMI handler nests inside an NMI handler
and then another NMI occurs. [...] When the processor enters SMM while
executing an NMI handler, the processor saves the SMRAM state save map
but does not save the attribute to keep NMI interrupts disabled.

- However, there is some hidden state, because "If NMIs were blocked
before the SMI occurred [and no IRET is executed while in SMM], they
are blocked after execution of RSM." This is represented by the new
HF2_SMM_INSIDE_NMI_MASK bit. If it is zero, NMIs are _unblocked_
on exit from RSM.

Backports commit 9982f74bad70479939491b69522da047a3be5a0d from qemu
2018-02-13 12:29:31 -05:00
Paolo Bonzini e57e92feca
target-i386: Use correct memory attributes for ioport accesses
In order to do this, stop using the cpu_in*/out* helpers, and instead
access address_space_io directly.

cpu_in* and cpu_out* remain for usage in the monitor, in qtest, and
in Xen.

Backports commit 3f7d84648607cc0fcb3812bb4b88978e2a7aa24f from qemu
2018-02-13 12:27:43 -05:00
Lioncash 25a58231fc
target-i386: Use correct memory attributes for memory accesses
These include page table walks, SVM accesses and SMM state save accesses.

The bulk of the patch is obtained with

sed -i 's/\(\<[a-z_]*_phys\(_notdirty\)\?\>(cs\)->as,/x86_\1,/'

Backports commit b216aa6c0fcbaa8ff4128969c14594896a5485a4 from qemu
2018-02-13 11:54:12 -05:00
Paolo Bonzini dc80b0893f
target-i386: introduce cpu_get_mem_attrs
Backports commit f794aa4a2fd772a3ec413c4e478cc23857cfee98 from qemu
2018-02-13 11:33:39 -05:00
Paolo Bonzini 88d1506e6a
memory: use mr->ram_addr in "is this RAM?" assertions
mr->terminates alone doesn't guarantee that we are looking at a RAM region.
mr->ram_addr also has to be checked, in order to distinguish RAM and I/O
regions.

So, do the following:

1) add a new define RAM_ADDR_INVALID, and test it in the assertions
instead of mr->terminates

2) IOMMU regions were not setting mr->ram_addr to a bogus value, initialize
it in the instance_init function so that the new assertions would fire
for IOMMU regions as well.

Backports commit ec05ec26f940564b1e07bf88857035ec27e21dd8 from qemu
2018-02-13 11:31:02 -05:00