Commit graph

59 commits

Author SHA1 Message Date
Sergey Sorokin a883d349fe
target-arm: Fix default_exception_el() function for the case when EL3 is not supported
If EL3 is not supported in current configuration,
we should not try to get EL3 bitness.

Backports commit cef9ee706792b1e205fe472b67053a0e82cd058e from qemu
2018-02-17 15:23:36 -05:00
Peter Maydell 1b88e0e8c8
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
For the A64 instruction set, the semihosting call instruction
is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
if semihosting is enabled.

Backports commit 8012c84ff92a36d05dfe61af9b24dd01a7ea25e4 from qemu
2018-02-17 15:23:34 -05:00
Lioncash f81894dddb
exec: Add semihosting stubs 2018-02-17 15:23:33 -05:00
Peter Maydell 8840d8370d
target-arm: Split DISAS_YIELD from DISAS_WFE
Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as "yield this CPU back to the top level loop so
another CPU has a chance to run". However it's rather confusing
that YIELD ends up calling HELPER(wfe), and if we ever want to
implement real behaviour for WFE and SEV it's likely to trip us up.

Split out the yield codepath to use DISAS_YIELD and a new
HELPER(yield) function, and have HELPER(wfe) call HELPER(yield).

Backports commit 049e24a191c212d9468db84169197887f2c91586 from qemu
2018-02-17 15:23:14 -05:00
Peter Maydell 6d7370457f
target-arm: Don't halt on WFI unless we don't have any work
Just NOP the WFI instruction if we have work to do.
This doesn't make much difference currently (though it does avoid
jumping out to the top level loop and immediately restarting),
but the distinction between "halt" and "don't halt" will become
more important when the decision to halt requires us to trap
to a higher exception level instead.

Backport commit 84549b6dcf9147559ec08b066de673587be6b763 from qemu
2018-02-12 23:10:45 -05:00
Greg Bellows 3c87e50745
target-arm: Extend FP checks to use an EL
Extend the ARM disassemble context to take a target exception EL instead of a
boolean enable. This change reverses the polarity of the check making a value
of 0 indicate floating point enabled (no exception).

Backports commit 9dbbc748d671c70599101836cd1c2719d92f3017 from qemu
2018-02-12 23:04:19 -05:00
Peter Maydell a41d967577
target-arm: Make singlestate TB flags common between AArch32/64
Currently we keep the TB flags PSTATE_SS and SS_ACTIVE in different
bit positions for AArch64 and AArch32. Replace these separate
definitions with a single common flag in the upper part of the
flags word.

Backports commit 3cf6a0fcedd429693d439556543400d5f0e31e1d from qemu
2018-02-12 22:57:53 -05:00
Greg Bellows edd8066082
target-arm: Add exception target el infrastructure
Add a CPU state exception target EL field that will be used for communicating
the EL to which an exception should be routed.

Add a disassembly context field for tracking the EL3 architecture needed for
determining the target exception EL.

Add a target EL argument to the generic exception helper for callers to specify
the EL to which the exception should be routed. Extended the helper to set
the newly added CPU state exception target el.

Added a function for setting the target exception EL and updated calls to helpers
to call it.

Backports commit 737103619869600668cc7e8700e4f6eab3943896 from qemu
2018-02-12 22:17:02 -05:00
Peter Maydell 8287ec801e
target-arm: A64: Avoid signed shifts in disas_ldst_pair()
Avoid shifting potentially negative signed offset values in
disas_ldst_pair() by keeping the offset in a uint64_t rather
than an int64_t.

Backports commit c2ebd862a54b7e12175d65c03ba259926cb2237a from qemu
2018-02-12 15:05:09 -05:00
Peter Maydell 4ea6fdc986
target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr
Shifting a negative integer left is undefined behaviour in C.
Avoid it by assembling and shifting the offset fields as
unsigned values and then sign extending as the final action.

Backports commit 037e1d009e2fcb80784d37f0e12aa999787d46d4 from qemu
2018-02-12 15:04:03 -05:00
Peter Maydell 0e9a6a26f5
target-arm: A64: Fix handling of rotate in logic_imm_decode_wmask
The code in logic_imm_decode_wmask attempts to rotate a mask
value within the bottom 'e' bits of the value with
mask = (mask >> r) | (mask << (e - r));
This has two issues:
* if the element size is 64 then a rotate by zero results
in a shift left by 64, which is undefined behaviour
* if the element size is smaller than 64 then this will
leave junk in the value at bit 'e' and above, which is
not valid input to bitfield_replicate(). As it happens,
the bits at bit 'e' to '2e - r' are exactly the ones
which bitfield_replicate is going to copy in there,
so this isn't a "wrong code generated" bug, but it's
confusing and if we ever put an assert in
bitfield_replicate it would fire on valid guest code.

Fix the former by not doing anything if r is zero, and
the latter by masking with bitmask64(e).

Backports commit e167adc9d9f5df4f8109aecd4552c407fdce094a from qemu
2018-02-12 15:02:34 -05:00
Peter Maydell b95cba4677
target-arm: A64: Fix shifts into sign bit
Fix attempts to shift into the sign bit of an int, which is undefined
behaviour in C and warned about by the clang sanitizer.

Backports commit 1743d55c8b38bcee632cf6eb2de81131635bb3d2 from qemu
2018-02-12 15:01:10 -05:00
Peter Maydell da216e211f
target-arm: Use correct mmu_idx for unprivileged loads and stores
The MMU index to use for unprivileged loads and stores is more
complicated than we currently implement:
* for A64, it should be "if at EL1, access as if EL0; otherwise
access at current EL"
* for A32/T32, it should be "if EL2, UNPREDICTABLE; otherwise
access as if at EL0".

In both cases, if we want to make the access for Secure EL0
this is not the same mmu_idx as for Non-Secure EL0.

Backports commit 579d21cce63f3dd2f6ee49c0b02a14e92cb4a836 from qemu
2018-02-12 11:28:17 -05:00
Peter Maydell 3261ed5801
target-arm: Define correct mmu_idx values and pass them in TB flags
We currently claim that for ARM the mmu_idx should simply be the current
exception level. However this isn't actually correct -- secure EL0 and EL1
should have separate indexes from non-secure EL0 and EL1 since their
VA->PA mappings may differ. We also will want an index for stage 2
translations when we properly support EL2.

Define and document all seven mmu index values that we require, and
pass the mmu index in the TB flags rather than exception level or
priv/user bit.

This change doesn't update the get_phys_addr() code, so our page
table walking still assumes a simplistic "user or priv?" model for
the moment.

Backports commit c1e3781090b9d36c60e1a254ba297cb34011d3d4 from qemu
2018-02-12 11:21:19 -05:00
Richard Henderson 2c091e5fb8
target-arm: Add condexec state to insn_start
Backports commit 52e971d9ff67e340ac2a86bd67e14bd31c7991e0 from qemu
2018-02-11 15:13:40 -05:00
Richard Henderson dd1ec408e5
target-*: Increment num_insns immediately after tcg_gen_insn_start
This does tidy the icount test common to all targets.

Backports commit 959082fc4a93a016a6b697e1e0c2b373d8a3a373 from qemu
2018-02-11 12:46:30 -05:00
Richard Henderson a64d0ff657
target-*: Unconditionally emit tcg_gen_insn_start
While we're at it, emit the opcode adjacent to where we currently
record data for search_pc. This puts gen_io_start et al on the
"correct" side of the marker.

Backports commit 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 from qemu
2018-02-11 12:41:20 -05:00
Lioncash b3f9ff667b
tcg: Rename debug_insn_start to insn_start
With an eye toward making it mandatory.

Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu
2018-02-11 12:34:01 -05:00
Richard Henderson eb5ed2a844
target-arm: Use tcg_gen_extrh_i64_i32
Usually, eliminate an operation from the translator by combining
a shift with an extract.

In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF,
merely a non-zero value. Given that we can extract both halves of a
64-bit input in one call, this simplifies the code.

Backports commit 7cb36e18b2f1c1f971ebdc2121de22a8c2e94fd6 from qemu
2018-02-11 02:57:54 -05:00
Richard Henderson b94da3fc13
target-arm: Recognize ROR
Backports commit 8fb0ad8e16ab3d03433244a1a03e1df757342ad8 from qemu
2018-02-11 02:57:33 -05:00
Richard Henderson 3173269986
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
For !SF, this initial ext32u can't be optimized away by the
current TCG code generator. (It would require backward bit
liveness propagation.)

Backports commit d3a77b42decd0cbfa62a5526e67d1d6d380c83a9 from qemu
2018-02-11 01:35:58 -05:00
Richard Henderson c637a97270
target-arm: Recognize UXTB, UXTH, LSR, LSL
These are all special case aliases of UBFM.

Backports commit 9924e85829fe21b5f38a5d267c9aea44c5d478ac from qemu
2018-02-11 01:34:11 -05:00
Richard Henderson d9e4e70636
target-arm: Recognize SXTB, SXTH, SXTW, ASR
These are all special case aliases of SBFM.

Backports commit ef60151bee9a95e3a5cc98b345a19ed7eb435ddb from qemu
2018-02-11 01:31:54 -05:00
Richard Henderson 5ee72ff9f5
target-arm: Implement fcsel with movcond
Backports commit 6e061029d74455d83f6fa070ac33de7a356cf60d from qemu
2018-02-11 01:29:14 -05:00
Richard Henderson 53bd2b1d5c
target-arm: Implement ccmp branchless
This can allow much of a ccmp to be elided when particular
flags are subsequently dead.

Backports commit 7dd03d773e0dafae9271318fc8d6b2b14de74403 from qemu
2018-02-11 01:25:51 -05:00
Richard Henderson 2c71ddefb1
target-arm: Use setcond and movcond for csel
Backports commit 259cb68491ab36427e7e5d820fe543d53b006ec6 from qemu
2018-02-10 23:57:11 -05:00
Richard Henderson a3aaf5a864
tcg: Remove tcg_gen_trunc_i64_i32
Replacing it with tcg_gen_extrl_i64_i32.

Backports commit ecc7b3aa71f5fdcf9ee87e74ca811d988282641d from qemu
2018-02-10 23:11:02 -05:00
Richard Henderson 232632e76c
tcg: Change translator-side labels to a pointer
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.

Note that the code generating backends still manipulate labels as int.

With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.

Backports commit 42a268c241183877192c376d03bd9b6d527407c7 from qemu
2018-02-09 14:17:56 -05:00
Lioncash 0273e6ae18
tcg: Put opcodes in a linked list
The previous setup required ops and args to be completely sequential,
and was error prone when it came to both iteration and optimization.
2018-02-09 12:54:05 -05:00
Richard Henderson a41b9acc0c
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
The method by which we count the number of ops emitted
is going to change. Abstract that away into some inlines.

Backports commit fe700adb3db5b028b504423b946d4ee5200a8f2f from qemu.
2018-02-09 09:31:17 -05:00
Richard Henderson 78378289e3
tcg: Move emit of INDEX_op_end into gen_tb_end
Backports commit 0a7df5da986bd7ee0789f2d7b8611f2e8eee5046 from qemu
2018-02-09 08:51:01 -05:00
Richard Henderson 6b4b493dae
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Thus, use cpu_env as the parameter, not TCG_AREG0 directly.
Update all uses in the translators.

Backports commit e1ccc05444676b92c63708096e36582be27fbee1 from qemu
2018-02-08 12:33:33 -05:00
Richard Henderson afb67fc002
target/arm: Fix aa64 ldp register writeback
Backports commit 3e4d91b94ce400326fae0850578d9e9f30a71adb from qemu
2018-02-08 08:29:51 -05:00
Eric Blake 37cdcbf771
maint: Fix macros with broken 'do/while(0); ' usage 2018-02-07 20:27:37 -05:00
Lioncash 0f453b0595
target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
Backports commit 9a2b5256ea1f68c89d5da4b54f180f576c2c82d6 from qemu
2018-02-07 10:09:26 -05:00
Lioncash dd577f5ea5
target/arm: Change the type of vfp.regs
Backports commit 3f68b8a5a6862f856524bb347bf348ae364dd43c from qemu
2018-02-07 09:57:43 -05:00
Lioncash ef07c136b6
target/arm: Add fp16 support to vfp_expand_imm
Backports commit 8081796a75414f9ed5ec3d97158e543ed45908ec from qemu.
2018-02-07 09:47:04 -05:00
Lioncash b55f35ba92
target/arm: Split out vfp_expand_imm
Backports commit e90a99fe6bde9b85bff8c052ade51520f20d9bce from qemu.
2018-02-07 09:44:52 -05:00
Lioncash 4c165ed788
translate-a64: Silence unused variable warning 2018-02-06 08:38:01 -05:00
Merry 29d38d7c22
Merge pull request #10 from lioncash/el-busto-ldst-exclusive
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks
2018-02-05 20:59:25 +00:00
Lioncash 1e451b386a
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks
Backports commit e14f0eb12f920fd96b9f79d15cedd437648e8667 from qemu
2018-02-04 23:17:45 -05:00
Lioncash 4a8a92bad2
Backport optimizations to AArch64's REV16 handling
Backports commits abb1066df313602ef0ca631126bd342d399d5359 and e4256c3cbf7eefebc0bc6e1f472c47c6dd20b996 from qemu.
2018-02-04 14:45:39 -05:00
Lioncash d41b200fd4
A64: Add EOR3 and BCAX support
Backported to unicorn from: https://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg05003.html
2018-01-25 21:18:36 -05:00
Ryan Hileman ae6ea3b91d fix arm64 hang (fix #827) (#828) 2017-05-09 20:19:32 +08:00
zhangwm 4a62409949 arm64eb: arm64 big endian also using little endian instructions. (#816)
* arm64eb: arm64 big endian also using little endian instructions.

* arm64: using another example that depends on endians.

example:
1. store a word: 0x12345678
2. load a byte:
   * little endian : 0x78
   * big endian    : 0x12
2017-05-04 20:00:48 +08:00
xorstream 8e45102b43 Arm support ported. (#736)
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file
2017-01-23 23:30:57 +08:00
xorstream fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Andrew Dutcher 97b10da133 Undo the disaster that was the patch to unicorn github issue #266 and fix it correctly. makes normal self-modifying code work. 2016-08-09 19:35:20 -07:00
Nguyen Anh Quynh 2341f5dd1a code style 2016-01-26 17:37:48 +08:00