Commit graph

5686 commits

Author SHA1 Message Date
Lioncash 3fa54df972
exec.c: Use correct attrs in cpu_memory_rw_debug()
In the softmmu version of cpu_memory_rw_debug(), we ask the
CPU for the attributes to use for the virtual memory access,
and we correctly use those to identify the address space
index. However, we were not passing them in to the
address_space_write_rom() and address_space_rw() functions.

The effect of this was that a memory access from the gdbstub
to a device which had behaviour that was sensitive to the
memory attributes (such as some ARMv8M NVIC registers) was
incorrectly always performed as if non-secure, rather than
using the right security state for the CPU's current state.

Fixes: https://bugs.launchpad.net/qemu/+bug/1812091

Backports commit ea7a5330b79523540ba776c529b09dc8cf3fa0c5 from qemu
2019-01-29 17:05:50 -05:00
Richard Henderson 64f10fa075
target/arm: Fix validation of 32-bit address spaces for aa32
When tsz == 0, aarch32 selects the address space via exclusion,
and there are no "top_bits" remaining that require validation.

Fixes: ba97be9f4a4

Backports commit 36d820af0eddf4fc6a533579b052d8f0085a9fb8 from qemu
2019-01-29 16:46:36 -05:00
Richard Henderson 3f0781e39b
tcg/aarch64: Implement vector minmax arithmetic
Backports commit 93f332a50371936ea02392bdb748c8140ef3f06a from qemu
2019-01-29 16:44:09 -05:00
Richard Henderson 8a012c3929
tcg/aarch64: Implement vector saturating arithmetic
Backports commit d32648d445c534cea7e2ad7ed8608208aa8831c1 from qemu
2019-01-29 16:42:50 -05:00
Richard Henderson 63d1aae6b2
tcg/i386: Implement vector minmax arithmetic
The avx instruction set does not directly provide MO_64.
We can still implement 64-bit with comparison and vpblendvb.

Backports commit bc37faf4cb2baa77c44298c01558970b88d32808 from qemu
2019-01-29 16:41:11 -05:00
Richard Henderson 5518b543ed
tcg/i386: Implement vector saturating arithmetic
Only MO_8 and MO_16 are implemented, since that's all the
instruction set provides.

Backports commit 8ffafbcec275e61f6a1a17ac1d0bd918d5b23db3 from qemu
2019-01-29 16:37:55 -05:00
Richard Henderson 24e65f60ed
tcg/i386: Split subroutines out of tcg_expand_vec_op
This routine was becoming too large.

Backports commit 44f1441dbe14e7174a707d7e7ecbc2c8e080bfda from qemu
2019-01-29 16:33:59 -05:00
Richard Henderson fb684825c8
tcg: Add opcodes for vector minmax arithmetic
Backports commit dd0a0fcdd8848c2a18970c44a62bd8f394c2b495 from qemu
2019-01-29 16:24:52 -05:00
Richard Henderson e0266239ea
tcg: Add opcodes for vector saturated arithmetic
Backports commit 8afaf0506606f8003ef696df849c5a98637a7a83 from qemu
2019-01-29 16:14:34 -05:00
Richard Henderson f1f2d78a52
tcg: Add write_aofs to GVecGen4
This allows writing 2 output, 3 input operations.

Backports commit 5d6acdd4a485f15b1081acc523b99c1f1a7c42ab from qemu
2019-01-29 16:00:57 -05:00
Richard Henderson e08d0feee4
tcg: Add gvec expanders for nand, nor, eqv
Backports commit f550805d8309500d642f640af8d9928958465478 from qemu
2019-01-29 15:57:28 -05:00
Richard Henderson 11664d444e
tcg: Add logical simplifications during gvec expand
We handle many of these during integer expansion, and the
rest of them during integer optimization.

Backports commit 9a9eda78e4e56051485efb65e01748084f99ac3c from qemu
2019-01-29 15:49:00 -05:00
Lioncash 4aaa75d05b
compiler: Add missing container_of macro for MSVC 2019-01-28 09:27:55 -05:00
Lioncash 65e5d72a94
compiler: Add glue macros for MSVC 2019-01-28 09:26:01 -05:00
Lioncash 3d4f37b78f
osdep: Conditionally include non-Windows headers 2019-01-28 09:24:20 -05:00
Lioncash 977ad292b3
accel/translate-all: Get rid of variable shadowing 2019-01-28 09:17:37 -05:00
Lioncash ce8697f978
accel/translate-all: Convert a void* cast into an unsigned char* cast
Strictly speaking, as far as the standard care, performing pointer
arithmetic on a void* type is ill formed. This is a GNU extension that
allows this. Instead, just use unsigned char* which preserves the same
behavior.
2019-01-28 09:14:33 -05:00
Lioncash d020acd771
qemu/compiler: Define likely() and unlikely() preprocessor macros if they don't exist
Makes the code more functional with MSVC
2019-01-28 09:10:03 -05:00
Lioncash 80e7661555
msvc: Update qapi source files 2019-01-28 09:03:05 -05:00
Lioncash fd019b5bfd
msvc: Update aarch64 project files
Amends project files to include the recently-added pauth_helper.c file.
2019-01-28 08:58:46 -05:00
Paolo Bonzini 54c93c5198
decodetree: re.fullmatch was added in 3.4
Python 3 versions earlier than 3.4 do not have it, use the
same workaround that is in place for 3.0.

Backports commit 651514df88fd53d537b3b78a7548663cc0816b1b from qemu
2019-01-25 13:47:47 -05:00
Yongbok Kim 75954fa97d
target/mips: Add I6500 core configuration
Add I6500 core configuration. Note that this configuration is
supported only on best-effort basis due to the lack of certain
features in QEMU.

Backports commit ca1ffd14ed8a11ad88619c0478e5ea58f0af5137 from qemu
2019-01-25 13:46:18 -05:00
Stefan Markovic 9a064bafe3
target/mips: nanoMIPS: Fix branch handling
Fix nanoMIPS branch handling.

Backports commit 697b7b6bc570c0fe4e32d079930fea6cd4cace6b from qemu
2019-01-25 12:50:26 -05:00
Aleksandar Markovic dbeb82e424
target/mips: Extend gen_scwp() functionality to support EVA
Extend gen_scwp() functionality to support EVA by adding an
additional argument, modify internals of the function to handle
new functionality, and accordingly change its invocations.

Backports commit 8d5388c1de8bf207316369213bd950bafa6badda from qemu
2019-01-25 12:46:46 -05:00
Aleksandar Markovic 49e7e28ec9
target/mips: Correct the second argument type of cpu_supports_isa()
"insn_flags" bitfield was expanded from 32-bit to 64-bit in commit
f9c9cd63e3. However, this was not reflected on the second argument
of the function cpu_supports_isa(). By chance, this did not create
some wrong behavior, since the left-most halves of all instances of
the second argument are currently all zeros. However, this is still
a bug waiting to happen. Correct this by changing the type of the
second argument to be always 64-bit.

Backports commit 5b1e098128367d6ef7cb2d1e99a55fcf4fa9cdde from qemu
2019-01-25 12:45:21 -05:00
Aleksandar Markovic fc2e767e17
target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers
Rename macros for extracting 3-bit-coded GPR numbers, to achieve
better consistency with the nanoMIPS documentation.

Backports commit 99e49abf119f700bf8664b7dfc60c22d9eaf9159 from qemu
2019-01-25 12:43:26 -05:00
Aleksandar Markovic adecea4679
target/mips: nanoMIPS: Remove an unused macro
Remove a macro that is never used.

Backports commit be3a131a057ce30038a179d718d15be9383b1258 from qemu
2019-01-25 12:41:40 -05:00
Aleksandar Markovic afde79b8f9
target/mips: nanoMIPS: Remove duplicate macro definitions
Several macros were defined twice, with identical values, so
remove duplicates.

Previously added in 80845edf37b.

This reverts commit 6bfa9f4c9cf24d6cfaaa227722e9cdcca1ad6fe9.

Backports commit 362d2e72546923f8f410733cc286ae5528c7811a from qemu
2019-01-25 12:40:53 -05:00
Thomas Huth a7c8939b0d
include/fpu/softfloat: Fix compilation with Clang on s390x
Clang v7.0.1 does not like the __int128 variable type for inline
assembly on s390x:

In file included from fpu/softfloat.c:97:
include/fpu/softfloat-macros.h:647:9: error: inline asm error:
This value type register class is not natively supported!
asm("dlgr %0, %1" : "+r"(n) : "r"(d));
^

Disable this code part there now when compiling with Clang, so that
the generic code gets used instead.

Backports commit 2c00542c70b9cbd6da510c97cd3d46adcf9e3efc from qemu
2019-01-24 18:37:51 -05:00
Lioncash 29d84a9296
target: Resolve repeated typedef warnings 2019-01-22 20:27:35 -05:00
Thomas Huth 72abfa9588
configure: Force the C standard to gnu99
Different versions of GCC and Clang use different versions of the C standard.
This repeatedly caused problems already, e.g. with duplicated typedefs:

https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg05829.html

or with for-loop variable initializers:

https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg00237.html

To avoid these problems, we should enforce the C language version to the
same level for all compilers. Since our minimum compiler versions is
GCC v4.8, our best option is "gnu99" for C code right now ("gnu17" is not
available there yet, and "gnu11" is marked as "experimental"), and "gnu++98"
for the few C++ code that we have in the repository.

Backports commit 7be41675f7cb16be7c8d2554add7a63fa43781a8 from qemu
2019-01-22 20:18:58 -05:00
Fredrik Noring baf2fe0fc1
target/mips: Introduce 32 R5900 multimedia registers
The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Backports commit a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd from qemu
2019-01-22 20:14:56 -05:00
Aleksandar Markovic 3bf320249e
target/mips: Rename 'rn' to 'register_name'
Rename 'rn' to 'register_name' in CP0-related handlers.

Backports commit 294fc2ea7f8af913523bf004433704377d9ee7a8 from qemu
2019-01-22 19:57:42 -05:00
Aleksandar Markovic 591ec2a44f
target/mips: Add CP0 register MemoryMapID
Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.

Backports commit 3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60 from qemu
2019-01-22 19:56:08 -05:00
Aleksandar Markovic 3a276522ac
target/mips: Amend preprocessor constants for CP0 registers
Correct existing CP0-related preprocessor constants (replace
"CPO" with "CP0" (form letter "O" to digit "0", when needed).
Besides, add preprocessor constants for CP0 subregisters.
The names of the subregisters were chosen to be in sync with
the table of corresponding assembler mnemonics found in the
documentation for I6500 and I6400 (release 1.0).

Backports commit 04992c8cd1c43ecdba39dd8c916db092db6ebae0 from qemu
2019-01-22 19:55:04 -05:00
Yongbok Kim 33e9ea3f10
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
Provide R/W access to SAARI and SAAR CP0 registers.

Backports commit 5fb2dcd17921be71b55fb62d59a12992707d2d3e from qemu
2019-01-22 19:51:38 -05:00
Yongbok Kim 6f850b88e4
target/mips: Add fields for SAARI and SAAR CP0 registers
Add fields for SAARI and SAAR CP0 registers.

Backports commit 167db30e981cd72bef15182178037e51afc8e40d from qemu
2019-01-22 19:40:31 -05:00
Aleksandar Markovic c0125e41a1
target/mips: Use preprocessor constants for 32 major CP0 registers
Use preprocessor constants for 32 major CP0 registers.

Backports commit 46d7642fcc97ac108c8080fbe41bc5d00bb537f2 from qemu
2019-01-22 19:38:43 -05:00
Aleksandar Markovic 0feca79dd5
target/mips: Add preprocessor constants for 32 major CP0 registers
Add preprocessor constants for 32 major CP0 registers.

Backports commit efd27d3f08655fc2bcf79a529566aee2cb2e81f8 from qemu
2019-01-22 19:22:39 -05:00
Aleksandar Markovic 9834762d2c
target/mips: Move comment containing summary of CP0 registers
Move comment containing summary of CP0 registers. Checkpatch
script reported some tabs in the resutling diff, so convert
these tabs to spaces too.

Backports commit ea9c5e836e205a87038c8153282d0b6d9234cda2 from qemu
2019-01-22 19:19:54 -05:00
Lioncash b17d2d4059
qemu/compiler: Add fallback macro for __has_builtin
Prevents compilation errors on non-clang compilers.
2019-01-22 19:02:49 -05:00
Aaron Lindsay cfd84d84f6
target/arm: Implement PMSWINC
Backports commit 0d4bfd7df809863b1f45fad35229fb9419527d06 from qemu
2019-01-22 18:59:26 -05:00
Aaron Lindsay 9727b7c3e0
target/arm: PMU: Set PMCR.N to 4
This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.

Backports commit ac689a2e5155d129acaa39603e2a7a29abd90d89 from qemu
2019-01-22 18:55:34 -05:00
Aaron Lindsay dede23994a
target/arm: PMU: Add instruction and cycle events
The instruction event is only enabled when icount is used, cycles are
always supported. Always defining get_cycle_count (but altering its
behavior depending on CONFIG_USER_ONLY) allows us to remove some
CONFIG_USER_ONLY #defines throughout the rest of the code.

Backports commit b2e2372511946fae86fbb8709edec7a41c6f3167 from qemu
2019-01-22 18:54:01 -05:00
Aaron Lindsay 1a815a1afc
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
Add arrays to hold the registers, the definitions themselves, access
functions, and logic to reset counters when PMCR.P is set. Update
filtering code to support counters other than PMCCNTR. Support migration
with raw read/write functions.

Backports commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59 from qemu
2019-01-22 18:07:53 -05:00
Aaron Lindsay c8c3defb18
target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
This commit doesn't add any supported events, but provides the framework
for adding them. We store the pm_event structs in a simple array, and
provide the mapping from the event numbers to array indexes in the
supported_event_map array. Because the value of PMCEID[01] depends upon
which events are supported at runtime, generate it dynamically.

Backports commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a from qemu
2019-01-22 17:45:36 -05:00
Aaron Lindsay 67accd4d88
target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
Backports commit cad8673744d0914587cd7380e70df11e8c4a0f50 from qemu
2019-01-22 17:32:29 -05:00
Aaron Lindsay 346e4226ec
target/arm: Define FIELDs for ID_DFR0
This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.

Backports commit beceb99c0c1218d0b55cc04ce6ef77579d3416cb from qemu
2019-01-22 17:26:25 -05:00
Aaron Lindsay 4ff0389d2d
target/arm: Implement PMOVSSET
Add an array for PMOVSSET so we only define it for v7ve+ platforms

Backports commit 327dd5108bb3b66bb5102b659e83a4348a005f5e from qemu
2019-01-22 17:25:22 -05:00
Aaron Lindsay d6d1d49cdd
target/arm: Allow AArch32 access for PMCCFILTR
Backports commit 4b8afa1f99c3575f6cfb26770f90e9fd7bc45468 from qemu
2019-01-22 17:19:03 -05:00