2015-08-21 07:04:50 +00:00
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* define it to use liveness analysis (better code) */
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#define USE_TCG_OPTIMIZATIONS
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2018-02-19 06:04:06 +00:00
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#include "qemu/osdep.h"
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2015-08-21 07:04:50 +00:00
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/* Define to jump the ELF file used to communicate with GDB. */
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#undef DEBUG_JIT
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2018-02-22 14:24:12 +00:00
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#include "qemu/cutils.h"
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2015-08-21 07:04:50 +00:00
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#include "qemu/host-utils.h"
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#include "qemu/timer.h"
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/* Note: the long term plan is to reduce the dependencies on the QEMU
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CPU definitions. Currently they are used for qemu_ld/st
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instructions */
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#define NO_CPU_IO_DEFS
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#include "cpu.h"
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2018-02-24 07:26:26 +00:00
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#include "exec/cpu-common.h"
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#include "exec/exec-all.h"
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2015-08-21 07:04:50 +00:00
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#include "tcg-op.h"
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#if UINTPTR_MAX == UINT32_MAX
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# define ELF_CLASS ELFCLASS32
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#else
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# define ELF_CLASS ELFCLASS64
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#endif
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#ifdef HOST_WORDS_BIGENDIAN
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# define ELF_DATA ELFDATA2MSB
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#else
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# define ELF_DATA ELFDATA2LSB
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#endif
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#include "elf.h"
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2018-02-21 01:38:57 +00:00
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/* Forward declarations for functions declared in tcg-target.inc.c and
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used here. */
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2015-08-21 07:04:50 +00:00
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static void tcg_target_init(TCGContext *s);
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2018-03-01 20:36:50 +00:00
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static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
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2015-08-21 07:04:50 +00:00
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static void tcg_target_qemu_prologue(TCGContext *s);
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static void patch_reloc(tcg_insn_unit *code_ptr, int type,
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intptr_t value, intptr_t addend);
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/* The CIE and FDE header definitions will be common to all hosts. */
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typedef struct {
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2018-02-24 22:32:36 +00:00
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//uint32_t QEMU_ALIGNED(sizeof(void *), len);
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uint32_t QEMU_ALIGNED(8, len);
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2015-08-21 07:04:50 +00:00
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uint32_t id;
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uint8_t version;
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char augmentation[1];
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uint8_t code_align;
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uint8_t data_align;
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uint8_t return_column;
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} DebugFrameCIE;
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2017-01-19 11:50:28 +00:00
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QEMU_PACK( typedef struct {
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2018-02-24 22:32:36 +00:00
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// uint32_t QEMU_ALIGNED(sizeof(void *), len);
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uint32_t QEMU_ALIGNED(8, len);
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2015-08-21 07:04:50 +00:00
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uint32_t cie_offset;
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uintptr_t func_start;
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uintptr_t func_len;
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2017-01-19 11:50:28 +00:00
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}) DebugFrameFDEHeader;
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2015-08-21 07:04:50 +00:00
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2017-01-19 11:50:28 +00:00
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QEMU_PACK( typedef struct {
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2015-08-21 07:04:50 +00:00
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DebugFrameCIE cie;
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DebugFrameFDEHeader fde;
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2017-01-19 11:50:28 +00:00
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}) DebugFrameHeader;
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2015-08-21 07:04:50 +00:00
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2018-02-21 01:38:57 +00:00
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/* Forward declarations for functions declared and used in tcg-target.inc.c. */
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2018-03-01 20:45:36 +00:00
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static const char *target_parse_constraint(TCGArgConstraint *ct,
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const char *ct_str, TCGType type);
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2015-08-21 07:04:50 +00:00
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static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
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intptr_t arg2);
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static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
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static void tcg_out_movi(TCGContext *s, TCGType type,
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TCGReg ret, tcg_target_long arg);
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static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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const int *const_args);
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2018-03-06 16:49:50 +00:00
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#if TCG_TARGET_MAYBE_vec
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static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
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unsigned vece, const TCGArg *args,
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const int *const_args);
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#else
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static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
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unsigned vece, const TCGArg *args,
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const int *const_args)
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{
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g_assert_not_reached();
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}
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#endif
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2015-08-21 07:04:50 +00:00
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static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
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intptr_t arg2);
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2018-02-25 06:41:28 +00:00
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static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
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TCGReg base, intptr_t ofs);
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2015-08-21 07:04:50 +00:00
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static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
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static int tcg_target_const_match(tcg_target_long val, TCGType type,
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const TCGArgConstraint *arg_ct);
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2018-03-05 03:03:22 +00:00
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#ifdef TCG_TARGET_NEED_LDST_LABELS
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static bool tcg_out_ldst_finalize(TCGContext *s);
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#endif
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2015-08-21 07:04:50 +00:00
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2018-03-05 08:22:14 +00:00
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#define TCG_HIGHWATER 1024
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2015-08-21 07:04:50 +00:00
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#if TCG_TARGET_INSN_UNIT_SIZE == 1
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_out8(TCGContext *s, uint8_t v)
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2015-08-21 07:04:50 +00:00
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{
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*s->code_ptr++ = v;
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}
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_patch8(tcg_insn_unit *p,
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2015-08-21 07:04:50 +00:00
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uint8_t v)
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{
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*p = v;
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}
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#endif
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#if TCG_TARGET_INSN_UNIT_SIZE <= 2
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_out16(TCGContext *s, uint16_t v)
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2015-08-21 07:04:50 +00:00
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{
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if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
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2017-01-19 11:50:28 +00:00
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*s->code_ptr++ = (tcg_insn_unit)v;
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2015-08-21 07:04:50 +00:00
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} else {
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tcg_insn_unit *p = s->code_ptr;
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memcpy(p, &v, sizeof(v));
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s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE);
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}
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}
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_patch16(tcg_insn_unit *p,
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2015-08-21 07:04:50 +00:00
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uint16_t v)
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{
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if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
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2017-01-19 11:50:28 +00:00
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*p = (tcg_insn_unit)v;
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2015-08-21 07:04:50 +00:00
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} else {
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memcpy(p, &v, sizeof(v));
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}
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}
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#endif
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#if TCG_TARGET_INSN_UNIT_SIZE <= 4
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_out32(TCGContext *s, uint32_t v)
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2015-08-21 07:04:50 +00:00
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{
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if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
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*s->code_ptr++ = v;
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} else {
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tcg_insn_unit *p = s->code_ptr;
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memcpy(p, &v, sizeof(v));
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s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE);
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}
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}
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_patch32(tcg_insn_unit *p,
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2015-08-21 07:04:50 +00:00
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uint32_t v)
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{
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if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
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*p = v;
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} else {
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memcpy(p, &v, sizeof(v));
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}
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}
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#endif
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#if TCG_TARGET_INSN_UNIT_SIZE <= 8
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_out64(TCGContext *s, uint64_t v)
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2015-08-21 07:04:50 +00:00
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{
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if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
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2017-01-19 11:50:28 +00:00
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*s->code_ptr++ = (tcg_insn_unit)v;
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2015-08-21 07:04:50 +00:00
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} else {
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tcg_insn_unit *p = s->code_ptr;
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memcpy(p, &v, sizeof(v));
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s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE);
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}
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}
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2017-01-19 11:50:28 +00:00
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static QEMU_UNUSED_FUNC inline void tcg_patch64(tcg_insn_unit *p,
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2015-08-21 07:04:50 +00:00
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uint64_t v)
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{
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if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
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2017-01-19 11:50:28 +00:00
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*p = (tcg_insn_unit)v;
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2015-08-21 07:04:50 +00:00
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} else {
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memcpy(p, &v, sizeof(v));
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}
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}
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#endif
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/* label relocation processing */
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static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
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2018-02-09 19:38:37 +00:00
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TCGLabel *l, intptr_t addend)
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2015-08-21 07:04:50 +00:00
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{
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TCGRelocation *r;
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if (l->has_value) {
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/* FIXME: This may break relocations on RISC targets that
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2018-03-12 22:03:02 +00:00
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modify instruction fields in place. The caller may not have
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2015-08-21 07:04:50 +00:00
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written the initial value. */
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patch_reloc(code_ptr, type, l->u.value, addend);
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} else {
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/* add a new relocation entry */
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r = tcg_malloc(s, sizeof(TCGRelocation));
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r->type = type;
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r->ptr = code_ptr;
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r->addend = addend;
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r->next = l->u.first_reloc;
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l->u.first_reloc = r;
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}
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}
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2018-02-09 19:38:37 +00:00
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static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
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2015-08-21 07:04:50 +00:00
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{
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intptr_t value = (intptr_t)ptr;
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TCGRelocation *r;
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2018-02-23 18:52:01 +00:00
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tcg_debug_assert(!l->has_value);
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2015-08-21 07:04:50 +00:00
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for (r = l->u.first_reloc; r != NULL; r = r->next) {
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patch_reloc(r->ptr, r->type, value, r->addend);
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}
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l->has_value = 1;
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l->u.value_ptr = ptr;
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}
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2018-02-09 19:10:32 +00:00
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TCGLabel *gen_new_label(TCGContext *s)
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2015-08-21 07:04:50 +00:00
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{
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2018-02-09 19:47:48 +00:00
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TCGLabel *l = tcg_malloc(s, sizeof(TCGLabel));
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TCGLabel ltmp = {0};
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ltmp.id = s->nb_labels++;
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*l = ltmp;
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2018-02-09 19:10:32 +00:00
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return l;
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2015-08-21 07:04:50 +00:00
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}
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2018-02-21 01:38:57 +00:00
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#include "tcg-target.inc.c"
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2015-08-21 07:04:50 +00:00
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/* pool based memory allocation */
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void *tcg_malloc_internal(TCGContext *s, int size)
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{
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TCGPool *p;
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int pool_size;
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if (size > TCG_POOL_CHUNK_SIZE) {
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/* big malloc: insert a new pool (XXX: could optimize) */
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p = g_malloc(sizeof(TCGPool) + size);
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p->size = size;
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p->next = s->pool_first_large;
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s->pool_first_large = p;
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return p->data;
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} else {
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p = s->pool_current;
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if (!p) {
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p = s->pool_first;
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if (!p)
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goto new_pool;
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} else {
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if (!p->next) {
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new_pool:
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pool_size = TCG_POOL_CHUNK_SIZE;
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p = g_malloc(sizeof(TCGPool) + pool_size);
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p->size = pool_size;
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p->next = NULL;
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if (s->pool_current)
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s->pool_current->next = p;
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else
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s->pool_first = p;
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} else {
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p = p->next;
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}
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}
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}
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s->pool_current = p;
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s->pool_cur = p->data + size;
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s->pool_end = p->data + p->size;
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return p->data;
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}
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void tcg_pool_reset(TCGContext *s)
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{
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TCGPool *p, *t;
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for (p = s->pool_first_large; p; p = t) {
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t = p->next;
|
2016-12-21 14:28:36 +00:00
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g_free(p);
|
2015-08-21 07:04:50 +00:00
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|
|
}
|
|
|
|
s->pool_first_large = NULL;
|
|
|
|
s->pool_cur = s->pool_end = NULL;
|
|
|
|
s->pool_current = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
typedef struct TCGHelperInfo {
|
|
|
|
void *func;
|
|
|
|
const char *name;
|
|
|
|
unsigned flags;
|
|
|
|
unsigned sizemask;
|
|
|
|
} TCGHelperInfo;
|
|
|
|
|
|
|
|
#include "exec/helper-proto.h"
|
|
|
|
|
|
|
|
static const TCGHelperInfo all_helpers[] = {
|
|
|
|
#include "exec/helper-tcg.h"
|
|
|
|
};
|
|
|
|
|
2018-03-01 20:36:50 +00:00
|
|
|
static void process_op_defs(TCGContext *s);
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
void tcg_context_init(TCGContext *s)
|
|
|
|
{
|
|
|
|
int op, total_args, n, i;
|
|
|
|
TCGOpDef *def;
|
|
|
|
TCGArgConstraint *args_ct;
|
|
|
|
int *sorted_args;
|
|
|
|
GHashTable *helper_table;
|
|
|
|
|
|
|
|
memset(s, 0, sizeof(*s));
|
|
|
|
s->nb_globals = 0;
|
|
|
|
|
|
|
|
// copy original tcg_op_defs_org for private usage
|
|
|
|
s->tcg_op_defs = g_malloc(sizeof(tcg_op_defs_org));
|
|
|
|
memcpy(s->tcg_op_defs, tcg_op_defs_org, sizeof(tcg_op_defs_org));
|
|
|
|
|
|
|
|
/* Count total number of arguments and allocate the corresponding
|
|
|
|
space */
|
|
|
|
total_args = 0;
|
|
|
|
for(op = 0; op < NB_OPS; op++) {
|
|
|
|
def = &s->tcg_op_defs[op];
|
|
|
|
n = def->nb_iargs + def->nb_oargs;
|
|
|
|
total_args += n;
|
|
|
|
}
|
|
|
|
|
|
|
|
args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
|
|
|
|
sorted_args = g_malloc(sizeof(int) * total_args);
|
|
|
|
|
|
|
|
for(op = 0; op < NB_OPS; op++) {
|
|
|
|
def = &s->tcg_op_defs[op];
|
|
|
|
def->args_ct = args_ct;
|
|
|
|
def->sorted_args = sorted_args;
|
|
|
|
n = def->nb_iargs + def->nb_oargs;
|
|
|
|
sorted_args += n;
|
|
|
|
args_ct += n;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register helpers. */
|
|
|
|
/* Use g_direct_hash/equal for direct pointer comparisons on func. */
|
|
|
|
s->helpers = helper_table = g_hash_table_new(NULL, NULL);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
|
|
|
|
g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
|
|
|
|
(gpointer)&all_helpers[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
tcg_target_init(s);
|
2018-03-01 20:36:50 +00:00
|
|
|
process_op_defs(s);
|
2018-02-21 00:24:31 +00:00
|
|
|
|
|
|
|
/* Reverse the order of the saved registers, assuming they're all at
|
|
|
|
the start of tcg_target_reg_alloc_order. */
|
|
|
|
for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) {
|
|
|
|
int r = tcg_target_reg_alloc_order[n];
|
|
|
|
if (tcg_regset_test_reg(s->tcg_target_call_clobber_regs, r)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (i = 0; i < n; ++i) {
|
|
|
|
s->indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i];
|
|
|
|
}
|
|
|
|
for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) {
|
|
|
|
s->indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i];
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-03-03 22:01:28 +00:00
|
|
|
/*
|
|
|
|
* Allocate TBs right before their corresponding translated code, making
|
|
|
|
* sure that TBs and code are on different cache lines.
|
|
|
|
*/
|
|
|
|
TranslationBlock *tcg_tb_alloc(TCGContext *s)
|
|
|
|
{
|
|
|
|
uintptr_t align = s->uc->qemu_icache_linesize;
|
|
|
|
TranslationBlock *tb;
|
|
|
|
void *next;
|
|
|
|
|
|
|
|
tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align);
|
|
|
|
next = (void *)ROUND_UP((uintptr_t)(tb + 1), align);
|
|
|
|
|
|
|
|
if (unlikely(next > s->code_gen_highwater)) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
s->code_gen_ptr = next;
|
2018-03-05 03:17:11 +00:00
|
|
|
s->data_gen_ptr = NULL;
|
2018-03-03 22:01:28 +00:00
|
|
|
return tb;
|
|
|
|
}
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
void tcg_prologue_init(TCGContext *s)
|
|
|
|
{
|
2018-02-16 15:25:01 +00:00
|
|
|
size_t prologue_size, total_size;
|
|
|
|
void *buf0, *buf1;
|
|
|
|
|
|
|
|
/* Put the prologue at the beginning of code_gen_buffer. */
|
|
|
|
buf0 = s->code_gen_buffer;
|
2018-03-05 16:25:48 +00:00
|
|
|
total_size = s->code_gen_buffer_size;
|
2018-02-16 15:25:01 +00:00
|
|
|
s->code_ptr = buf0;
|
|
|
|
s->code_buf = buf0;
|
2018-03-05 16:25:48 +00:00
|
|
|
s->data_gen_ptr = NULL;
|
2018-02-16 15:25:01 +00:00
|
|
|
s->code_gen_prologue = buf0;
|
|
|
|
|
2018-03-05 16:25:48 +00:00
|
|
|
/* Compute a high-water mark, at which we voluntarily flush the buffer
|
|
|
|
and start over. The size here is arbitrary, significantly larger
|
|
|
|
than we expect the code generation for any one opcode to require. */
|
|
|
|
s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER);
|
|
|
|
|
|
|
|
#ifdef TCG_TARGET_NEED_POOL_LABELS
|
|
|
|
s->pool_labels = NULL;
|
|
|
|
#endif
|
|
|
|
|
2018-02-16 15:25:01 +00:00
|
|
|
/* Generate the prologue. */
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_target_qemu_prologue(s);
|
2018-03-05 16:25:48 +00:00
|
|
|
|
|
|
|
#ifdef TCG_TARGET_NEED_POOL_LABELS
|
|
|
|
/* Allow the prologue to put e.g. guest_base into a pool entry. */
|
|
|
|
{
|
|
|
|
bool ok = tcg_out_pool_finalize(s);
|
|
|
|
tcg_debug_assert(ok);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-02-16 15:25:01 +00:00
|
|
|
buf1 = s->code_ptr;
|
|
|
|
flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1);
|
|
|
|
|
|
|
|
/* Deduct the prologue from the buffer. */
|
|
|
|
prologue_size = tcg_current_code_size(s);
|
|
|
|
s->code_gen_ptr = buf1;
|
|
|
|
s->code_gen_buffer = buf1;
|
|
|
|
s->code_buf = buf1;
|
2018-03-05 16:25:48 +00:00
|
|
|
total_size -= prologue_size;
|
2018-02-16 15:25:01 +00:00
|
|
|
s->code_gen_buffer_size = total_size;
|
|
|
|
|
|
|
|
// Unicorn: commented out
|
|
|
|
// tcg_register_jit(s->code_gen_buffer, total_size);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
#ifdef DEBUG_DISAS
|
|
|
|
if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
|
|
|
|
size_t size = tcg_current_code_size(s);
|
|
|
|
qemu_log("PROLOGUE: [size=%zu]\n", size);
|
2018-02-16 15:25:01 +00:00
|
|
|
qemu_log("PROLOGUE: [size=%zu]\n", prologue_size);
|
2018-03-05 16:25:48 +00:00
|
|
|
if (s->data_gen_ptr) {
|
|
|
|
size_t code_size = s->data_gen_ptr - buf0;
|
|
|
|
size_t data_size = prologue_size - code_size;
|
|
|
|
size_t i;
|
|
|
|
|
|
|
|
// Unicorn: commented out
|
|
|
|
//log_disas(buf0, code_size);
|
|
|
|
|
|
|
|
for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) {
|
|
|
|
if (sizeof(tcg_target_ulong) == 8) {
|
|
|
|
qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n",
|
|
|
|
(uintptr_t)s->data_gen_ptr + i,
|
|
|
|
*(uint64_t *)(s->data_gen_ptr + i));
|
|
|
|
} else {
|
|
|
|
qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n",
|
|
|
|
(uintptr_t)s->data_gen_ptr + i,
|
|
|
|
*(uint32_t *)(s->data_gen_ptr + i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
2018-03-05 16:28:36 +00:00
|
|
|
// Unicorn: commented out
|
|
|
|
//log_disas(buf0, prologue_size);
|
2018-03-05 16:25:48 +00:00
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
qemu_log("\n");
|
|
|
|
qemu_log_flush();
|
|
|
|
}
|
|
|
|
#endif
|
2018-03-03 01:56:29 +00:00
|
|
|
|
|
|
|
/* Assert that goto_ptr is implemented completely. */
|
|
|
|
if (TCG_TARGET_HAS_goto_ptr) {
|
|
|
|
tcg_debug_assert(s->code_gen_epilogue != NULL);
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void tcg_func_start(TCGContext *s)
|
|
|
|
{
|
|
|
|
tcg_pool_reset(s);
|
|
|
|
s->nb_temps = s->nb_globals;
|
|
|
|
|
|
|
|
/* No temps have been previously allocated for size or locality. */
|
|
|
|
memset(s->free_temps, 0, sizeof(s->free_temps));
|
|
|
|
|
2018-05-11 15:24:59 +00:00
|
|
|
s->nb_ops = 0;
|
2015-08-21 07:04:50 +00:00
|
|
|
s->nb_labels = 0;
|
|
|
|
s->current_frame_offset = s->frame_start;
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_TCG
|
|
|
|
s->goto_tb_issue_mask = 0;
|
|
|
|
#endif
|
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_INIT(&s->ops);
|
|
|
|
QTAILQ_INIT(&s->free_ops);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-19 16:17:39 +00:00
|
|
|
static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
|
|
|
|
{
|
|
|
|
int n = s->nb_temps++;
|
|
|
|
tcg_debug_assert(n < TCG_MAX_TEMPS);
|
|
|
|
return memset(&s->temps[n], 0, sizeof(TCGTemp));
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline TCGTemp *tcg_global_alloc(TCGContext *s)
|
|
|
|
{
|
2018-03-05 12:21:07 +00:00
|
|
|
TCGTemp *ts;
|
|
|
|
|
2018-02-19 16:17:39 +00:00
|
|
|
tcg_debug_assert(s->nb_globals == s->nb_temps);
|
|
|
|
s->nb_globals++;
|
2018-03-05 12:21:07 +00:00
|
|
|
ts = tcg_temp_alloc(s);
|
|
|
|
ts->temp_global = 1;
|
|
|
|
|
|
|
|
return ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-03-05 13:53:51 +00:00
|
|
|
static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
|
|
|
|
TCGReg reg, const char *name)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
|
|
|
TCGTemp *ts;
|
|
|
|
|
2018-02-08 18:03:59 +00:00
|
|
|
if (TCG_TARGET_REG_BITS == 32 && type != TCG_TYPE_I32) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_abort();
|
2018-02-08 18:03:59 +00:00
|
|
|
}
|
2018-02-19 16:17:39 +00:00
|
|
|
|
|
|
|
ts = tcg_global_alloc(s);
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->base_type = type;
|
|
|
|
ts->type = type;
|
|
|
|
ts->fixed_reg = 1;
|
|
|
|
ts->reg = reg;
|
|
|
|
ts->name = name;
|
|
|
|
tcg_regset_set_reg(s->reserved_regs, reg);
|
2018-02-19 16:17:39 +00:00
|
|
|
|
2018-03-05 13:53:51 +00:00
|
|
|
return ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-19 07:06:03 +00:00
|
|
|
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
|
2018-02-08 18:03:59 +00:00
|
|
|
{
|
|
|
|
s->frame_start = start;
|
|
|
|
s->frame_end = start + size;
|
2018-03-05 13:53:51 +00:00
|
|
|
s->frame_temp
|
|
|
|
= tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
|
2018-02-08 18:03:59 +00:00
|
|
|
}
|
|
|
|
|
2018-02-19 07:06:03 +00:00
|
|
|
TCGv_i32 tcg_global_reg_new_i32(TCGContext *s, TCGReg reg, const char *name)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 13:53:51 +00:00
|
|
|
TCGTemp *t;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-08 18:03:59 +00:00
|
|
|
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
|
|
|
|
tcg_abort();
|
|
|
|
}
|
2018-03-05 13:53:51 +00:00
|
|
|
t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
|
|
|
|
return temp_tcgv_i32(s, t);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-19 07:06:03 +00:00
|
|
|
TCGv_i64 tcg_global_reg_new_i64(TCGContext *s, TCGReg reg, const char *name)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 13:53:51 +00:00
|
|
|
TCGTemp *t;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-08 18:03:59 +00:00
|
|
|
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
|
2018-03-05 13:53:51 +00:00
|
|
|
t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
|
|
|
|
return temp_tcgv_i64(s, t);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-03-05 13:53:51 +00:00
|
|
|
TCGTemp *tcg_global_mem_new_internal(TCGContext *s, TCGType type, TCGv_ptr base,
|
|
|
|
intptr_t offset, const char *name)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 14:01:21 +00:00
|
|
|
TCGTemp *base_ts = tcgv_ptr_temp(s, base);
|
2018-02-19 16:17:39 +00:00
|
|
|
TCGTemp *ts = tcg_global_alloc(s);
|
2018-02-21 00:18:44 +00:00
|
|
|
int indirect_reg = 0, bigendian = 0;
|
2018-02-19 16:17:39 +00:00
|
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
|
|
|
bigendian = 1;
|
|
|
|
#endif
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-21 00:18:44 +00:00
|
|
|
if (!base_ts->fixed_reg) {
|
2018-02-26 03:23:00 +00:00
|
|
|
/* We do not support double-indirect registers. */
|
|
|
|
tcg_debug_assert(!base_ts->indirect_reg);
|
2018-02-21 00:18:44 +00:00
|
|
|
base_ts->indirect_base = 1;
|
2018-02-26 03:23:00 +00:00
|
|
|
s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64
|
|
|
|
? 2 : 1);
|
|
|
|
indirect_reg = 1;
|
2018-02-21 00:18:44 +00:00
|
|
|
}
|
|
|
|
|
2018-02-19 16:17:39 +00:00
|
|
|
if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
|
|
|
|
TCGTemp *ts2 = tcg_global_alloc(s);
|
2015-08-21 07:04:50 +00:00
|
|
|
char buf[64];
|
2018-02-19 16:17:39 +00:00
|
|
|
|
|
|
|
ts->base_type = TCG_TYPE_I64;
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->type = TCG_TYPE_I32;
|
2018-02-21 00:18:44 +00:00
|
|
|
ts->indirect_reg = indirect_reg;
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->mem_allocated = 1;
|
2018-02-08 18:03:59 +00:00
|
|
|
ts->mem_base = base_ts;
|
2018-02-19 16:17:39 +00:00
|
|
|
ts->mem_offset = offset + bigendian * 4;
|
2015-08-21 07:04:50 +00:00
|
|
|
pstrcpy(buf, sizeof(buf), name);
|
|
|
|
pstrcat(buf, sizeof(buf), "_0");
|
2018-02-25 06:36:26 +00:00
|
|
|
ts->name = strdup(buf);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-19 16:17:39 +00:00
|
|
|
tcg_debug_assert(ts2 == ts + 1);
|
|
|
|
ts2->base_type = TCG_TYPE_I64;
|
|
|
|
ts2->type = TCG_TYPE_I32;
|
2018-02-21 00:18:44 +00:00
|
|
|
ts2->indirect_reg = indirect_reg;
|
2018-02-19 16:17:39 +00:00
|
|
|
ts2->mem_allocated = 1;
|
|
|
|
ts2->mem_base = base_ts;
|
|
|
|
ts2->mem_offset = offset + (1 - bigendian) * 4;
|
2015-08-21 07:04:50 +00:00
|
|
|
pstrcpy(buf, sizeof(buf), name);
|
|
|
|
pstrcat(buf, sizeof(buf), "_1");
|
2018-02-25 06:36:26 +00:00
|
|
|
ts2->name = g_strdup(buf);
|
2018-02-19 16:17:39 +00:00
|
|
|
} else {
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->base_type = type;
|
|
|
|
ts->type = type;
|
2018-02-21 00:18:44 +00:00
|
|
|
ts->indirect_reg = indirect_reg;
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->mem_allocated = 1;
|
2018-02-08 18:03:59 +00:00
|
|
|
ts->mem_base = base_ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->mem_offset = offset;
|
|
|
|
ts->name = name;
|
|
|
|
}
|
2018-03-05 13:53:51 +00:00
|
|
|
return ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-05-03 18:46:46 +00:00
|
|
|
TCGTemp *tcg_temp_new_internal(TCGContext *s, TCGType type, bool temp_local)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
|
|
|
TCGTemp *ts;
|
|
|
|
int idx, k;
|
|
|
|
|
|
|
|
k = type + (temp_local ? TCG_TYPE_COUNT : 0);
|
|
|
|
idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
|
|
|
|
if (idx < TCG_MAX_TEMPS) {
|
|
|
|
/* There is already an available temp with the right type. */
|
|
|
|
clear_bit(idx, s->free_temps[k].l);
|
|
|
|
|
|
|
|
ts = &s->temps[idx];
|
|
|
|
ts->temp_allocated = 1;
|
2018-02-19 16:17:39 +00:00
|
|
|
tcg_debug_assert(ts->base_type == type);
|
|
|
|
tcg_debug_assert(ts->temp_local == temp_local);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
2018-02-19 16:17:39 +00:00
|
|
|
ts = tcg_temp_alloc(s);
|
|
|
|
if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
|
|
|
|
TCGTemp *ts2 = tcg_temp_alloc(s);
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->base_type = type;
|
|
|
|
ts->type = TCG_TYPE_I32;
|
|
|
|
ts->temp_allocated = 1;
|
|
|
|
ts->temp_local = temp_local;
|
2018-02-19 16:17:39 +00:00
|
|
|
|
|
|
|
tcg_debug_assert(ts2 == ts + 1);
|
|
|
|
ts2->base_type = TCG_TYPE_I64;
|
|
|
|
ts2->type = TCG_TYPE_I32;
|
|
|
|
ts2->temp_allocated = 1;
|
|
|
|
ts2->temp_local = temp_local;
|
|
|
|
} else {
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->base_type = type;
|
|
|
|
ts->type = type;
|
|
|
|
ts->temp_allocated = 1;
|
|
|
|
ts->temp_local = temp_local;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_TCG)
|
|
|
|
s->temps_in_use++;
|
|
|
|
#endif
|
2018-03-05 13:53:51 +00:00
|
|
|
return ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-03-06 16:49:50 +00:00
|
|
|
TCGv_vec tcg_temp_new_vec(TCGContext *s, TCGType type)
|
|
|
|
{
|
|
|
|
TCGTemp *t;
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_TCG
|
|
|
|
switch (type) {
|
|
|
|
case TCG_TYPE_V64:
|
|
|
|
assert(TCG_TARGET_HAS_v64);
|
|
|
|
break;
|
|
|
|
case TCG_TYPE_V128:
|
|
|
|
assert(TCG_TARGET_HAS_v128);
|
|
|
|
break;
|
|
|
|
case TCG_TYPE_V256:
|
|
|
|
assert(TCG_TARGET_HAS_v256);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
t = tcg_temp_new_internal(s, type, 0);
|
|
|
|
return temp_tcgv_vec(s, t);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Create a new temp of the same type as an existing temp. */
|
|
|
|
TCGv_vec tcg_temp_new_vec_matching(TCGContext *s, TCGv_vec match)
|
|
|
|
{
|
|
|
|
TCGTemp *t = tcgv_vec_temp(s, match);
|
|
|
|
|
|
|
|
tcg_debug_assert(t->temp_allocated != 0);
|
|
|
|
|
|
|
|
t = tcg_temp_new_internal(s, t->base_type, 0);
|
|
|
|
return temp_tcgv_vec(s, t);
|
|
|
|
}
|
|
|
|
|
2018-05-03 18:46:46 +00:00
|
|
|
void tcg_temp_free_internal(TCGContext *s, TCGTemp *ts)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 13:53:51 +00:00
|
|
|
int k, idx;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_TCG)
|
|
|
|
s->temps_in_use--;
|
|
|
|
if (s->temps_in_use < 0) {
|
|
|
|
fprintf(stderr, "More temporaries freed than allocated!\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-03-05 13:53:51 +00:00
|
|
|
tcg_debug_assert(ts->temp_global == 0);
|
2018-02-23 18:52:01 +00:00
|
|
|
tcg_debug_assert(ts->temp_allocated != 0);
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->temp_allocated = 0;
|
|
|
|
|
2018-03-05 13:53:51 +00:00
|
|
|
idx = temp_idx(s, ts);
|
2015-08-21 07:04:50 +00:00
|
|
|
k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
|
|
|
|
set_bit(idx, s->free_temps[k].l);
|
|
|
|
}
|
|
|
|
|
|
|
|
TCGv_i32 tcg_const_i32(TCGContext *s, int32_t val)
|
|
|
|
{
|
|
|
|
TCGv_i32 t0;
|
|
|
|
t0 = tcg_temp_new_i32(s);
|
|
|
|
tcg_gen_movi_i32(s, t0, val);
|
|
|
|
return t0;
|
|
|
|
}
|
|
|
|
|
|
|
|
TCGv_i64 tcg_const_i64(TCGContext *s, int64_t val)
|
|
|
|
{
|
|
|
|
TCGv_i64 t0;
|
|
|
|
t0 = tcg_temp_new_i64(s);
|
|
|
|
tcg_gen_movi_i64(s, t0, val);
|
|
|
|
return t0;
|
|
|
|
}
|
|
|
|
|
|
|
|
TCGv_i32 tcg_const_local_i32(TCGContext *s, int32_t val)
|
|
|
|
{
|
|
|
|
TCGv_i32 t0;
|
|
|
|
t0 = tcg_temp_local_new_i32(s);
|
|
|
|
tcg_gen_movi_i32(s, t0, val);
|
|
|
|
return t0;
|
|
|
|
}
|
|
|
|
|
|
|
|
TCGv_i64 tcg_const_local_i64(TCGContext *s, int64_t val)
|
|
|
|
{
|
|
|
|
TCGv_i64 t0;
|
|
|
|
t0 = tcg_temp_local_new_i64(s);
|
|
|
|
tcg_gen_movi_i64(s, t0, val);
|
|
|
|
return t0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_TCG)
|
|
|
|
void tcg_clear_temp_count(TCGContext *s)
|
|
|
|
{
|
|
|
|
s->temps_in_use = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int tcg_check_temp_count(TCGContext *s)
|
|
|
|
{
|
|
|
|
if (s->temps_in_use) {
|
|
|
|
/* Clear the count so that we don't give another
|
|
|
|
* warning immediately next time around.
|
|
|
|
*/
|
|
|
|
s->temps_in_use = 0;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-03-05 04:20:12 +00:00
|
|
|
/* Return true if OP may appear in the opcode stream.
|
|
|
|
Test the runtime variable that controls each opcode. */
|
|
|
|
bool tcg_op_supported(TCGOpcode op)
|
|
|
|
{
|
2018-03-06 16:49:50 +00:00
|
|
|
const bool have_vec
|
|
|
|
= TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256;
|
|
|
|
|
2018-03-05 04:20:12 +00:00
|
|
|
switch (op) {
|
|
|
|
case INDEX_op_discard:
|
|
|
|
case INDEX_op_set_label:
|
|
|
|
case INDEX_op_call:
|
|
|
|
case INDEX_op_br:
|
|
|
|
case INDEX_op_mb:
|
|
|
|
case INDEX_op_insn_start:
|
|
|
|
case INDEX_op_exit_tb:
|
|
|
|
case INDEX_op_goto_tb:
|
|
|
|
case INDEX_op_qemu_ld_i32:
|
|
|
|
case INDEX_op_qemu_st_i32:
|
|
|
|
case INDEX_op_qemu_ld_i64:
|
|
|
|
case INDEX_op_qemu_st_i64:
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case INDEX_op_goto_ptr:
|
|
|
|
return TCG_TARGET_HAS_goto_ptr;
|
|
|
|
|
|
|
|
case INDEX_op_mov_i32:
|
|
|
|
case INDEX_op_movi_i32:
|
|
|
|
case INDEX_op_setcond_i32:
|
|
|
|
case INDEX_op_brcond_i32:
|
|
|
|
case INDEX_op_ld8u_i32:
|
|
|
|
case INDEX_op_ld8s_i32:
|
|
|
|
case INDEX_op_ld16u_i32:
|
|
|
|
case INDEX_op_ld16s_i32:
|
|
|
|
case INDEX_op_ld_i32:
|
|
|
|
case INDEX_op_st8_i32:
|
|
|
|
case INDEX_op_st16_i32:
|
|
|
|
case INDEX_op_st_i32:
|
|
|
|
case INDEX_op_add_i32:
|
|
|
|
case INDEX_op_sub_i32:
|
|
|
|
case INDEX_op_mul_i32:
|
|
|
|
case INDEX_op_and_i32:
|
|
|
|
case INDEX_op_or_i32:
|
|
|
|
case INDEX_op_xor_i32:
|
|
|
|
case INDEX_op_shl_i32:
|
|
|
|
case INDEX_op_shr_i32:
|
|
|
|
case INDEX_op_sar_i32:
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case INDEX_op_movcond_i32:
|
|
|
|
return TCG_TARGET_HAS_movcond_i32;
|
|
|
|
case INDEX_op_div_i32:
|
|
|
|
case INDEX_op_divu_i32:
|
|
|
|
return TCG_TARGET_HAS_div_i32;
|
|
|
|
case INDEX_op_rem_i32:
|
|
|
|
case INDEX_op_remu_i32:
|
|
|
|
return TCG_TARGET_HAS_rem_i32;
|
|
|
|
case INDEX_op_div2_i32:
|
|
|
|
case INDEX_op_divu2_i32:
|
|
|
|
return TCG_TARGET_HAS_div2_i32;
|
|
|
|
case INDEX_op_rotl_i32:
|
|
|
|
case INDEX_op_rotr_i32:
|
|
|
|
return TCG_TARGET_HAS_rot_i32;
|
|
|
|
case INDEX_op_deposit_i32:
|
|
|
|
return TCG_TARGET_HAS_deposit_i32;
|
|
|
|
case INDEX_op_extract_i32:
|
|
|
|
return TCG_TARGET_HAS_extract_i32;
|
|
|
|
case INDEX_op_sextract_i32:
|
|
|
|
return TCG_TARGET_HAS_sextract_i32;
|
|
|
|
case INDEX_op_add2_i32:
|
|
|
|
return TCG_TARGET_HAS_add2_i32;
|
|
|
|
case INDEX_op_sub2_i32:
|
|
|
|
return TCG_TARGET_HAS_sub2_i32;
|
|
|
|
case INDEX_op_mulu2_i32:
|
|
|
|
return TCG_TARGET_HAS_mulu2_i32;
|
|
|
|
case INDEX_op_muls2_i32:
|
|
|
|
return TCG_TARGET_HAS_muls2_i32;
|
|
|
|
case INDEX_op_muluh_i32:
|
|
|
|
return TCG_TARGET_HAS_muluh_i32;
|
|
|
|
case INDEX_op_mulsh_i32:
|
|
|
|
return TCG_TARGET_HAS_mulsh_i32;
|
|
|
|
case INDEX_op_ext8s_i32:
|
|
|
|
return TCG_TARGET_HAS_ext8s_i32;
|
|
|
|
case INDEX_op_ext16s_i32:
|
|
|
|
return TCG_TARGET_HAS_ext16s_i32;
|
|
|
|
case INDEX_op_ext8u_i32:
|
|
|
|
return TCG_TARGET_HAS_ext8u_i32;
|
|
|
|
case INDEX_op_ext16u_i32:
|
|
|
|
return TCG_TARGET_HAS_ext16u_i32;
|
|
|
|
case INDEX_op_bswap16_i32:
|
|
|
|
return TCG_TARGET_HAS_bswap16_i32;
|
|
|
|
case INDEX_op_bswap32_i32:
|
|
|
|
return TCG_TARGET_HAS_bswap32_i32;
|
|
|
|
case INDEX_op_not_i32:
|
|
|
|
return TCG_TARGET_HAS_not_i32;
|
|
|
|
case INDEX_op_neg_i32:
|
|
|
|
return TCG_TARGET_HAS_neg_i32;
|
|
|
|
case INDEX_op_andc_i32:
|
|
|
|
return TCG_TARGET_HAS_andc_i32;
|
|
|
|
case INDEX_op_orc_i32:
|
|
|
|
return TCG_TARGET_HAS_orc_i32;
|
|
|
|
case INDEX_op_eqv_i32:
|
|
|
|
return TCG_TARGET_HAS_eqv_i32;
|
|
|
|
case INDEX_op_nand_i32:
|
|
|
|
return TCG_TARGET_HAS_nand_i32;
|
|
|
|
case INDEX_op_nor_i32:
|
|
|
|
return TCG_TARGET_HAS_nor_i32;
|
|
|
|
case INDEX_op_clz_i32:
|
|
|
|
return TCG_TARGET_HAS_clz_i32;
|
|
|
|
case INDEX_op_ctz_i32:
|
|
|
|
return TCG_TARGET_HAS_ctz_i32;
|
|
|
|
case INDEX_op_ctpop_i32:
|
|
|
|
return TCG_TARGET_HAS_ctpop_i32;
|
|
|
|
|
|
|
|
case INDEX_op_brcond2_i32:
|
|
|
|
case INDEX_op_setcond2_i32:
|
|
|
|
return TCG_TARGET_REG_BITS == 32;
|
|
|
|
|
|
|
|
case INDEX_op_mov_i64:
|
|
|
|
case INDEX_op_movi_i64:
|
|
|
|
case INDEX_op_setcond_i64:
|
|
|
|
case INDEX_op_brcond_i64:
|
|
|
|
case INDEX_op_ld8u_i64:
|
|
|
|
case INDEX_op_ld8s_i64:
|
|
|
|
case INDEX_op_ld16u_i64:
|
|
|
|
case INDEX_op_ld16s_i64:
|
|
|
|
case INDEX_op_ld32u_i64:
|
|
|
|
case INDEX_op_ld32s_i64:
|
|
|
|
case INDEX_op_ld_i64:
|
|
|
|
case INDEX_op_st8_i64:
|
|
|
|
case INDEX_op_st16_i64:
|
|
|
|
case INDEX_op_st32_i64:
|
|
|
|
case INDEX_op_st_i64:
|
|
|
|
case INDEX_op_add_i64:
|
|
|
|
case INDEX_op_sub_i64:
|
|
|
|
case INDEX_op_mul_i64:
|
|
|
|
case INDEX_op_and_i64:
|
|
|
|
case INDEX_op_or_i64:
|
|
|
|
case INDEX_op_xor_i64:
|
|
|
|
case INDEX_op_shl_i64:
|
|
|
|
case INDEX_op_shr_i64:
|
|
|
|
case INDEX_op_sar_i64:
|
|
|
|
case INDEX_op_ext_i32_i64:
|
|
|
|
case INDEX_op_extu_i32_i64:
|
|
|
|
return TCG_TARGET_REG_BITS == 64;
|
|
|
|
|
|
|
|
case INDEX_op_movcond_i64:
|
|
|
|
return TCG_TARGET_HAS_movcond_i64;
|
|
|
|
case INDEX_op_div_i64:
|
|
|
|
case INDEX_op_divu_i64:
|
|
|
|
return TCG_TARGET_HAS_div_i64;
|
|
|
|
case INDEX_op_rem_i64:
|
|
|
|
case INDEX_op_remu_i64:
|
|
|
|
return TCG_TARGET_HAS_rem_i64;
|
|
|
|
case INDEX_op_div2_i64:
|
|
|
|
case INDEX_op_divu2_i64:
|
|
|
|
return TCG_TARGET_HAS_div2_i64;
|
|
|
|
case INDEX_op_rotl_i64:
|
|
|
|
case INDEX_op_rotr_i64:
|
|
|
|
return TCG_TARGET_HAS_rot_i64;
|
|
|
|
case INDEX_op_deposit_i64:
|
|
|
|
return TCG_TARGET_HAS_deposit_i64;
|
|
|
|
case INDEX_op_extract_i64:
|
|
|
|
return TCG_TARGET_HAS_extract_i64;
|
|
|
|
case INDEX_op_sextract_i64:
|
|
|
|
return TCG_TARGET_HAS_sextract_i64;
|
|
|
|
case INDEX_op_extrl_i64_i32:
|
|
|
|
return TCG_TARGET_HAS_extrl_i64_i32;
|
|
|
|
case INDEX_op_extrh_i64_i32:
|
|
|
|
return TCG_TARGET_HAS_extrh_i64_i32;
|
|
|
|
case INDEX_op_ext8s_i64:
|
|
|
|
return TCG_TARGET_HAS_ext8s_i64;
|
|
|
|
case INDEX_op_ext16s_i64:
|
|
|
|
return TCG_TARGET_HAS_ext16s_i64;
|
|
|
|
case INDEX_op_ext32s_i64:
|
|
|
|
return TCG_TARGET_HAS_ext32s_i64;
|
|
|
|
case INDEX_op_ext8u_i64:
|
|
|
|
return TCG_TARGET_HAS_ext8u_i64;
|
|
|
|
case INDEX_op_ext16u_i64:
|
|
|
|
return TCG_TARGET_HAS_ext16u_i64;
|
|
|
|
case INDEX_op_ext32u_i64:
|
|
|
|
return TCG_TARGET_HAS_ext32u_i64;
|
|
|
|
case INDEX_op_bswap16_i64:
|
|
|
|
return TCG_TARGET_HAS_bswap16_i64;
|
|
|
|
case INDEX_op_bswap32_i64:
|
|
|
|
return TCG_TARGET_HAS_bswap32_i64;
|
|
|
|
case INDEX_op_bswap64_i64:
|
|
|
|
return TCG_TARGET_HAS_bswap64_i64;
|
|
|
|
case INDEX_op_not_i64:
|
|
|
|
return TCG_TARGET_HAS_not_i64;
|
|
|
|
case INDEX_op_neg_i64:
|
|
|
|
return TCG_TARGET_HAS_neg_i64;
|
|
|
|
case INDEX_op_andc_i64:
|
|
|
|
return TCG_TARGET_HAS_andc_i64;
|
|
|
|
case INDEX_op_orc_i64:
|
|
|
|
return TCG_TARGET_HAS_orc_i64;
|
|
|
|
case INDEX_op_eqv_i64:
|
|
|
|
return TCG_TARGET_HAS_eqv_i64;
|
|
|
|
case INDEX_op_nand_i64:
|
|
|
|
return TCG_TARGET_HAS_nand_i64;
|
|
|
|
case INDEX_op_nor_i64:
|
|
|
|
return TCG_TARGET_HAS_nor_i64;
|
|
|
|
case INDEX_op_clz_i64:
|
|
|
|
return TCG_TARGET_HAS_clz_i64;
|
|
|
|
case INDEX_op_ctz_i64:
|
|
|
|
return TCG_TARGET_HAS_ctz_i64;
|
|
|
|
case INDEX_op_ctpop_i64:
|
|
|
|
return TCG_TARGET_HAS_ctpop_i64;
|
|
|
|
case INDEX_op_add2_i64:
|
|
|
|
return TCG_TARGET_HAS_add2_i64;
|
|
|
|
case INDEX_op_sub2_i64:
|
|
|
|
return TCG_TARGET_HAS_sub2_i64;
|
|
|
|
case INDEX_op_mulu2_i64:
|
|
|
|
return TCG_TARGET_HAS_mulu2_i64;
|
|
|
|
case INDEX_op_muls2_i64:
|
|
|
|
return TCG_TARGET_HAS_muls2_i64;
|
|
|
|
case INDEX_op_muluh_i64:
|
|
|
|
return TCG_TARGET_HAS_muluh_i64;
|
|
|
|
case INDEX_op_mulsh_i64:
|
|
|
|
return TCG_TARGET_HAS_mulsh_i64;
|
|
|
|
|
2018-03-06 16:49:50 +00:00
|
|
|
case INDEX_op_mov_vec:
|
|
|
|
case INDEX_op_dup_vec:
|
|
|
|
case INDEX_op_dupi_vec:
|
|
|
|
case INDEX_op_ld_vec:
|
|
|
|
case INDEX_op_st_vec:
|
|
|
|
case INDEX_op_add_vec:
|
|
|
|
case INDEX_op_sub_vec:
|
|
|
|
case INDEX_op_and_vec:
|
|
|
|
case INDEX_op_or_vec:
|
|
|
|
case INDEX_op_xor_vec:
|
2018-03-06 19:07:42 +00:00
|
|
|
case INDEX_op_cmp_vec:
|
2018-03-06 16:49:50 +00:00
|
|
|
return have_vec;
|
|
|
|
case INDEX_op_dup2_vec:
|
|
|
|
return have_vec && TCG_TARGET_REG_BITS == 32;
|
|
|
|
case INDEX_op_not_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_not_vec;
|
|
|
|
case INDEX_op_neg_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_neg_vec;
|
|
|
|
case INDEX_op_andc_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_andc_vec;
|
|
|
|
case INDEX_op_orc_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_orc_vec;
|
2018-03-06 19:36:48 +00:00
|
|
|
case INDEX_op_mul_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_mul_vec;
|
2018-03-06 18:45:25 +00:00
|
|
|
case INDEX_op_shli_vec:
|
|
|
|
case INDEX_op_shri_vec:
|
|
|
|
case INDEX_op_sari_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_shi_vec;
|
|
|
|
case INDEX_op_shls_vec:
|
|
|
|
case INDEX_op_shrs_vec:
|
|
|
|
case INDEX_op_sars_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_shs_vec;
|
|
|
|
case INDEX_op_shlv_vec:
|
|
|
|
case INDEX_op_shrv_vec:
|
|
|
|
case INDEX_op_sarv_vec:
|
|
|
|
return have_vec && TCG_TARGET_HAS_shv_vec;
|
2018-03-06 16:49:50 +00:00
|
|
|
|
2018-03-06 17:19:54 +00:00
|
|
|
default:
|
|
|
|
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
|
|
|
|
return true;
|
2018-03-05 04:20:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Note: we convert the 64 bit args to 32 bit and do some alignment
|
|
|
|
and endian swap. Maybe it would be better to do the alignment
|
|
|
|
and endian swap in tcg_reg_alloc_call(). */
|
2018-03-05 13:27:45 +00:00
|
|
|
void tcg_gen_callN(TCGContext *s, void *func, TCGTemp *ret, int nargs, TCGTemp **args)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 09:26:19 +00:00
|
|
|
int i, real_args, nb_rets, pi;
|
2015-08-21 07:04:50 +00:00
|
|
|
unsigned sizemask, flags;
|
|
|
|
TCGHelperInfo *info;
|
2018-03-05 09:26:19 +00:00
|
|
|
TCGOp *op;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
info = g_hash_table_lookup(s->helpers, (gpointer)func);
|
|
|
|
flags = info->flags;
|
|
|
|
sizemask = info->sizemask;
|
|
|
|
|
|
|
|
#if defined(__sparc__) && !defined(__arch64__) \
|
|
|
|
&& !defined(CONFIG_TCG_INTERPRETER)
|
|
|
|
/* We have 64-bit values in one register, but need to pass as two
|
|
|
|
separate parameters. Split them. */
|
|
|
|
int orig_sizemask = sizemask;
|
|
|
|
int orig_nargs = nargs;
|
|
|
|
TCGv_i64 retl, reth;
|
2018-03-05 13:27:45 +00:00
|
|
|
TCGTemp *split_args[MAX_OPC_PARAM];
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 20:51:07 +00:00
|
|
|
retl = NULL;
|
|
|
|
reth = NULL;
|
2015-08-21 07:04:50 +00:00
|
|
|
if (sizemask != 0) {
|
|
|
|
for (i = real_args = 0; i < nargs; ++i) {
|
|
|
|
int is_64bit = sizemask & (1 << (i+1)*2);
|
|
|
|
if (is_64bit) {
|
2018-03-05 13:53:51 +00:00
|
|
|
TCGv_i64 orig = temp_tcgv_i64(s, args[i]);
|
2017-02-26 01:47:40 +00:00
|
|
|
TCGv_i32 h = tcg_temp_new_i32(s);
|
|
|
|
TCGv_i32 l = tcg_temp_new_i32(s);
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_gen_extr_i64_i32(l, h, orig);
|
2018-03-05 13:27:45 +00:00
|
|
|
split_args[real_args++] = tcgv_i32_temp(s, h);
|
|
|
|
split_args[real_args++] = tcgv_i32_temp(s, l);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
split_args[real_args++] = args[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
nargs = real_args;
|
|
|
|
args = split_args;
|
|
|
|
sizemask = 0;
|
|
|
|
}
|
|
|
|
#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
|
|
|
|
for (i = 0; i < nargs; ++i) {
|
|
|
|
int is_64bit = sizemask & (1 << (i+1)*2);
|
|
|
|
int is_signed = sizemask & (2 << (i+1)*2);
|
|
|
|
if (!is_64bit) {
|
|
|
|
TCGv_i64 temp = tcg_temp_new_i64(s);
|
2018-03-05 13:53:51 +00:00
|
|
|
TCGv_i64 orig = temp_tcgv_i64(s, args[i]);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (is_signed) {
|
2017-02-26 01:47:40 +00:00
|
|
|
tcg_gen_ext32s_i64(s, temp, orig);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
2017-02-26 01:47:40 +00:00
|
|
|
tcg_gen_ext32u_i64(s, temp, orig);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 13:27:45 +00:00
|
|
|
args[i] = tcgv_i64_temp(s, temp);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* TCG_TARGET_EXTEND_ARGS */
|
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
op = tcg_emit_op(s, INDEX_op_call);
|
2018-03-05 09:26:19 +00:00
|
|
|
|
|
|
|
pi = 0;
|
2018-03-05 13:27:45 +00:00
|
|
|
if (ret != NULL) {
|
2015-08-21 07:04:50 +00:00
|
|
|
#if defined(__sparc__) && !defined(__arch64__) \
|
|
|
|
&& !defined(CONFIG_TCG_INTERPRETER)
|
|
|
|
if (orig_sizemask & 1) {
|
|
|
|
/* The 32-bit ABI is going to return the 64-bit value in
|
|
|
|
the %o0/%o1 register pair. Prepare for this by using
|
|
|
|
two return temporaries, and reassemble below. */
|
|
|
|
retl = tcg_temp_new_i64(s);
|
|
|
|
reth = tcg_temp_new_i64(s);
|
2018-03-05 13:27:45 +00:00
|
|
|
op->args[pi++] = tcgv_i64_arg(reth);
|
|
|
|
op->args[pi++] = tcgv_i64_arg(retl);
|
2015-08-21 07:04:50 +00:00
|
|
|
nb_rets = 2;
|
|
|
|
} else {
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(ret);
|
2015-08-21 07:04:50 +00:00
|
|
|
nb_rets = 1;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
|
|
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(ret + 1);
|
|
|
|
op->args[pi++] = temp_arg(ret);
|
2015-08-21 07:04:50 +00:00
|
|
|
#else
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(ret);
|
|
|
|
op->args[pi++] = temp_arg(ret + 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
#endif
|
|
|
|
nb_rets = 2;
|
|
|
|
} else {
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(ret);
|
2015-08-21 07:04:50 +00:00
|
|
|
nb_rets = 1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
nb_rets = 0;
|
|
|
|
}
|
2018-03-05 21:51:53 +00:00
|
|
|
TCGOP_CALLO(op) = nb_rets;
|
2018-03-05 09:26:19 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
real_args = 0;
|
|
|
|
for (i = 0; i < nargs; i++) {
|
|
|
|
int is_64bit = sizemask & (1 << (i+1)*2);
|
|
|
|
if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
|
|
|
|
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
|
|
|
|
/* some targets want aligned 64 bit args */
|
|
|
|
if (real_args & 1) {
|
2018-03-05 09:26:19 +00:00
|
|
|
op->args[pi++] = TCG_CALL_DUMMY_ARG;
|
2015-08-21 07:04:50 +00:00
|
|
|
real_args++;
|
|
|
|
}
|
|
|
|
#endif
|
2018-02-26 03:00:09 +00:00
|
|
|
/* If stack grows up, then we will be placing successive
|
|
|
|
arguments at lower addresses, which means we need to
|
|
|
|
reverse the order compared to how we would normally
|
|
|
|
treat either big or little-endian. For those arguments
|
|
|
|
that will wind up in registers, this still works for
|
|
|
|
HPPA (the only current STACK_GROWSUP target) since the
|
|
|
|
argument registers are *also* allocated in decreasing
|
|
|
|
order. If another such target is added, this logic may
|
|
|
|
have to get more complicated to differentiate between
|
|
|
|
stack arguments and register arguments. */
|
2015-08-21 07:04:50 +00:00
|
|
|
#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(args[i] + 1);
|
|
|
|
op->args[pi++] = temp_arg(args[i]);
|
2015-08-21 07:04:50 +00:00
|
|
|
#else
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(args[i]);
|
|
|
|
op->args[pi++] = temp_arg(args[i] + 1);
|
2015-08-21 07:04:50 +00:00
|
|
|
#endif
|
|
|
|
real_args += 2;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[pi++] = temp_arg(args[i]);
|
2015-08-21 07:04:50 +00:00
|
|
|
real_args++;
|
|
|
|
}
|
2018-03-05 09:26:19 +00:00
|
|
|
op->args[pi++] = (uintptr_t)func;
|
|
|
|
op->args[pi++] = flags;
|
2018-03-05 21:51:53 +00:00
|
|
|
TCGOP_CALLI(op) = real_args;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 09:26:19 +00:00
|
|
|
/* Make sure the fields didn't overflow. */
|
2018-03-05 21:51:53 +00:00
|
|
|
tcg_debug_assert(TCGOP_CALLI(op) == real_args);
|
2018-03-05 09:26:19 +00:00
|
|
|
tcg_debug_assert(pi <= ARRAY_SIZE(op->args));
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
#if defined(__sparc__) && !defined(__arch64__) \
|
|
|
|
&& !defined(CONFIG_TCG_INTERPRETER)
|
|
|
|
/* Free all of the parts we allocated above. */
|
|
|
|
for (i = real_args = 0; i < orig_nargs; ++i) {
|
|
|
|
int is_64bit = orig_sizemask & (1 << (i+1)*2);
|
|
|
|
if (is_64bit) {
|
2018-03-05 13:53:51 +00:00
|
|
|
tcg_temp_free_internal(s, args[real_args++]);
|
|
|
|
tcg_temp_free_internal(s, args[real_args++]);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
real_args++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (orig_sizemask & 1) {
|
|
|
|
/* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
|
|
|
|
Note that describing these as TCGv_i64 eliminates an unnecessary
|
|
|
|
zero-extension that tcg_gen_concat_i32_i64 would create. */
|
2018-03-05 13:53:51 +00:00
|
|
|
tcg_gen_concat32_i64(s, temp_tcgv_i64(s, ret), retl, reth);
|
2017-02-26 01:47:40 +00:00
|
|
|
tcg_temp_free_i64(s, retl);
|
|
|
|
tcg_temp_free_i64(s, reth);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
|
|
|
|
for (i = 0; i < nargs; ++i) {
|
|
|
|
int is_64bit = sizemask & (1 << (i+1)*2);
|
|
|
|
if (!is_64bit) {
|
2018-03-05 13:53:51 +00:00
|
|
|
tcg_temp_free_internal(s, args[i]);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* TCG_TARGET_EXTEND_ARGS */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tcg_reg_alloc_start(TCGContext *s)
|
|
|
|
{
|
2018-03-05 12:49:59 +00:00
|
|
|
int i, n;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGTemp *ts;
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2018-03-05 12:49:59 +00:00
|
|
|
for (i = 0, n = s->nb_globals; i < n; i++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
ts = &s->temps[i];
|
2018-03-05 12:49:59 +00:00
|
|
|
ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:49:59 +00:00
|
|
|
for (n = s->nb_temps; i < n; i++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
ts = &s->temps[i];
|
2018-03-05 12:49:59 +00:00
|
|
|
ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD);
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->mem_allocated = 0;
|
|
|
|
ts->fixed_reg = 0;
|
|
|
|
}
|
2018-02-19 16:30:24 +00:00
|
|
|
|
|
|
|
memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-19 16:30:24 +00:00
|
|
|
static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
|
|
|
|
TCGTemp *ts)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-02-19 16:30:24 +00:00
|
|
|
int idx = temp_idx(s, ts);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 12:21:07 +00:00
|
|
|
if (ts->temp_global) {
|
2015-08-21 07:04:50 +00:00
|
|
|
pstrcpy(buf, buf_size, ts->name);
|
2018-02-19 16:30:24 +00:00
|
|
|
} else if (ts->temp_local) {
|
|
|
|
snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
2018-02-19 16:30:24 +00:00
|
|
|
snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
return buf;
|
|
|
|
}
|
|
|
|
|
2018-03-05 12:16:49 +00:00
|
|
|
static char *tcg_get_arg_str(TCGContext *s, char *buf,
|
|
|
|
int buf_size, TCGArg arg)
|
2018-02-19 16:30:24 +00:00
|
|
|
{
|
2018-03-05 14:55:39 +00:00
|
|
|
return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg));
|
2018-02-19 16:30:24 +00:00
|
|
|
}
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Find helper name. */
|
|
|
|
static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
|
|
|
|
{
|
|
|
|
const char *ret = NULL;
|
|
|
|
if (s->helpers) {
|
|
|
|
TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val);
|
|
|
|
if (info) {
|
|
|
|
ret = info->name;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char * const cond_name[] =
|
|
|
|
{
|
2017-01-19 11:50:28 +00:00
|
|
|
#ifdef _MSC_VER
|
2017-01-21 01:28:22 +00:00
|
|
|
"never", // TCG_COND_NEVER
|
|
|
|
"always", // TCG_COND_ALWAYS
|
|
|
|
"lt", // TCG_COND_LT
|
|
|
|
"ge", // TCG_COND_GE
|
|
|
|
"ltu", // TCG_COND_LTU
|
|
|
|
"geu", // TCG_COND_GEU
|
|
|
|
NULL, // n/a
|
|
|
|
NULL, // n/a
|
|
|
|
"eq", // TCG_COND_EQ
|
|
|
|
"ne", // TCG_COND_NE
|
|
|
|
"le", // TCG_COND_LE
|
|
|
|
"gt", // TCG_COND_GT
|
|
|
|
"leu", // TCG_COND_LEU
|
|
|
|
"gtu", // TCG_COND_GTU
|
|
|
|
NULL, // n/a
|
|
|
|
NULL, // n/a
|
2017-01-19 11:50:28 +00:00
|
|
|
#else
|
2015-08-21 07:04:50 +00:00
|
|
|
[TCG_COND_NEVER] = "never",
|
|
|
|
[TCG_COND_ALWAYS] = "always",
|
|
|
|
[TCG_COND_EQ] = "eq",
|
|
|
|
[TCG_COND_NE] = "ne",
|
|
|
|
[TCG_COND_LT] = "lt",
|
|
|
|
[TCG_COND_GE] = "ge",
|
|
|
|
[TCG_COND_LE] = "le",
|
|
|
|
[TCG_COND_GT] = "gt",
|
|
|
|
[TCG_COND_LTU] = "ltu",
|
|
|
|
[TCG_COND_GEU] = "geu",
|
|
|
|
[TCG_COND_LEU] = "leu",
|
|
|
|
[TCG_COND_GTU] = "gtu"
|
2017-01-19 11:50:28 +00:00
|
|
|
#endif
|
2015-08-21 07:04:50 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const char * const ldst_name[] =
|
|
|
|
{
|
2017-01-19 11:50:28 +00:00
|
|
|
#ifdef _MSC_VER
|
2017-01-21 01:28:22 +00:00
|
|
|
"ub", // MO_UB
|
2017-01-19 11:50:28 +00:00
|
|
|
# ifdef HOST_WORDS_BIGENDIAN
|
2017-01-21 01:28:22 +00:00
|
|
|
"beuw", // MO_BEUW
|
|
|
|
"beul", // MO_BEUL
|
|
|
|
"beq", // MO_BEQ
|
|
|
|
"sb", // MO_SB
|
|
|
|
"besw", // MO_BESW
|
|
|
|
"besl", // MO_BESL
|
|
|
|
NULL, // n/a
|
|
|
|
NULL, // n/a
|
|
|
|
"leuw", // MO_LEUW
|
|
|
|
"leul", // MO_LEUL
|
|
|
|
"leq", // MO_LEQ
|
|
|
|
NULL, // n/a
|
|
|
|
"lesw", // MO_LESW
|
|
|
|
"lesl", // MO_LESL
|
|
|
|
NULL, // n/a
|
2017-01-19 11:50:28 +00:00
|
|
|
# else // !HOST_WORDS_BIGENDIAN
|
2017-01-21 01:28:22 +00:00
|
|
|
"leuw", // MO_LEUW
|
|
|
|
"leul", // MO_LEUL
|
|
|
|
"leq", // MO_LEQ
|
|
|
|
"sb", // MO_SB
|
|
|
|
"lesw", // MO_LESW
|
|
|
|
"lesl", // MO_LESL
|
|
|
|
NULL, // n/a
|
|
|
|
NULL, // n/a
|
|
|
|
"beuw", // MO_BEUW
|
|
|
|
"beul", // MO_BEUL
|
|
|
|
"beq", // MO_BEQ
|
|
|
|
NULL, // n/a
|
|
|
|
"besw", // MO_BESW
|
|
|
|
"besl", // MO_BESL
|
|
|
|
NULL, // n/a
|
2017-01-19 11:50:28 +00:00
|
|
|
# endif // HOST_WORDS_BIGENDIAN
|
|
|
|
|
|
|
|
#else //_MSC_VER
|
2017-01-21 01:28:22 +00:00
|
|
|
[MO_UB] = "ub",
|
2015-08-21 07:04:50 +00:00
|
|
|
[MO_SB] = "sb",
|
|
|
|
[MO_LEUW] = "leuw",
|
|
|
|
[MO_LESW] = "lesw",
|
|
|
|
[MO_LEUL] = "leul",
|
|
|
|
[MO_LESL] = "lesl",
|
|
|
|
[MO_LEQ] = "leq",
|
|
|
|
[MO_BEUW] = "beuw",
|
|
|
|
[MO_BESW] = "besw",
|
|
|
|
[MO_BEUL] = "beul",
|
|
|
|
[MO_BESL] = "besl",
|
|
|
|
[MO_BEQ] = "beq",
|
2017-01-19 11:50:28 +00:00
|
|
|
#endif // _MSC_VER
|
2015-08-21 07:04:50 +00:00
|
|
|
};
|
|
|
|
|
2018-02-25 06:51:06 +00:00
|
|
|
static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = {
|
|
|
|
"",
|
|
|
|
"al2+",
|
|
|
|
"al4+",
|
|
|
|
"al8+",
|
|
|
|
"al16+",
|
|
|
|
"al32+",
|
|
|
|
"al64+",
|
|
|
|
#ifdef ALIGNED_ONLY
|
|
|
|
"un+"
|
|
|
|
#else
|
|
|
|
"al+",
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
void tcg_dump_ops(TCGContext *s)
|
|
|
|
{
|
|
|
|
char buf[128];
|
2018-02-09 14:54:01 +00:00
|
|
|
TCGOp *op;
|
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_FOREACH(op, &s->ops, link) {
|
2018-02-09 14:54:01 +00:00
|
|
|
int i, k, nb_oargs, nb_iargs, nb_cargs;
|
|
|
|
const TCGOpDef *def;
|
|
|
|
TCGOpcode c;
|
2018-02-26 03:12:59 +00:00
|
|
|
int col = 0;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-09 14:54:01 +00:00
|
|
|
c = op->opc;
|
2015-08-21 07:04:50 +00:00
|
|
|
def = &s->tcg_op_defs[c];
|
2018-02-09 14:54:01 +00:00
|
|
|
|
2018-02-11 17:31:22 +00:00
|
|
|
if (c == INDEX_op_insn_start) {
|
2018-03-05 21:01:13 +00:00
|
|
|
col += qemu_log("\n ----");
|
2018-02-11 18:03:29 +00:00
|
|
|
|
|
|
|
for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
|
|
|
|
target_ulong a;
|
2015-08-21 07:04:50 +00:00
|
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
2018-03-05 12:06:09 +00:00
|
|
|
a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]);
|
2015-08-21 07:04:50 +00:00
|
|
|
#else
|
2018-03-05 12:06:09 +00:00
|
|
|
a = op->args[i];
|
2015-08-21 07:04:50 +00:00
|
|
|
#endif
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(" " TARGET_FMT_lx, a);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
} else if (c == INDEX_op_call) {
|
|
|
|
/* variable number of arguments */
|
2018-03-05 21:51:53 +00:00
|
|
|
nb_oargs = TCGOP_CALLO(op);
|
|
|
|
nb_iargs = TCGOP_CALLI(op);
|
2015-08-21 07:04:50 +00:00
|
|
|
nb_cargs = def->nb_cargs;
|
|
|
|
|
|
|
|
/* function name, flags, out args */
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
|
2018-03-05 12:06:09 +00:00
|
|
|
tcg_find_helper(s, op->args[nb_oargs + nb_iargs]),
|
|
|
|
op->args[nb_oargs + nb_iargs + 1], nb_oargs);
|
2015-08-21 07:04:50 +00:00
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2018-03-05 12:16:49 +00:00
|
|
|
col += qemu_log(",%s", tcg_get_arg_str(s, buf, sizeof(buf),
|
|
|
|
op->args[i]));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
for (i = 0; i < nb_iargs; i++) {
|
2018-03-05 12:06:09 +00:00
|
|
|
TCGArg arg = op->args[nb_oargs + i];
|
2015-08-21 07:04:50 +00:00
|
|
|
const char *t = "<dummy>";
|
|
|
|
if (arg != TCG_CALL_DUMMY_ARG) {
|
2018-03-05 12:16:49 +00:00
|
|
|
t = tcg_get_arg_str(s, buf, sizeof(buf), arg);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(",%s", t);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
} else {
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(" %s ", def->name);
|
2018-02-09 14:54:01 +00:00
|
|
|
|
|
|
|
nb_oargs = def->nb_oargs;
|
|
|
|
nb_iargs = def->nb_iargs;
|
|
|
|
nb_cargs = def->nb_cargs;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-12 22:03:02 +00:00
|
|
|
if (def->flags & TCG_OPF_VECTOR) {
|
|
|
|
col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op),
|
|
|
|
8 << TCGOP_VECE(op));
|
|
|
|
}
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
k = 0;
|
2018-02-09 14:54:01 +00:00
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
if (k != 0) {
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(",");
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:16:49 +00:00
|
|
|
col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf),
|
|
|
|
op->args[k++]));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-09 14:54:01 +00:00
|
|
|
for (i = 0; i < nb_iargs; i++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
if (k != 0) {
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(",");
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:16:49 +00:00
|
|
|
col += qemu_log("%s", tcg_get_arg_str(s, buf, sizeof(buf),
|
|
|
|
op->args[k++]));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
switch (c) {
|
|
|
|
case INDEX_op_brcond_i32:
|
|
|
|
case INDEX_op_setcond_i32:
|
|
|
|
case INDEX_op_movcond_i32:
|
|
|
|
case INDEX_op_brcond2_i32:
|
|
|
|
case INDEX_op_setcond2_i32:
|
|
|
|
case INDEX_op_brcond_i64:
|
|
|
|
case INDEX_op_setcond_i64:
|
|
|
|
case INDEX_op_movcond_i64:
|
2018-03-06 19:07:42 +00:00
|
|
|
case INDEX_op_cmp_vec:
|
2018-03-05 12:06:09 +00:00
|
|
|
if (op->args[k] < ARRAY_SIZE(cond_name)
|
|
|
|
&& cond_name[op->args[k]]) {
|
|
|
|
col += qemu_log(",%s", cond_name[op->args[k++]]);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
2018-03-05 12:06:09 +00:00
|
|
|
col += qemu_log(",$0x%" TCG_PRIlx, op->args[k++]);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
i = 1;
|
|
|
|
break;
|
|
|
|
case INDEX_op_qemu_ld_i32:
|
|
|
|
case INDEX_op_qemu_st_i32:
|
|
|
|
case INDEX_op_qemu_ld_i64:
|
|
|
|
case INDEX_op_qemu_st_i64:
|
2018-02-11 00:01:17 +00:00
|
|
|
{
|
2018-03-05 12:06:09 +00:00
|
|
|
TCGMemOpIdx oi = op->args[k++];
|
2018-02-11 00:01:17 +00:00
|
|
|
TCGMemOp op = get_memop(oi);
|
|
|
|
unsigned ix = get_mmuidx(oi);
|
|
|
|
|
2018-02-11 01:32:48 +00:00
|
|
|
if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(",$0x%x,%u", op, ix);
|
2018-02-11 00:01:17 +00:00
|
|
|
} else {
|
2018-02-25 06:51:06 +00:00
|
|
|
const char *s_al, *s_op;
|
|
|
|
s_al = alignment_name[(op & MO_AMASK) >> MO_ASHIFT];
|
2018-02-11 01:32:48 +00:00
|
|
|
s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)];
|
2018-02-26 03:12:59 +00:00
|
|
|
col += qemu_log(",%s%s,%u", s_al, s_op, ix);
|
2018-02-11 00:01:17 +00:00
|
|
|
}
|
|
|
|
i = 1;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
2018-02-09 19:47:48 +00:00
|
|
|
switch (c) {
|
|
|
|
case INDEX_op_set_label:
|
|
|
|
case INDEX_op_br:
|
|
|
|
case INDEX_op_brcond_i32:
|
|
|
|
case INDEX_op_brcond_i64:
|
|
|
|
case INDEX_op_brcond2_i32:
|
2018-03-05 12:06:09 +00:00
|
|
|
col += qemu_log("%s$L%d", k ? "," : "",
|
|
|
|
arg_label(s, op->args[k])->id);
|
2018-02-09 19:47:48 +00:00
|
|
|
i++, k++;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
for (; i < nb_cargs; i++, k++) {
|
2018-03-05 12:06:09 +00:00
|
|
|
col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]);
|
2018-02-26 03:12:59 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (op->life) {
|
|
|
|
unsigned life = op->life;
|
|
|
|
|
|
|
|
for (; col < 48; ++col) {
|
|
|
|
putc(' ', qemu_logfile);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (life & (SYNC_ARG * 3)) {
|
|
|
|
qemu_log(" sync:");
|
|
|
|
for (i = 0; i < 2; ++i) {
|
|
|
|
if (life & (SYNC_ARG << i)) {
|
|
|
|
qemu_log(" %d", i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
life /= DEAD_ARG;
|
|
|
|
if (life) {
|
|
|
|
qemu_log(" dead:");
|
|
|
|
for (i = 0; life; ++i, life >>= 1) {
|
|
|
|
if (life & 1) {
|
|
|
|
qemu_log(" %d", i);
|
|
|
|
}
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
2018-02-26 02:36:41 +00:00
|
|
|
qemu_log("\n");
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we give more priority to constraints with less registers */
|
|
|
|
static int get_constraint_priority(const TCGOpDef *def, int k)
|
|
|
|
{
|
|
|
|
const TCGArgConstraint *arg_ct;
|
|
|
|
|
|
|
|
int i, n;
|
|
|
|
arg_ct = &def->args_ct[k];
|
|
|
|
if (arg_ct->ct & TCG_CT_ALIAS) {
|
|
|
|
/* an alias is equivalent to a single register */
|
|
|
|
n = 1;
|
|
|
|
} else {
|
|
|
|
if (!(arg_ct->ct & TCG_CT_REG))
|
|
|
|
return 0;
|
|
|
|
n = 0;
|
|
|
|
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
|
|
|
|
if (tcg_regset_test_reg(arg_ct->u.regs, i))
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return TCG_TARGET_NB_REGS - n + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* sort from highest priority to lowest */
|
|
|
|
static void sort_constraints(TCGOpDef *def, int start, int n)
|
|
|
|
{
|
|
|
|
int i, j, p1, p2, tmp;
|
|
|
|
|
|
|
|
for(i = 0; i < n; i++)
|
|
|
|
def->sorted_args[start + i] = start + i;
|
|
|
|
if (n <= 1)
|
|
|
|
return;
|
|
|
|
for(i = 0; i < n - 1; i++) {
|
|
|
|
for(j = i + 1; j < n; j++) {
|
|
|
|
p1 = get_constraint_priority(def, def->sorted_args[start + i]);
|
|
|
|
p2 = get_constraint_priority(def, def->sorted_args[start + j]);
|
|
|
|
if (p1 < p2) {
|
|
|
|
tmp = def->sorted_args[start + i];
|
|
|
|
def->sorted_args[start + i] = def->sorted_args[start + j];
|
|
|
|
def->sorted_args[start + j] = tmp;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-01 20:36:50 +00:00
|
|
|
static void process_op_defs(TCGContext *s)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
|
|
|
TCGOpcode op;
|
|
|
|
|
2018-03-01 20:36:50 +00:00
|
|
|
for (op = 0; op < NB_OPS; op++) {
|
|
|
|
TCGOpDef *def = &s->tcg_op_defs[op];
|
|
|
|
const TCGTargetOpDef *tdefs;
|
2018-03-01 20:45:36 +00:00
|
|
|
TCGType type;
|
|
|
|
int i, nb_args;
|
2018-03-01 20:36:50 +00:00
|
|
|
|
|
|
|
if (def->flags & TCG_OPF_NOT_PRESENT) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
nb_args = def->nb_iargs + def->nb_oargs;
|
2018-03-01 20:36:50 +00:00
|
|
|
if (nb_args == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
tdefs = tcg_target_op_def(op);
|
|
|
|
/* Missing TCGTargetOpDef entry. */
|
|
|
|
tcg_debug_assert(tdefs != NULL);
|
|
|
|
|
2018-03-01 20:45:36 +00:00
|
|
|
type = (def->flags & TCG_OPF_64BIT ? TCG_TYPE_I64 : TCG_TYPE_I32);
|
2018-03-01 20:36:50 +00:00
|
|
|
for (i = 0; i < nb_args; i++) {
|
|
|
|
const char *ct_str = tdefs->args_ct_str[i];
|
|
|
|
/* Incomplete TCGTargetOpDef entry. */
|
2018-02-23 18:52:01 +00:00
|
|
|
tcg_debug_assert(ct_str != NULL);
|
2018-03-01 20:36:50 +00:00
|
|
|
|
2018-03-05 04:23:28 +00:00
|
|
|
def->args_ct[i].u.regs = 0;
|
2015-08-21 07:04:50 +00:00
|
|
|
def->args_ct[i].ct = 0;
|
2018-03-01 20:49:03 +00:00
|
|
|
while (*ct_str != '\0') {
|
|
|
|
switch(*ct_str) {
|
|
|
|
case '0':
|
|
|
|
case '1':
|
|
|
|
case '2':
|
|
|
|
case '3':
|
|
|
|
case '4':
|
|
|
|
case '5':
|
|
|
|
case '6':
|
|
|
|
case '7':
|
|
|
|
case '8':
|
|
|
|
case '9':
|
|
|
|
{
|
|
|
|
int oarg = *ct_str - '0';
|
|
|
|
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
|
|
|
|
tcg_debug_assert(oarg < def->nb_oargs);
|
|
|
|
tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
|
|
|
|
/* TCG_CT_ALIAS is for the output arguments.
|
|
|
|
The input is tagged with TCG_CT_IALIAS. */
|
|
|
|
def->args_ct[i] = def->args_ct[oarg];
|
|
|
|
def->args_ct[oarg].ct |= TCG_CT_ALIAS;
|
|
|
|
def->args_ct[oarg].alias_index = i;
|
|
|
|
def->args_ct[i].ct |= TCG_CT_IALIAS;
|
|
|
|
def->args_ct[i].alias_index = oarg;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-01 20:49:03 +00:00
|
|
|
ct_str++;
|
|
|
|
break;
|
|
|
|
case '&':
|
|
|
|
def->args_ct[i].ct |= TCG_CT_NEWREG;
|
|
|
|
ct_str++;
|
|
|
|
break;
|
|
|
|
case 'i':
|
|
|
|
def->args_ct[i].ct |= TCG_CT_CONST;
|
|
|
|
ct_str++;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ct_str = target_parse_constraint(&def->args_ct[i],
|
|
|
|
ct_str, type);
|
|
|
|
/* Typo in TCGTargetOpDef constraint. */
|
|
|
|
tcg_debug_assert(ct_str != NULL);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TCGTargetOpDef entry with too much information? */
|
2018-02-23 18:52:01 +00:00
|
|
|
tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
/* sort the constraints (XXX: this is just an heuristic) */
|
|
|
|
sort_constraints(def, 0, def->nb_oargs);
|
|
|
|
sort_constraints(def, def->nb_oargs, def->nb_iargs);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-09 18:03:25 +00:00
|
|
|
void tcg_op_remove(TCGContext *s, TCGOp *op)
|
|
|
|
{
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_REMOVE(&s->ops, op, link);
|
|
|
|
QTAILQ_INSERT_TAIL(&s->free_ops, op, link);
|
2018-05-11 15:24:59 +00:00
|
|
|
s->nb_ops--;
|
2018-02-09 18:03:25 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
2018-03-12 22:03:02 +00:00
|
|
|
atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1);
|
2018-02-09 18:03:25 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
static TCGOp *tcg_op_alloc(TCGContext *s, TCGOpcode opc)
|
2018-02-26 03:23:00 +00:00
|
|
|
{
|
2018-03-05 21:01:13 +00:00
|
|
|
TCGOp *op;
|
2018-02-26 03:23:00 +00:00
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
if (likely(QTAILQ_EMPTY(&s->free_ops))) {
|
|
|
|
op = tcg_malloc(s, sizeof(TCGOp));
|
|
|
|
} else {
|
|
|
|
op = QTAILQ_FIRST(&s->free_ops);
|
|
|
|
QTAILQ_REMOVE(&s->free_ops, op, link);
|
|
|
|
}
|
|
|
|
memset(op, 0, offsetof(TCGOp, link));
|
|
|
|
op->opc = opc;
|
2018-05-11 15:24:59 +00:00
|
|
|
s->nb_ops++;
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
return op;
|
|
|
|
}
|
2018-02-26 03:23:00 +00:00
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
TCGOp *tcg_emit_op(TCGContext *s, TCGOpcode opc)
|
|
|
|
{
|
|
|
|
TCGOp *op = tcg_op_alloc(s, opc);
|
|
|
|
QTAILQ_INSERT_TAIL(&s->ops, op, link);
|
|
|
|
return op;
|
|
|
|
}
|
2018-02-26 03:23:00 +00:00
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op,
|
|
|
|
TCGOpcode opc, int nargs)
|
|
|
|
{
|
|
|
|
TCGOp *new_op = tcg_op_alloc(s, opc);
|
|
|
|
QTAILQ_INSERT_BEFORE(old_op, new_op, link);
|
2018-02-26 03:23:00 +00:00
|
|
|
return new_op;
|
|
|
|
}
|
|
|
|
|
|
|
|
TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
|
|
|
|
TCGOpcode opc, int nargs)
|
|
|
|
{
|
2018-03-05 21:01:13 +00:00
|
|
|
TCGOp *new_op = tcg_op_alloc(s, opc);
|
|
|
|
QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link);
|
2018-02-26 03:23:00 +00:00
|
|
|
return new_op;
|
|
|
|
}
|
|
|
|
|
2018-02-26 03:00:09 +00:00
|
|
|
#define TS_DEAD 1
|
|
|
|
#define TS_MEM 2
|
|
|
|
|
2018-02-26 03:23:00 +00:00
|
|
|
#define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
|
|
|
|
#define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* liveness analysis: end of function: all temps are dead, and globals
|
|
|
|
should be in memory. */
|
2018-03-05 12:29:27 +00:00
|
|
|
static inline void tcg_la_func_end(TCGContext *s)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 12:29:27 +00:00
|
|
|
int ng = s->nb_globals;
|
|
|
|
int nt = s->nb_temps;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ng; ++i) {
|
|
|
|
s->temps[i].state = TS_DEAD | TS_MEM;
|
|
|
|
}
|
|
|
|
for (i = ng; i < nt; ++i) {
|
|
|
|
s->temps[i].state = TS_DEAD;
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* liveness analysis: end of basic block: all temps are dead, globals
|
|
|
|
and local temps should be in memory. */
|
2018-03-05 12:29:27 +00:00
|
|
|
static void tcg_la_bb_end(TCGContext *s)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 12:29:27 +00:00
|
|
|
int ng = s->nb_globals;
|
|
|
|
int nt = s->nb_temps;
|
|
|
|
int i;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 12:29:27 +00:00
|
|
|
for (i = 0; i < ng; ++i) {
|
|
|
|
s->temps[i].state = TS_DEAD | TS_MEM;
|
|
|
|
}
|
|
|
|
for (i = ng; i < nt; ++i) {
|
|
|
|
s->temps[i].state = (s->temps[i].temp_local
|
|
|
|
? TS_DEAD | TS_MEM
|
|
|
|
: TS_DEAD);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-21 10:01:01 +00:00
|
|
|
/*
|
|
|
|
Unicorn: for brcond, we should refresh liveness states for TCG globals
|
|
|
|
*/
|
2018-03-05 12:29:27 +00:00
|
|
|
static inline void tcg_la_br_end(TCGContext *s)
|
2015-12-21 10:01:01 +00:00
|
|
|
{
|
2018-03-05 12:29:27 +00:00
|
|
|
int ng = s->nb_globals;
|
|
|
|
int nt = s->nb_temps;
|
2015-12-21 10:01:01 +00:00
|
|
|
int i;
|
2018-03-05 12:29:27 +00:00
|
|
|
|
|
|
|
for (i = 0; i < ng; i++) {
|
|
|
|
s->temps[i].state = TS_MEM;
|
2018-02-26 03:00:09 +00:00
|
|
|
}
|
2018-03-05 12:29:27 +00:00
|
|
|
for(i = ng; i < nt; i++) {
|
|
|
|
s->temps[i].state = s->temps[i].temp_local;
|
2015-12-21 10:01:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-26 02:27:00 +00:00
|
|
|
/* Liveness analysis : update the opc_arg_life array to tell if a
|
2015-08-21 07:04:50 +00:00
|
|
|
given input arguments is dead. Instructions updating dead
|
|
|
|
temporaries are removed. */
|
2018-03-05 12:29:27 +00:00
|
|
|
static void liveness_pass_1(TCGContext *s)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-02-26 03:00:09 +00:00
|
|
|
int nb_globals = s->nb_globals;
|
2018-03-05 21:01:13 +00:00
|
|
|
TCGOp *op, *op_prev;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 12:29:27 +00:00
|
|
|
tcg_la_func_end(s);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, TCGOpHead, link, op_prev) {
|
2018-02-09 14:54:01 +00:00
|
|
|
int i, nb_iargs, nb_oargs;
|
|
|
|
TCGOpcode opc_new, opc_new2;
|
|
|
|
bool have_opc_new2;
|
2018-02-26 02:27:00 +00:00
|
|
|
TCGLifeData arg_life = 0;
|
2018-03-05 12:29:27 +00:00
|
|
|
TCGTemp *arg_ts;
|
2018-02-09 14:54:01 +00:00
|
|
|
TCGOpcode opc = op->opc;
|
|
|
|
const TCGOpDef *def = &s->tcg_op_defs[opc];
|
|
|
|
|
2018-03-12 22:03:02 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_call:
|
|
|
|
{
|
|
|
|
int call_flags;
|
|
|
|
|
2018-03-05 21:51:53 +00:00
|
|
|
nb_oargs = TCGOP_CALLO(op);
|
|
|
|
nb_iargs = TCGOP_CALLI(op);
|
2018-03-05 12:06:09 +00:00
|
|
|
call_flags = op->args[nb_oargs + nb_iargs + 1];
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-09 14:54:01 +00:00
|
|
|
/* pure functions can be removed if their result is unused */
|
2015-08-21 07:04:50 +00:00
|
|
|
if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
|
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts->state != TS_DEAD) {
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_not_remove_call;
|
|
|
|
}
|
|
|
|
}
|
2018-02-09 14:54:01 +00:00
|
|
|
goto do_remove;
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
do_not_remove_call:
|
|
|
|
|
|
|
|
/* output args are dead */
|
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts->state & TS_DEAD) {
|
2018-02-26 02:27:00 +00:00
|
|
|
arg_life |= DEAD_ARG << i;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts->state & TS_MEM) {
|
2018-02-26 02:27:00 +00:00
|
|
|
arg_life |= SYNC_ARG << i;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = TS_DEAD;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
|
|
|
|
TCG_CALL_NO_READ_GLOBALS))) {
|
|
|
|
/* globals should go back to memory */
|
2018-03-05 12:29:27 +00:00
|
|
|
for (i = 0; i < nb_globals; i++) {
|
|
|
|
s->temps[i].state = TS_DEAD | TS_MEM;
|
|
|
|
}
|
2018-02-26 03:00:09 +00:00
|
|
|
} else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
|
|
|
|
/* globals should be synced to memory */
|
|
|
|
for (i = 0; i < nb_globals; i++) {
|
2018-03-05 12:29:27 +00:00
|
|
|
s->temps[i].state |= TS_MEM;
|
2018-02-26 03:00:09 +00:00
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-26 03:00:09 +00:00
|
|
|
/* record arguments that die in this helper */
|
2015-08-21 07:04:50 +00:00
|
|
|
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts && arg_ts->state & TS_DEAD) {
|
|
|
|
arg_life |= DEAD_ARG << i;
|
2018-02-26 03:00:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
/* input arguments are live for preceding opcodes */
|
|
|
|
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts) {
|
|
|
|
arg_ts->state &= ~TS_DEAD;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2018-02-11 17:31:22 +00:00
|
|
|
case INDEX_op_insn_start:
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
case INDEX_op_discard:
|
|
|
|
/* mark the temporary as dead */
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_temp(op->args[0])->state = TS_DEAD;
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case INDEX_op_add2_i32:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_add_i32;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_addsub2;
|
|
|
|
case INDEX_op_sub2_i32:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_sub_i32;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_addsub2;
|
|
|
|
case INDEX_op_add2_i64:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_add_i64;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_addsub2;
|
|
|
|
case INDEX_op_sub2_i64:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_sub_i64;
|
2015-08-21 07:04:50 +00:00
|
|
|
do_addsub2:
|
|
|
|
nb_iargs = 4;
|
|
|
|
nb_oargs = 2;
|
|
|
|
/* Test if the high part of the operation is dead, but not
|
|
|
|
the low part. The result can be optimized to a simple
|
|
|
|
add or sub. This happens often for x86_64 guest when the
|
|
|
|
cpu mode is set to 32 bit. */
|
2018-03-05 14:55:39 +00:00
|
|
|
if (arg_temp(op->args[1])->state == TS_DEAD) {
|
|
|
|
if (arg_temp(op->args[0])->state == TS_DEAD) {
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_remove;
|
|
|
|
}
|
2018-02-09 14:54:01 +00:00
|
|
|
/* Replace the opcode and adjust the args in place,
|
|
|
|
leaving 3 unused args at the end. */
|
|
|
|
op->opc = opc = opc_new;
|
2018-03-05 12:06:09 +00:00
|
|
|
op->args[1] = op->args[2];
|
|
|
|
op->args[2] = op->args[4];
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Fall through and mark the single-word operation live. */
|
|
|
|
nb_iargs = 2;
|
|
|
|
nb_oargs = 1;
|
|
|
|
}
|
|
|
|
goto do_not_remove;
|
|
|
|
|
|
|
|
case INDEX_op_mulu2_i32:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_mul_i32;
|
|
|
|
opc_new2 = INDEX_op_muluh_i32;
|
|
|
|
have_opc_new2 = TCG_TARGET_HAS_muluh_i32;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_mul2;
|
|
|
|
case INDEX_op_muls2_i32:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_mul_i32;
|
|
|
|
opc_new2 = INDEX_op_mulsh_i32;
|
|
|
|
have_opc_new2 = TCG_TARGET_HAS_mulsh_i32;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_mul2;
|
|
|
|
case INDEX_op_mulu2_i64:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_mul_i64;
|
|
|
|
opc_new2 = INDEX_op_muluh_i64;
|
|
|
|
have_opc_new2 = TCG_TARGET_HAS_muluh_i64;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_mul2;
|
|
|
|
case INDEX_op_muls2_i64:
|
2018-02-09 14:54:01 +00:00
|
|
|
opc_new = INDEX_op_mul_i64;
|
|
|
|
opc_new2 = INDEX_op_mulsh_i64;
|
|
|
|
have_opc_new2 = TCG_TARGET_HAS_mulsh_i64;
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_mul2;
|
|
|
|
do_mul2:
|
|
|
|
nb_iargs = 2;
|
|
|
|
nb_oargs = 2;
|
2018-03-05 14:55:39 +00:00
|
|
|
if (arg_temp(op->args[1])->state == TS_DEAD) {
|
|
|
|
if (arg_temp(op->args[0])->state == TS_DEAD) {
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Both parts of the operation are dead. */
|
|
|
|
goto do_remove;
|
|
|
|
}
|
|
|
|
/* The high part of the operation is dead; generate the low. */
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = opc = opc_new;
|
2018-03-05 12:06:09 +00:00
|
|
|
op->args[1] = op->args[2];
|
|
|
|
op->args[2] = op->args[3];
|
2018-03-05 14:55:39 +00:00
|
|
|
} else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) {
|
2018-03-12 22:03:02 +00:00
|
|
|
/* The low part of the operation is dead; generate the high. */
|
2018-02-09 14:54:01 +00:00
|
|
|
op->opc = opc = opc_new2;
|
2018-03-05 12:06:09 +00:00
|
|
|
op->args[0] = op->args[1];
|
|
|
|
op->args[1] = op->args[2];
|
|
|
|
op->args[2] = op->args[3];
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
goto do_not_remove;
|
|
|
|
}
|
|
|
|
/* Mark the single-word operation live. */
|
|
|
|
nb_oargs = 1;
|
|
|
|
goto do_not_remove;
|
|
|
|
|
|
|
|
default:
|
|
|
|
/* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
|
|
|
|
nb_iargs = def->nb_iargs;
|
|
|
|
nb_oargs = def->nb_oargs;
|
|
|
|
|
|
|
|
/* Test if the operation can be removed because all
|
|
|
|
its outputs are dead. We assume that nb_oargs == 0
|
|
|
|
implies side effects */
|
|
|
|
if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
|
2018-02-09 14:54:01 +00:00
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
if (arg_temp(op->args[i])->state != TS_DEAD) {
|
2015-08-21 07:04:50 +00:00
|
|
|
goto do_not_remove;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
do_remove:
|
2018-02-09 18:20:10 +00:00
|
|
|
tcg_op_remove(s, op);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
do_not_remove:
|
|
|
|
/* output args are dead */
|
2018-02-09 14:54:01 +00:00
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts->state & TS_DEAD) {
|
2018-02-26 02:27:00 +00:00
|
|
|
arg_life |= DEAD_ARG << i;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts->state & TS_MEM) {
|
2018-02-26 02:27:00 +00:00
|
|
|
arg_life |= SYNC_ARG << i;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = TS_DEAD;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* if end of basic block, update */
|
2015-12-21 10:01:01 +00:00
|
|
|
if (def->flags & TCG_OPF_BB_END) {
|
2015-09-22 01:30:05 +00:00
|
|
|
// Unicorn: do not optimize dead temps on brcond,
|
2015-08-21 07:04:50 +00:00
|
|
|
// this causes problem because check_exit_request() inserts
|
|
|
|
// brcond instruction in the middle of the TB,
|
|
|
|
// which incorrectly flags end-of-block
|
2018-02-26 03:00:09 +00:00
|
|
|
if (opc != INDEX_op_brcond_i32) {
|
2018-03-05 12:29:27 +00:00
|
|
|
tcg_la_bb_end(s);
|
2018-02-26 03:00:09 +00:00
|
|
|
} else {
|
|
|
|
// Unicorn: we do not touch dead temps for brcond,
|
|
|
|
// but we should refresh TCG globals In-Memory states,
|
|
|
|
// otherwise, important CPU states(especially conditional flags) might be forgotten,
|
|
|
|
// result in wrongly generated host code that run into wrong branch.
|
|
|
|
// Refer to https://github.com/unicorn-engine/unicorn/issues/287 for further information
|
2018-03-05 12:29:27 +00:00
|
|
|
tcg_la_br_end(s);
|
2018-02-26 03:00:09 +00:00
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
|
|
|
|
/* globals should be synced to memory */
|
2018-02-26 03:00:09 +00:00
|
|
|
for (i = 0; i < nb_globals; i++) {
|
2018-03-05 12:29:27 +00:00
|
|
|
s->temps[i].state |= TS_MEM;
|
2018-02-26 03:00:09 +00:00
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-26 03:00:09 +00:00
|
|
|
/* record arguments that die in this opcode */
|
2018-02-09 14:54:01 +00:00
|
|
|
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts->state & TS_DEAD) {
|
2018-02-26 02:27:00 +00:00
|
|
|
arg_life |= DEAD_ARG << i;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-26 03:00:09 +00:00
|
|
|
}
|
|
|
|
/* input arguments are live for preceding opcodes */
|
|
|
|
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_temp(op->args[i])->state &= ~TS_DEAD;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2018-02-26 02:49:33 +00:00
|
|
|
op->life = arg_life;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-26 03:23:00 +00:00
|
|
|
/* Liveness analysis: Convert indirect regs to direct temporaries. */
|
2018-03-05 12:29:27 +00:00
|
|
|
static bool liveness_pass_2(TCGContext *s)
|
2018-02-26 03:23:00 +00:00
|
|
|
{
|
|
|
|
int nb_globals = s->nb_globals;
|
2018-03-05 21:01:13 +00:00
|
|
|
int nb_temps, i;
|
2018-02-26 03:23:00 +00:00
|
|
|
bool changes = false;
|
2018-03-05 21:01:13 +00:00
|
|
|
TCGOp *op, *op_next;
|
2018-02-26 03:23:00 +00:00
|
|
|
|
|
|
|
/* Create a temporary for each indirect global. */
|
|
|
|
for (i = 0; i < nb_globals; ++i) {
|
|
|
|
TCGTemp *its = &s->temps[i];
|
|
|
|
if (its->indirect_reg) {
|
|
|
|
TCGTemp *dts = tcg_temp_alloc(s);
|
|
|
|
dts->type = its->type;
|
|
|
|
dts->base_type = its->base_type;
|
2018-03-05 12:29:27 +00:00
|
|
|
its->state_ptr = dts;
|
|
|
|
} else {
|
|
|
|
its->state_ptr = NULL;
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
2018-03-05 12:29:27 +00:00
|
|
|
/* All globals begin dead. */
|
|
|
|
its->state = TS_DEAD;
|
|
|
|
}
|
|
|
|
for (nb_temps = s->nb_temps; i < nb_temps; ++i) {
|
|
|
|
TCGTemp *its = &s->temps[i];
|
|
|
|
its->state_ptr = NULL;
|
|
|
|
its->state = TS_DEAD;
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
|
2018-02-26 03:23:00 +00:00
|
|
|
TCGOpcode opc = op->opc;
|
|
|
|
const TCGOpDef *def = &s->tcg_op_defs[opc];
|
|
|
|
TCGLifeData arg_life = op->life;
|
|
|
|
int nb_iargs, nb_oargs, call_flags;
|
2018-03-05 12:29:27 +00:00
|
|
|
TCGTemp *arg_ts, *dir_ts;
|
2018-02-26 03:23:00 +00:00
|
|
|
|
|
|
|
if (opc == INDEX_op_call) {
|
2018-03-05 21:51:53 +00:00
|
|
|
nb_oargs = TCGOP_CALLO(op);
|
|
|
|
nb_iargs = TCGOP_CALLI(op);
|
2018-03-05 12:06:09 +00:00
|
|
|
call_flags = op->args[nb_oargs + nb_iargs + 1];
|
2018-02-26 03:23:00 +00:00
|
|
|
} else {
|
|
|
|
nb_iargs = def->nb_iargs;
|
|
|
|
nb_oargs = def->nb_oargs;
|
|
|
|
|
|
|
|
/* Set flags similar to how calls require. */
|
|
|
|
if (def->flags & TCG_OPF_BB_END) {
|
|
|
|
/* Like writing globals: save_globals */
|
|
|
|
call_flags = 0;
|
|
|
|
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
|
|
|
|
/* Like reading globals: sync_globals */
|
|
|
|
call_flags = TCG_CALL_NO_WRITE_GLOBALS;
|
|
|
|
} else {
|
|
|
|
/* No effect on globals. */
|
|
|
|
call_flags = (TCG_CALL_NO_READ_GLOBALS |
|
|
|
|
TCG_CALL_NO_WRITE_GLOBALS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure that input arguments are available. */
|
|
|
|
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts) {
|
|
|
|
dir_ts = arg_ts->state_ptr;
|
|
|
|
if (dir_ts && arg_ts->state == TS_DEAD) {
|
|
|
|
TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32
|
2018-02-26 03:23:00 +00:00
|
|
|
? INDEX_op_ld_i32
|
|
|
|
: INDEX_op_ld_i64);
|
|
|
|
TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3);
|
|
|
|
|
2018-03-05 14:55:39 +00:00
|
|
|
lop->args[0] = temp_arg(dir_ts);
|
|
|
|
lop->args[1] = temp_arg(arg_ts->mem_base);
|
2018-03-05 12:29:27 +00:00
|
|
|
lop->args[2] = arg_ts->mem_offset;
|
2018-02-26 03:23:00 +00:00
|
|
|
|
|
|
|
/* Loaded, but synced with memory. */
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = TS_MEM;
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Perform input replacement, and mark inputs that became dead.
|
|
|
|
No action is required except keeping temp_state up to date
|
|
|
|
so that we reload when needed. */
|
|
|
|
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
if (arg_ts) {
|
|
|
|
dir_ts = arg_ts->state_ptr;
|
|
|
|
if (dir_ts) {
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[i] = temp_arg(dir_ts);
|
2018-02-26 03:23:00 +00:00
|
|
|
changes = true;
|
|
|
|
if (IS_DEAD_ARG(i)) {
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = TS_DEAD;
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Liveness analysis should ensure that the following are
|
|
|
|
all correct, for call sites and basic block end points. */
|
|
|
|
if (call_flags & TCG_CALL_NO_READ_GLOBALS) {
|
|
|
|
/* Nothing to do */
|
|
|
|
} else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) {
|
|
|
|
for (i = 0; i < nb_globals; ++i) {
|
|
|
|
/* Liveness should see that globals are synced back,
|
|
|
|
that is, either TS_DEAD or TS_MEM. */
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts = &s->temps[i];
|
|
|
|
tcg_debug_assert(arg_ts->state_ptr == 0
|
|
|
|
|| arg_ts->state != 0);
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < nb_globals; ++i) {
|
|
|
|
/* Liveness should see that globals are saved back,
|
|
|
|
that is, TS_DEAD, waiting to be reloaded. */
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts = &s->temps[i];
|
|
|
|
tcg_debug_assert(arg_ts->state_ptr == 0
|
|
|
|
|| arg_ts->state == TS_DEAD);
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Outputs become available. */
|
|
|
|
for (i = 0; i < nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
arg_ts = arg_temp(op->args[i]);
|
2018-03-05 12:29:27 +00:00
|
|
|
dir_ts = arg_ts->state_ptr;
|
|
|
|
if (!dir_ts) {
|
2018-02-26 03:23:00 +00:00
|
|
|
continue;
|
|
|
|
}
|
2018-03-05 14:55:39 +00:00
|
|
|
op->args[i] = temp_arg(dir_ts);
|
2018-02-26 03:23:00 +00:00
|
|
|
changes = true;
|
|
|
|
|
|
|
|
/* The output is now live and modified. */
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = 0;
|
2018-02-26 03:23:00 +00:00
|
|
|
|
|
|
|
/* Sync outputs upon their last write. */
|
|
|
|
if (NEED_SYNC_ARG(i)) {
|
2018-03-05 12:29:27 +00:00
|
|
|
TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32
|
2018-02-26 03:23:00 +00:00
|
|
|
? INDEX_op_st_i32
|
|
|
|
: INDEX_op_st_i64);
|
|
|
|
TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3);
|
|
|
|
|
2018-03-05 14:55:39 +00:00
|
|
|
sop->args[0] = temp_arg(dir_ts);
|
|
|
|
sop->args[1] = temp_arg(arg_ts->mem_base);
|
2018-03-05 12:29:27 +00:00
|
|
|
sop->args[2] = arg_ts->mem_offset;
|
2018-02-26 03:23:00 +00:00
|
|
|
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = TS_MEM;
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
/* Drop outputs that are dead. */
|
|
|
|
if (IS_DEAD_ARG(i)) {
|
2018-03-05 12:29:27 +00:00
|
|
|
arg_ts->state = TS_DEAD;
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return changes;
|
|
|
|
}
|
|
|
|
|
2018-02-23 18:55:11 +00:00
|
|
|
#ifdef CONFIG_DEBUG_TCG
|
2015-08-21 07:04:50 +00:00
|
|
|
static void dump_regs(TCGContext *s)
|
|
|
|
{
|
|
|
|
TCGTemp *ts;
|
|
|
|
int i;
|
|
|
|
char buf[64];
|
|
|
|
|
|
|
|
for(i = 0; i < s->nb_temps; i++) {
|
|
|
|
ts = &s->temps[i];
|
2018-03-05 12:16:49 +00:00
|
|
|
printf(" %10s: ", tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts));
|
2015-08-21 07:04:50 +00:00
|
|
|
switch(ts->val_type) {
|
|
|
|
case TEMP_VAL_REG:
|
|
|
|
printf("%s", tcg_target_reg_names[ts->reg]);
|
|
|
|
break;
|
|
|
|
case TEMP_VAL_MEM:
|
2018-02-08 18:03:59 +00:00
|
|
|
printf("%d(%s)", (int)ts->mem_offset
|
|
|
|
tcg_target_reg_names[ts->mem_base->reg]);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
case TEMP_VAL_CONST:
|
|
|
|
printf("$0x%" TCG_PRIlx, ts->val);
|
|
|
|
break;
|
|
|
|
case TEMP_VAL_DEAD:
|
|
|
|
printf("D");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("???");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
|
2018-02-19 16:30:24 +00:00
|
|
|
if (s->reg_to_temp[i] != NULL) {
|
2015-08-21 07:04:50 +00:00
|
|
|
printf("%s: %s\n",
|
|
|
|
tcg_target_reg_names[i],
|
2018-02-19 16:30:24 +00:00
|
|
|
tcg_get_arg_str_ptr(s, buf, sizeof(buf), s->reg_to_temp[i]));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void check_regs(TCGContext *s)
|
|
|
|
{
|
2018-02-21 00:12:37 +00:00
|
|
|
int reg;
|
2018-02-19 07:06:03 +00:00
|
|
|
int k;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGTemp *ts;
|
|
|
|
char buf[64];
|
|
|
|
|
2018-02-19 16:30:24 +00:00
|
|
|
for (reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
|
|
|
|
ts = s->reg_to_temp[reg];
|
|
|
|
if (ts != NULL) {
|
|
|
|
if (ts->val_type != TEMP_VAL_REG || ts->reg != reg) {
|
2015-08-21 07:04:50 +00:00
|
|
|
printf("Inconsistency for register %s:\n",
|
|
|
|
tcg_target_reg_names[reg]);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2018-02-19 16:30:24 +00:00
|
|
|
for (k = 0; k < s->nb_temps; k++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
ts = &s->temps[k];
|
2018-02-19 16:30:24 +00:00
|
|
|
if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg
|
|
|
|
&& s->reg_to_temp[ts->reg] != ts) {
|
|
|
|
printf("Inconsistency for temp %s:\n",
|
|
|
|
tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts));
|
2015-08-21 07:04:50 +00:00
|
|
|
fail:
|
2018-02-19 16:30:24 +00:00
|
|
|
printf("reg state:\n");
|
|
|
|
dump_regs(s);
|
|
|
|
tcg_abort();
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-03-05 12:51:38 +00:00
|
|
|
static void temp_allocate_frame(TCGContext *s, TCGTemp *ts)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
|
|
|
#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
|
|
|
|
/* Sparc64 stack is accessed with offset of 2047 */
|
|
|
|
s->current_frame_offset = (s->current_frame_offset +
|
|
|
|
(tcg_target_long)sizeof(tcg_target_long) - 1) &
|
|
|
|
~(sizeof(tcg_target_long) - 1);
|
|
|
|
#endif
|
|
|
|
if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
|
|
|
|
s->frame_end) {
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
ts->mem_offset = s->current_frame_offset;
|
2018-02-08 18:03:59 +00:00
|
|
|
ts->mem_base = s->frame_temp;
|
2015-08-21 07:04:50 +00:00
|
|
|
ts->mem_allocated = 1;
|
|
|
|
s->current_frame_offset += sizeof(tcg_target_long);
|
|
|
|
}
|
|
|
|
|
2018-02-21 00:18:44 +00:00
|
|
|
static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet);
|
|
|
|
|
2018-02-25 06:41:28 +00:00
|
|
|
/* Mark a temporary as free or dead. If 'free_or_dead' is negative,
|
|
|
|
mark it free; otherwise mark it dead. */
|
|
|
|
static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-02-25 06:41:28 +00:00
|
|
|
if (ts->fixed_reg) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (ts->val_type == TEMP_VAL_REG) {
|
|
|
|
s->reg_to_temp[ts->reg] = NULL;
|
|
|
|
}
|
|
|
|
ts->val_type = (free_or_dead < 0
|
|
|
|
|| ts->temp_local
|
2018-03-05 12:21:07 +00:00
|
|
|
|| ts->temp_global
|
2018-02-25 06:41:28 +00:00
|
|
|
? TEMP_VAL_MEM : TEMP_VAL_DEAD);
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-25 06:41:28 +00:00
|
|
|
/* Mark a temporary as dead. */
|
|
|
|
static inline void temp_dead(TCGContext *s, TCGTemp *ts)
|
|
|
|
{
|
|
|
|
temp_free_or_dead(s, ts, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
|
|
|
|
registers needs to be allocated to store a constant. If 'free_or_dead'
|
|
|
|
is non-zero, subsequently release the temporary; if it is positive, the
|
|
|
|
temp is dead; if it is negative, the temp is free. */
|
|
|
|
static void temp_sync(TCGContext *s, TCGTemp *ts,
|
|
|
|
TCGRegSet allocated_regs, int free_or_dead)
|
|
|
|
{
|
|
|
|
if (ts->fixed_reg) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!ts->mem_coherent) {
|
2015-08-21 07:04:50 +00:00
|
|
|
if (!ts->mem_allocated) {
|
2018-03-05 12:51:38 +00:00
|
|
|
temp_allocate_frame(s, ts);
|
2018-02-25 06:41:28 +00:00
|
|
|
}
|
|
|
|
switch (ts->val_type) {
|
|
|
|
case TEMP_VAL_CONST:
|
|
|
|
/* If we're going to free the temp immediately, then we won't
|
|
|
|
require it later in a register, so attempt to store the
|
|
|
|
constant to memory directly. */
|
|
|
|
if (free_or_dead
|
|
|
|
&& tcg_out_sti(s, ts->type, ts->val,
|
|
|
|
ts->mem_base->reg, ts->mem_offset)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
temp_load(s, ts, s->tcg_target_available_regs[ts->type],
|
|
|
|
allocated_regs);
|
|
|
|
/* fallthrough */
|
|
|
|
|
|
|
|
case TEMP_VAL_REG:
|
|
|
|
tcg_out_st(s, ts->type, ts->reg,
|
|
|
|
ts->mem_base->reg, ts->mem_offset);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TEMP_VAL_MEM:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TEMP_VAL_DEAD:
|
|
|
|
default:
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
ts->mem_coherent = 1;
|
|
|
|
}
|
|
|
|
if (free_or_dead) {
|
|
|
|
temp_free_or_dead(s, ts, free_or_dead);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* free register 'reg' by spilling the corresponding temporary if necessary */
|
2018-02-21 00:18:44 +00:00
|
|
|
static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-02-19 16:30:24 +00:00
|
|
|
TCGTemp *ts = s->reg_to_temp[reg];
|
|
|
|
if (ts != NULL) {
|
2018-02-25 06:41:28 +00:00
|
|
|
temp_sync(s, ts, allocated_regs, -1);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate a register belonging to reg1 & ~reg2 */
|
2018-02-21 00:18:44 +00:00
|
|
|
static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs,
|
2018-02-21 00:24:31 +00:00
|
|
|
TCGRegSet allocated_regs, bool rev)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-02-21 00:24:31 +00:00
|
|
|
int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order);
|
|
|
|
const int *order;
|
2018-02-19 07:06:03 +00:00
|
|
|
TCGReg reg;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGRegSet reg_ct;
|
|
|
|
|
2018-03-05 04:34:12 +00:00
|
|
|
reg_ct = desired_regs & ~allocated_regs;
|
2018-02-21 00:24:31 +00:00
|
|
|
order = rev ? s->indirect_reg_alloc_order : tcg_target_reg_alloc_order;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
/* first try free registers */
|
2018-02-21 00:24:31 +00:00
|
|
|
for(i = 0; i < n; i++) {
|
|
|
|
reg = order[i];
|
2018-02-19 16:30:24 +00:00
|
|
|
if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL)
|
2015-08-21 07:04:50 +00:00
|
|
|
return reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: do better spill choice */
|
2018-02-21 00:24:31 +00:00
|
|
|
for(i = 0; i < n; i++) {
|
|
|
|
reg = order[i];
|
2015-08-21 07:04:50 +00:00
|
|
|
if (tcg_regset_test_reg(reg_ct, reg)) {
|
2018-02-21 00:18:44 +00:00
|
|
|
tcg_reg_free(s, reg, allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
return reg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
|
2018-02-19 16:43:59 +00:00
|
|
|
/* Make sure the temporary is in a register. If needed, allocate the register
|
|
|
|
from DESIRED while avoiding ALLOCATED. */
|
|
|
|
static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
|
|
|
|
TCGRegSet allocated_regs)
|
|
|
|
{
|
|
|
|
TCGReg reg;
|
|
|
|
|
|
|
|
switch (ts->val_type) {
|
|
|
|
case TEMP_VAL_REG:
|
|
|
|
return;
|
|
|
|
case TEMP_VAL_CONST:
|
2018-02-21 00:24:31 +00:00
|
|
|
reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base);
|
2018-02-19 16:43:59 +00:00
|
|
|
tcg_out_movi(s, ts->type, reg, ts->val);
|
|
|
|
ts->mem_coherent = 0;
|
|
|
|
break;
|
|
|
|
case TEMP_VAL_MEM:
|
2018-02-21 00:24:31 +00:00
|
|
|
reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base);
|
2018-02-19 16:43:59 +00:00
|
|
|
tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset);
|
|
|
|
ts->mem_coherent = 1;
|
|
|
|
break;
|
|
|
|
case TEMP_VAL_DEAD:
|
|
|
|
default:
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
ts->reg = reg;
|
|
|
|
ts->val_type = TEMP_VAL_REG;
|
|
|
|
s->reg_to_temp[reg] = ts;
|
|
|
|
}
|
|
|
|
|
2018-02-25 06:41:28 +00:00
|
|
|
/* Save a temporary to memory. 'allocated_regs' is used in case a
|
|
|
|
temporary registers needs to be allocated to store a constant. */
|
|
|
|
static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-02-26 03:23:00 +00:00
|
|
|
/* The liveness analysis already ensures that globals are back
|
|
|
|
in memory. Keep an tcg_debug_assert for safety. */
|
|
|
|
tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* save globals to their canonical location and assume they can be
|
|
|
|
modified be the following code. 'allocated_regs' is used in case a
|
|
|
|
temporary registers needs to be allocated to store a constant. */
|
|
|
|
static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
|
|
|
|
{
|
2018-03-05 12:49:59 +00:00
|
|
|
int i, n;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 12:49:59 +00:00
|
|
|
for (i = 0, n = s->nb_globals; i < n; i++) {
|
2018-02-19 16:39:01 +00:00
|
|
|
temp_save(s, &s->temps[i], allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* sync globals to their canonical location and assume they can be
|
|
|
|
read by the following code. 'allocated_regs' is used in case a
|
|
|
|
temporary registers needs to be allocated to store a constant. */
|
|
|
|
static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
|
|
|
|
{
|
2018-03-05 12:49:59 +00:00
|
|
|
int i, n;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 12:49:59 +00:00
|
|
|
for (i = 0, n = s->nb_globals; i < n; i++) {
|
2018-02-19 16:36:09 +00:00
|
|
|
TCGTemp *ts = &s->temps[i];
|
2018-02-26 03:23:00 +00:00
|
|
|
tcg_debug_assert(ts->val_type != TEMP_VAL_REG
|
|
|
|
|| ts->fixed_reg
|
|
|
|
|| ts->mem_coherent);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* at the end of a basic block, we assume all temporaries are dead and
|
|
|
|
all globals are stored at their canonical location. */
|
|
|
|
static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2018-02-19 16:39:01 +00:00
|
|
|
for (i = s->nb_globals; i < s->nb_temps; i++) {
|
|
|
|
TCGTemp *ts = &s->temps[i];
|
2015-08-21 07:04:50 +00:00
|
|
|
if (ts->temp_local) {
|
2018-02-19 16:39:01 +00:00
|
|
|
temp_save(s, ts, allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
2018-02-26 03:23:00 +00:00
|
|
|
/* The liveness analysis already ensures that temps are dead.
|
|
|
|
Keep an tcg_debug_assert for safety. */
|
|
|
|
tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
save_globals(s, allocated_regs);
|
|
|
|
}
|
|
|
|
|
2018-02-26 15:08:44 +00:00
|
|
|
static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
|
|
|
|
tcg_target_ulong val, TCGLifeData arg_life)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
|
|
|
if (ots->fixed_reg) {
|
2018-02-25 06:41:28 +00:00
|
|
|
/* For fixed registers, we do not do any constant propagation. */
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_out_movi(s, ots->type, ots->reg, val);
|
2018-02-25 06:41:28 +00:00
|
|
|
return;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2018-02-25 06:41:28 +00:00
|
|
|
/* The movi is not explicitly generated here. */
|
|
|
|
if (ots->val_type == TEMP_VAL_REG) {
|
|
|
|
s->reg_to_temp[ots->reg] = NULL;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-25 06:41:28 +00:00
|
|
|
ots->val_type = TEMP_VAL_CONST;
|
|
|
|
ots->val = val;
|
|
|
|
ots->mem_coherent = 0;
|
|
|
|
if (NEED_SYNC_ARG(0)) {
|
|
|
|
temp_sync(s, ots, s->reserved_regs, IS_DEAD_ARG(0));
|
|
|
|
} else if (IS_DEAD_ARG(0)) {
|
2018-02-19 16:34:14 +00:00
|
|
|
temp_dead(s, ots);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-05 12:12:09 +00:00
|
|
|
static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op)
|
2018-02-26 15:08:44 +00:00
|
|
|
{
|
2018-03-05 14:55:39 +00:00
|
|
|
TCGTemp *ots = arg_temp(op->args[0]);
|
2018-03-05 12:12:09 +00:00
|
|
|
tcg_target_ulong val = op->args[1];
|
2018-02-26 15:08:44 +00:00
|
|
|
|
2018-03-05 12:12:09 +00:00
|
|
|
tcg_reg_alloc_do_movi(s, ots, val, op->life);
|
2018-02-26 15:08:44 +00:00
|
|
|
}
|
|
|
|
|
2018-03-05 12:12:09 +00:00
|
|
|
static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 12:12:09 +00:00
|
|
|
const TCGLifeData arg_life = op->life;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGRegSet allocated_regs;
|
|
|
|
TCGTemp *ts, *ots;
|
|
|
|
TCGType otype, itype;
|
|
|
|
|
2018-03-05 04:30:01 +00:00
|
|
|
allocated_regs = s->reserved_regs;
|
2018-03-05 14:55:39 +00:00
|
|
|
ots = arg_temp(op->args[0]);
|
|
|
|
ts = arg_temp(op->args[1]);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
/* Note that otype != itype for no-op truncation. */
|
|
|
|
otype = ots->type;
|
|
|
|
itype = ts->type;
|
|
|
|
|
2018-02-26 15:08:44 +00:00
|
|
|
if (ts->val_type == TEMP_VAL_CONST) {
|
|
|
|
/* propagate constant or generate sti */
|
|
|
|
tcg_target_ulong val = ts->val;
|
|
|
|
if (IS_DEAD_ARG(1)) {
|
|
|
|
temp_dead(s, ts);
|
|
|
|
}
|
|
|
|
tcg_reg_alloc_do_movi(s, ots, val, arg_life);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the source value is in memory we're going to be forced
|
|
|
|
to have it in a register in order to perform the copy. Copy
|
|
|
|
the SOURCE value into its own register first, that way we
|
|
|
|
don't have to reload SOURCE the next time it is used. */
|
|
|
|
if (ts->val_type == TEMP_VAL_MEM) {
|
2018-02-19 16:43:59 +00:00
|
|
|
temp_load(s, ts, s->tcg_target_available_regs[itype], allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
2018-02-26 15:08:44 +00:00
|
|
|
tcg_debug_assert(ts->val_type == TEMP_VAL_REG);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
|
|
|
|
/* mov to a non-saved dead register makes no sense (even with
|
|
|
|
liveness analysis disabled). */
|
2018-02-23 18:52:01 +00:00
|
|
|
tcg_debug_assert(NEED_SYNC_ARG(0));
|
2015-08-21 07:04:50 +00:00
|
|
|
if (!ots->mem_allocated) {
|
2018-03-05 12:51:38 +00:00
|
|
|
temp_allocate_frame(s, ots);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-08 18:03:59 +00:00
|
|
|
tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset);
|
2015-08-21 07:04:50 +00:00
|
|
|
if (IS_DEAD_ARG(1)) {
|
2018-02-19 16:34:14 +00:00
|
|
|
temp_dead(s, ts);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-19 16:34:14 +00:00
|
|
|
temp_dead(s, ots);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
|
|
|
|
/* the mov can be suppressed */
|
|
|
|
if (ots->val_type == TEMP_VAL_REG) {
|
2018-02-19 16:30:24 +00:00
|
|
|
s->reg_to_temp[ots->reg] = NULL;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
ots->reg = ts->reg;
|
2018-02-19 16:34:14 +00:00
|
|
|
temp_dead(s, ts);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
if (ots->val_type != TEMP_VAL_REG) {
|
|
|
|
/* When allocating a new register, make sure to not spill the
|
|
|
|
input one. */
|
|
|
|
tcg_regset_set_reg(allocated_regs, ts->reg);
|
2017-01-19 11:50:28 +00:00
|
|
|
ots->reg = tcg_reg_alloc(s, (TCGRegSet)s->tcg_target_available_regs[otype],
|
2018-02-21 00:24:31 +00:00
|
|
|
allocated_regs, ots->indirect_base);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
tcg_out_mov(s, otype, ots->reg, ts->reg);
|
|
|
|
}
|
|
|
|
ots->val_type = TEMP_VAL_REG;
|
|
|
|
ots->mem_coherent = 0;
|
2018-02-19 16:30:24 +00:00
|
|
|
s->reg_to_temp[ots->reg] = ots;
|
2015-08-21 07:04:50 +00:00
|
|
|
if (NEED_SYNC_ARG(0)) {
|
2018-02-25 06:41:28 +00:00
|
|
|
temp_sync(s, ots, allocated_regs, 0);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-05 12:12:09 +00:00
|
|
|
static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 12:12:09 +00:00
|
|
|
const TCGLifeData arg_life = op->life;
|
|
|
|
const TCGOpDef * const def = &s->tcg_op_defs[op->opc];
|
2018-03-01 20:24:47 +00:00
|
|
|
TCGRegSet i_allocated_regs;
|
|
|
|
TCGRegSet o_allocated_regs;
|
2018-02-19 07:06:03 +00:00
|
|
|
int i, k, nb_iargs, nb_oargs;
|
|
|
|
TCGReg reg;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGArg arg;
|
|
|
|
const TCGArgConstraint *arg_ct;
|
|
|
|
TCGTemp *ts;
|
|
|
|
TCGArg new_args[TCG_MAX_OP_ARGS];
|
|
|
|
int const_args[TCG_MAX_OP_ARGS];
|
|
|
|
|
|
|
|
nb_oargs = def->nb_oargs;
|
|
|
|
nb_iargs = def->nb_iargs;
|
|
|
|
|
|
|
|
/* copy constants */
|
2018-03-12 22:03:02 +00:00
|
|
|
memcpy(new_args + nb_oargs + nb_iargs,
|
2018-03-05 12:12:09 +00:00
|
|
|
op->args + nb_oargs + nb_iargs,
|
2015-08-21 07:04:50 +00:00
|
|
|
sizeof(TCGArg) * def->nb_cargs);
|
|
|
|
|
2018-03-05 04:30:01 +00:00
|
|
|
i_allocated_regs = s->reserved_regs;
|
|
|
|
o_allocated_regs = s->reserved_regs;
|
2018-03-01 20:24:47 +00:00
|
|
|
|
2018-03-12 22:03:02 +00:00
|
|
|
/* satisfy input constraints */
|
2018-03-05 12:12:09 +00:00
|
|
|
for (k = 0; k < nb_iargs; k++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
i = def->sorted_args[nb_oargs + k];
|
2018-03-05 12:12:09 +00:00
|
|
|
arg = op->args[i];
|
2015-08-21 07:04:50 +00:00
|
|
|
arg_ct = &def->args_ct[i];
|
2018-03-05 14:55:39 +00:00
|
|
|
ts = arg_temp(arg);
|
2018-02-19 16:43:59 +00:00
|
|
|
|
|
|
|
if (ts->val_type == TEMP_VAL_CONST
|
|
|
|
&& tcg_target_const_match(ts->val, ts->type, arg_ct)) {
|
|
|
|
/* constant is OK for instruction */
|
|
|
|
const_args[i] = 1;
|
|
|
|
new_args[i] = ts->val;
|
|
|
|
goto iarg_end;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-19 16:43:59 +00:00
|
|
|
|
2018-03-01 20:24:47 +00:00
|
|
|
temp_load(s, ts, arg_ct->u.regs, i_allocated_regs);
|
2018-02-19 16:43:59 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
if (arg_ct->ct & TCG_CT_IALIAS) {
|
|
|
|
if (ts->fixed_reg) {
|
|
|
|
/* if fixed register, we must allocate a new register
|
|
|
|
if the alias is not the same register */
|
2018-03-05 12:12:09 +00:00
|
|
|
if (arg != op->args[arg_ct->alias_index])
|
2015-08-21 07:04:50 +00:00
|
|
|
goto allocate_in_reg;
|
|
|
|
} else {
|
|
|
|
/* if the input is aliased to an output and if it is
|
|
|
|
not dead after the instruction, we must allocate
|
|
|
|
a new register and move it */
|
|
|
|
if (!IS_DEAD_ARG(i)) {
|
|
|
|
goto allocate_in_reg;
|
|
|
|
}
|
2018-03-05 04:30:01 +00:00
|
|
|
/* check if the current register has already been allocated
|
|
|
|
for another input aliased to an output */
|
|
|
|
int k2, i2;
|
|
|
|
for (k2 = 0 ; k2 < k ; k2++) {
|
|
|
|
i2 = def->sorted_args[nb_oargs + k2];
|
|
|
|
if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
|
|
|
|
(new_args[i2] == ts->reg)) {
|
|
|
|
goto allocate_in_reg;
|
|
|
|
}
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
reg = ts->reg;
|
|
|
|
if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
|
|
|
|
/* nothing to do : the constraint is satisfied */
|
|
|
|
} else {
|
|
|
|
allocate_in_reg:
|
2018-03-12 22:03:02 +00:00
|
|
|
/* allocate a new register matching the constraint
|
2015-08-21 07:04:50 +00:00
|
|
|
and move the temporary register into it */
|
2018-03-01 20:24:47 +00:00
|
|
|
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
|
2018-02-21 00:24:31 +00:00
|
|
|
ts->indirect_base);
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_out_mov(s, ts->type, reg, ts->reg);
|
|
|
|
}
|
|
|
|
new_args[i] = reg;
|
|
|
|
const_args[i] = 0;
|
2018-03-01 20:24:47 +00:00
|
|
|
tcg_regset_set_reg(i_allocated_regs, reg);
|
2015-08-21 07:04:50 +00:00
|
|
|
iarg_end: ;
|
|
|
|
}
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* mark dead temporaries and free the associated registers */
|
|
|
|
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
|
|
|
|
if (IS_DEAD_ARG(i)) {
|
2018-03-05 14:55:39 +00:00
|
|
|
temp_dead(s, arg_temp(op->args[i]));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (def->flags & TCG_OPF_BB_END) {
|
2018-03-01 20:24:47 +00:00
|
|
|
tcg_reg_alloc_bb_end(s, i_allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
if (def->flags & TCG_OPF_CALL_CLOBBER) {
|
2018-03-12 22:03:02 +00:00
|
|
|
/* XXX: permit generic clobber register list ? */
|
2018-03-05 04:30:01 +00:00
|
|
|
for (i = 0; i < TCG_TARGET_NB_REGS; i++) {
|
2018-02-19 16:22:12 +00:00
|
|
|
if (tcg_regset_test_reg(s->tcg_target_call_clobber_regs, i)) {
|
2018-03-01 20:24:47 +00:00
|
|
|
tcg_reg_free(s, i, i_allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (def->flags & TCG_OPF_SIDE_EFFECTS) {
|
|
|
|
/* sync globals if the op has side effects and might trigger
|
|
|
|
an exception. */
|
2018-03-01 20:24:47 +00:00
|
|
|
sync_globals(s, i_allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* satisfy the output constraints */
|
|
|
|
for(k = 0; k < nb_oargs; k++) {
|
|
|
|
i = def->sorted_args[k];
|
2018-03-05 12:12:09 +00:00
|
|
|
arg = op->args[i];
|
2015-08-21 07:04:50 +00:00
|
|
|
arg_ct = &def->args_ct[i];
|
2018-03-05 14:55:39 +00:00
|
|
|
ts = arg_temp(arg);
|
2018-03-01 20:49:03 +00:00
|
|
|
if ((arg_ct->ct & TCG_CT_ALIAS)
|
|
|
|
&& !const_args[arg_ct->alias_index]) {
|
2015-08-21 07:04:50 +00:00
|
|
|
reg = new_args[arg_ct->alias_index];
|
2018-03-01 20:24:47 +00:00
|
|
|
} else if (arg_ct->ct & TCG_CT_NEWREG) {
|
|
|
|
reg = tcg_reg_alloc(s, arg_ct->u.regs,
|
|
|
|
i_allocated_regs | o_allocated_regs,
|
|
|
|
ts->indirect_base);
|
2015-08-21 07:04:50 +00:00
|
|
|
} else {
|
|
|
|
/* if fixed register, we try to use it */
|
|
|
|
reg = ts->reg;
|
|
|
|
if (ts->fixed_reg &&
|
|
|
|
tcg_regset_test_reg(arg_ct->u.regs, reg)) {
|
|
|
|
goto oarg_end;
|
|
|
|
}
|
2018-03-01 20:24:47 +00:00
|
|
|
reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
|
2018-02-21 00:24:31 +00:00
|
|
|
ts->indirect_base);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-03-01 20:24:47 +00:00
|
|
|
tcg_regset_set_reg(o_allocated_regs, reg);
|
2015-08-21 07:04:50 +00:00
|
|
|
/* if a fixed register is used, then a move will be done afterwards */
|
|
|
|
if (!ts->fixed_reg) {
|
|
|
|
if (ts->val_type == TEMP_VAL_REG) {
|
2018-02-19 16:30:24 +00:00
|
|
|
s->reg_to_temp[ts->reg] = NULL;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
ts->val_type = TEMP_VAL_REG;
|
|
|
|
ts->reg = reg;
|
|
|
|
/* temp value is modified, so the value kept in memory is
|
|
|
|
potentially not the same */
|
|
|
|
ts->mem_coherent = 0;
|
2018-02-19 16:30:24 +00:00
|
|
|
s->reg_to_temp[reg] = ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
oarg_end:
|
|
|
|
new_args[i] = reg;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* emit instruction */
|
2018-03-06 16:49:50 +00:00
|
|
|
if (def->flags & TCG_OPF_VECTOR) {
|
|
|
|
tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
|
|
|
|
new_args, const_args);
|
|
|
|
} else {
|
|
|
|
tcg_out_op(s, op->opc, new_args, const_args);
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
/* move the outputs in the correct register if needed */
|
|
|
|
for(i = 0; i < nb_oargs; i++) {
|
2018-03-05 14:55:39 +00:00
|
|
|
ts = arg_temp(op->args[i]);
|
2015-08-21 07:04:50 +00:00
|
|
|
reg = new_args[i];
|
|
|
|
if (ts->fixed_reg && ts->reg != reg) {
|
|
|
|
tcg_out_mov(s, ts->type, ts->reg, reg);
|
|
|
|
}
|
|
|
|
if (NEED_SYNC_ARG(i)) {
|
2018-03-01 20:24:47 +00:00
|
|
|
temp_sync(s, ts, o_allocated_regs, IS_DEAD_ARG(i));
|
2018-02-25 06:41:28 +00:00
|
|
|
} else if (IS_DEAD_ARG(i)) {
|
2018-02-19 16:34:14 +00:00
|
|
|
temp_dead(s, ts);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef TCG_TARGET_STACK_GROWSUP
|
|
|
|
#define STACK_DIR(x) (-(x))
|
|
|
|
#else
|
|
|
|
#define STACK_DIR(x) (x)
|
|
|
|
#endif
|
|
|
|
|
2018-03-05 12:12:09 +00:00
|
|
|
static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 21:51:53 +00:00
|
|
|
const int nb_oargs = TCGOP_CALLO(op);
|
|
|
|
const int nb_iargs = TCGOP_CALLI(op);
|
2018-03-05 12:12:09 +00:00
|
|
|
const TCGLifeData arg_life = op->life;
|
2018-02-19 07:06:03 +00:00
|
|
|
int flags, nb_regs, i;
|
|
|
|
TCGReg reg;
|
2015-08-21 07:04:50 +00:00
|
|
|
TCGArg arg;
|
|
|
|
TCGTemp *ts;
|
|
|
|
intptr_t stack_offset;
|
|
|
|
size_t call_stack_size;
|
|
|
|
tcg_insn_unit *func_addr;
|
|
|
|
int allocate_args;
|
|
|
|
TCGRegSet allocated_regs;
|
|
|
|
|
2018-03-05 12:12:09 +00:00
|
|
|
func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs];
|
|
|
|
flags = op->args[nb_oargs + nb_iargs + 1];
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
|
2018-02-09 14:54:01 +00:00
|
|
|
if (nb_regs > nb_iargs) {
|
|
|
|
nb_regs = nb_iargs;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* assign stack slots first */
|
2018-02-09 14:54:01 +00:00
|
|
|
call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long);
|
2015-08-21 07:04:50 +00:00
|
|
|
call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
|
|
|
|
~(TCG_TARGET_STACK_ALIGN - 1);
|
|
|
|
allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
|
|
|
|
if (allocate_args) {
|
|
|
|
/* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
|
|
|
|
preallocate call stack */
|
|
|
|
tcg_abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
|
2018-03-05 12:12:09 +00:00
|
|
|
for (i = nb_regs; i < nb_iargs; i++) {
|
|
|
|
arg = op->args[nb_oargs + i];
|
2015-08-21 07:04:50 +00:00
|
|
|
#ifdef TCG_TARGET_STACK_GROWSUP
|
|
|
|
stack_offset -= sizeof(tcg_target_long);
|
|
|
|
#endif
|
|
|
|
if (arg != TCG_CALL_DUMMY_ARG) {
|
2018-03-05 14:55:39 +00:00
|
|
|
ts = arg_temp(arg);
|
2018-02-19 16:43:59 +00:00
|
|
|
temp_load(s, ts, s->tcg_target_available_regs[ts->type],
|
|
|
|
s->reserved_regs);
|
|
|
|
tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
#ifndef TCG_TARGET_STACK_GROWSUP
|
|
|
|
stack_offset += sizeof(tcg_target_long);
|
|
|
|
#endif
|
|
|
|
}
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* assign input registers */
|
2018-03-05 04:30:01 +00:00
|
|
|
allocated_regs = s->reserved_regs;
|
2018-03-05 12:12:09 +00:00
|
|
|
for (i = 0; i < nb_regs; i++) {
|
|
|
|
arg = op->args[nb_oargs + i];
|
2015-08-21 07:04:50 +00:00
|
|
|
if (arg != TCG_CALL_DUMMY_ARG) {
|
2018-03-05 14:55:39 +00:00
|
|
|
ts = arg_temp(arg);
|
2015-08-21 07:04:50 +00:00
|
|
|
reg = tcg_target_call_iarg_regs[i];
|
2018-02-21 00:18:44 +00:00
|
|
|
tcg_reg_free(s, reg, allocated_regs);
|
2018-02-19 16:43:59 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
if (ts->val_type == TEMP_VAL_REG) {
|
|
|
|
if (ts->reg != reg) {
|
|
|
|
tcg_out_mov(s, ts->type, reg, ts->reg);
|
|
|
|
}
|
|
|
|
} else {
|
2018-03-05 04:23:28 +00:00
|
|
|
TCGRegSet arg_set = 0;
|
2018-02-19 16:43:59 +00:00
|
|
|
|
|
|
|
tcg_regset_set_reg(arg_set, reg);
|
|
|
|
temp_load(s, ts, arg_set, allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-19 16:43:59 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
tcg_regset_set_reg(allocated_regs, reg);
|
|
|
|
}
|
|
|
|
}
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* mark dead temporaries and free the associated registers */
|
2018-03-05 12:12:09 +00:00
|
|
|
for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
if (IS_DEAD_ARG(i)) {
|
2018-03-05 14:55:39 +00:00
|
|
|
temp_dead(s, arg_temp(op->args[i]));
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
2018-03-12 22:03:02 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* clobber call registers */
|
2018-03-12 22:03:02 +00:00
|
|
|
for (i = 0; i < TCG_TARGET_NB_REGS; i++) {
|
2018-02-19 16:22:12 +00:00
|
|
|
if (tcg_regset_test_reg(s->tcg_target_call_clobber_regs, i)) {
|
2018-02-21 00:18:44 +00:00
|
|
|
tcg_reg_free(s, i, allocated_regs);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Save globals if they might be written by the helper, sync them if
|
|
|
|
they might be read. */
|
|
|
|
if (flags & TCG_CALL_NO_READ_GLOBALS) {
|
|
|
|
/* Nothing to do */
|
|
|
|
} else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
|
|
|
|
sync_globals(s, allocated_regs);
|
|
|
|
} else {
|
|
|
|
save_globals(s, allocated_regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
tcg_out_call(s, func_addr);
|
|
|
|
|
|
|
|
/* assign output registers and emit moves if needed */
|
|
|
|
for(i = 0; i < nb_oargs; i++) {
|
2018-03-05 12:12:09 +00:00
|
|
|
arg = op->args[i];
|
2018-03-05 14:55:39 +00:00
|
|
|
ts = arg_temp(arg);
|
2015-08-21 07:04:50 +00:00
|
|
|
reg = tcg_target_call_oarg_regs[i];
|
2018-02-23 18:52:01 +00:00
|
|
|
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
if (ts->fixed_reg) {
|
|
|
|
if (ts->reg != reg) {
|
|
|
|
tcg_out_mov(s, ts->type, ts->reg, reg);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (ts->val_type == TEMP_VAL_REG) {
|
2018-02-19 16:30:24 +00:00
|
|
|
s->reg_to_temp[ts->reg] = NULL;
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
ts->val_type = TEMP_VAL_REG;
|
|
|
|
ts->reg = reg;
|
|
|
|
ts->mem_coherent = 0;
|
2018-02-19 16:30:24 +00:00
|
|
|
s->reg_to_temp[reg] = ts;
|
2015-08-21 07:04:50 +00:00
|
|
|
if (NEED_SYNC_ARG(i)) {
|
2018-02-25 06:41:28 +00:00
|
|
|
temp_sync(s, ts, allocated_regs, IS_DEAD_ARG(i));
|
|
|
|
} else if (IS_DEAD_ARG(i)) {
|
2018-02-19 16:34:14 +00:00
|
|
|
temp_dead(s, ts);
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
|
|
|
|
static void dump_op_count(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2018-02-09 18:20:10 +00:00
|
|
|
for(i = 0; i < NB_OPS; i++) {
|
2015-08-21 07:04:50 +00:00
|
|
|
qemu_log("%s %" PRId64 "\n", s->tcg_op_defs[i].name, tcg_table_op_count[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
2018-02-22 14:27:56 +00:00
|
|
|
int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
|
2015-08-21 07:04:50 +00:00
|
|
|
{
|
2018-03-05 21:01:13 +00:00
|
|
|
int i, num_insns;
|
|
|
|
TCGOp *op;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-16 15:18:47 +00:00
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
{
|
2018-10-23 18:37:35 +00:00
|
|
|
int n = 0;
|
2018-02-16 15:18:47 +00:00
|
|
|
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_FOREACH(op, &s->ops, link) {
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
atomic_set(&s->op_count, s->op_count + n);
|
2018-02-16 15:18:47 +00:00
|
|
|
if (n > s->op_count_max) {
|
2018-03-05 21:01:13 +00:00
|
|
|
atomic_set(&s->op_count_max, n);
|
2018-02-16 15:18:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
n = s->nb_temps;
|
2018-03-05 21:01:13 +00:00
|
|
|
atomic_set(&s->temp_count, s->temp_count + n);
|
2018-02-16 15:18:47 +00:00
|
|
|
if (n > s->temp_count_max) {
|
2018-03-05 21:01:13 +00:00
|
|
|
atomic_set(&s->temp_count_max, n);
|
2018-02-16 15:18:47 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
#ifdef DEBUG_DISAS
|
2018-02-22 15:05:12 +00:00
|
|
|
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
|
|
|
|
&& qemu_log_in_addr_range(tb->pc))) {
|
2015-08-21 07:04:50 +00:00
|
|
|
qemu_log("OP:\n");
|
|
|
|
tcg_dump_ops(s);
|
|
|
|
qemu_log("\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
s->opt_time -= profile_getclock();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef USE_TCG_OPTIMIZATIONS
|
2018-02-09 14:54:01 +00:00
|
|
|
tcg_optimize(s);
|
2015-08-21 07:04:50 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
s->opt_time += profile_getclock();
|
|
|
|
s->la_time -= profile_getclock();
|
|
|
|
#endif
|
|
|
|
|
2018-03-05 12:29:27 +00:00
|
|
|
liveness_pass_1(s);
|
2018-02-26 03:23:00 +00:00
|
|
|
|
2018-03-05 12:29:27 +00:00
|
|
|
if (s->nb_indirects > 0) {
|
2018-02-26 03:23:00 +00:00
|
|
|
#ifdef DEBUG_DISAS
|
2018-03-05 12:29:27 +00:00
|
|
|
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
|
|
|
|
&& qemu_log_in_addr_range(tb->pc))) {
|
|
|
|
qemu_log("OP before indirect lowering:\n");
|
|
|
|
tcg_dump_ops(s);
|
|
|
|
qemu_log("\n");
|
|
|
|
}
|
2018-02-26 03:23:00 +00:00
|
|
|
#endif
|
2018-03-05 12:29:27 +00:00
|
|
|
/* Replace indirect temps with direct temps. */
|
|
|
|
if (liveness_pass_2(s)) {
|
|
|
|
/* If changes were made, re-run liveness. */
|
|
|
|
liveness_pass_1(s);
|
2018-02-26 03:23:00 +00:00
|
|
|
}
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
s->la_time += profile_getclock();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef DEBUG_DISAS
|
2018-02-22 15:05:12 +00:00
|
|
|
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
|
|
|
|
&& qemu_log_in_addr_range(tb->pc))) {
|
2015-08-21 07:04:50 +00:00
|
|
|
qemu_log("OP after optimization and liveness analysis:\n");
|
|
|
|
tcg_dump_ops(s);
|
|
|
|
qemu_log("\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
tcg_reg_alloc_start(s);
|
|
|
|
|
2018-03-05 07:57:19 +00:00
|
|
|
s->code_buf = tb->tc.ptr;
|
|
|
|
s->code_ptr = tb->tc.ptr;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-03-05 03:03:22 +00:00
|
|
|
#ifdef TCG_TARGET_NEED_LDST_LABELS
|
2018-05-03 19:08:59 +00:00
|
|
|
QSIMPLEQ_INIT(&s->ldst_labels);
|
2018-03-05 03:03:22 +00:00
|
|
|
#endif
|
2018-03-05 03:17:11 +00:00
|
|
|
#ifdef TCG_TARGET_NEED_POOL_LABELS
|
|
|
|
s->pool_labels = NULL;
|
|
|
|
#endif
|
2015-08-21 07:04:50 +00:00
|
|
|
|
2018-02-16 14:45:15 +00:00
|
|
|
num_insns = -1;
|
2018-03-05 21:01:13 +00:00
|
|
|
QTAILQ_FOREACH(op, &s->ops, link) {
|
2018-02-09 14:54:01 +00:00
|
|
|
TCGOpcode opc = op->opc;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
tcg_table_op_count[opc]++;
|
|
|
|
#endif
|
2018-02-09 14:54:01 +00:00
|
|
|
switch (opc) {
|
2015-08-21 07:04:50 +00:00
|
|
|
case INDEX_op_mov_i32:
|
|
|
|
case INDEX_op_mov_i64:
|
2018-03-06 16:49:50 +00:00
|
|
|
case INDEX_op_mov_vec:
|
2018-03-05 12:12:09 +00:00
|
|
|
tcg_reg_alloc_mov(s, op);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
case INDEX_op_movi_i32:
|
|
|
|
case INDEX_op_movi_i64:
|
2018-03-06 16:49:50 +00:00
|
|
|
case INDEX_op_dupi_vec:
|
2018-03-05 12:12:09 +00:00
|
|
|
tcg_reg_alloc_movi(s, op);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
2018-02-11 17:31:22 +00:00
|
|
|
case INDEX_op_insn_start:
|
2018-02-16 14:45:15 +00:00
|
|
|
if (num_insns >= 0) {
|
|
|
|
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
|
|
|
|
}
|
|
|
|
num_insns++;
|
2018-02-16 13:12:33 +00:00
|
|
|
for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
|
|
|
|
target_ulong a;
|
|
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
2018-03-05 12:06:09 +00:00
|
|
|
a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]);
|
2018-02-16 13:12:33 +00:00
|
|
|
#else
|
2018-03-05 12:06:09 +00:00
|
|
|
a = op->args[i];
|
2018-02-16 13:12:33 +00:00
|
|
|
#endif
|
2018-02-16 14:45:15 +00:00
|
|
|
s->gen_insn_data[num_insns][i] = a;
|
2018-02-16 13:12:33 +00:00
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
case INDEX_op_discard:
|
2018-03-05 14:55:39 +00:00
|
|
|
temp_dead(s, arg_temp(op->args[0]));
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
case INDEX_op_set_label:
|
|
|
|
tcg_reg_alloc_bb_end(s, s->reserved_regs);
|
2018-03-05 12:06:09 +00:00
|
|
|
tcg_out_label(s, arg_label(s, op->args[0]), s->code_ptr);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
case INDEX_op_call:
|
2018-03-05 12:12:09 +00:00
|
|
|
tcg_reg_alloc_call(s, op);
|
2018-02-09 14:54:01 +00:00
|
|
|
break;
|
2015-08-21 07:04:50 +00:00
|
|
|
default:
|
|
|
|
/* Sanity check that we've not introduced any unhandled opcodes. */
|
2018-03-05 04:20:12 +00:00
|
|
|
tcg_debug_assert(tcg_op_supported(opc));
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Note: in order to speed up the code, it would be much
|
|
|
|
faster to have specialized register allocator functions for
|
|
|
|
some common argument patterns */
|
2018-03-05 12:12:09 +00:00
|
|
|
tcg_reg_alloc_op(s, op);
|
2015-08-21 07:04:50 +00:00
|
|
|
break;
|
|
|
|
}
|
2018-02-23 18:55:11 +00:00
|
|
|
#ifdef CONFIG_DEBUG_TCG
|
2015-08-21 07:04:50 +00:00
|
|
|
check_regs(s);
|
|
|
|
#endif
|
2018-02-16 19:26:29 +00:00
|
|
|
/* Test for (pending) buffer overflow. The assumption is that any
|
|
|
|
one operation beginning below the high water mark cannot overrun
|
|
|
|
the buffer completely. Thus we can test for overflow after
|
|
|
|
generating code without having to check during generation. */
|
2018-02-17 23:53:06 +00:00
|
|
|
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
|
2018-02-16 19:26:29 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
}
|
2018-02-16 14:45:15 +00:00
|
|
|
tcg_debug_assert(num_insns >= 0);
|
|
|
|
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
|
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* Generate TB finalization at the end of block */
|
2018-03-05 03:03:22 +00:00
|
|
|
#ifdef TCG_TARGET_NEED_LDST_LABELS
|
|
|
|
if (!tcg_out_ldst_finalize(s)) {
|
2018-02-19 06:40:12 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2018-03-05 03:03:22 +00:00
|
|
|
#endif
|
2018-03-05 03:17:11 +00:00
|
|
|
#ifdef TCG_TARGET_NEED_POOL_LABELS
|
|
|
|
if (!tcg_out_pool_finalize(s)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
#endif
|
2015-09-28 02:58:43 +00:00
|
|
|
|
2015-08-21 07:04:50 +00:00
|
|
|
/* flush instruction cache */
|
|
|
|
flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
|
|
|
|
|
|
|
|
return tcg_current_code_size(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PROFILER
|
|
|
|
void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
|
|
|
|
{
|
|
|
|
#if 0
|
|
|
|
TCGContext *s = &tcg_ctx;
|
2018-02-16 14:45:15 +00:00
|
|
|
int64_t tb_count = s->tb_count;
|
|
|
|
int64_t tb_div_count = tb_count ? tb_count : 1;
|
|
|
|
int64_t tot = s->interm_time + s->code_time;
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
|
|
|
|
tot, tot / 2.4e9);
|
|
|
|
cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
|
2018-02-16 14:45:15 +00:00
|
|
|
tb_count, s->tb_count1 - tb_count,
|
|
|
|
(double)(s->tb_count1 - s->tb_count)
|
|
|
|
/ (s->tb_count1 ? s->tb_count1 : 1) * 100.0);
|
2015-08-21 07:04:50 +00:00
|
|
|
cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
|
2018-02-16 14:45:15 +00:00
|
|
|
(double)s->op_count / tb_div_count, s->op_count_max);
|
2015-08-21 07:04:50 +00:00
|
|
|
cpu_fprintf(f, "deleted ops/TB %0.2f\n",
|
2018-02-16 14:45:15 +00:00
|
|
|
(double)s->del_op_count / tb_div_count);
|
2015-08-21 07:04:50 +00:00
|
|
|
cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
|
2018-02-16 14:45:15 +00:00
|
|
|
(double)s->temp_count / tb_div_count, s->temp_count_max);
|
|
|
|
cpu_fprintf(f, "avg host code/TB %0.1f\n",
|
|
|
|
(double)s->code_out_len / tb_div_count);
|
|
|
|
cpu_fprintf(f, "avg search data/TB %0.1f\n",
|
|
|
|
(double)s->search_out_len / tb_div_count);
|
2015-08-21 07:04:50 +00:00
|
|
|
|
|
|
|
cpu_fprintf(f, "cycles/op %0.1f\n",
|
|
|
|
s->op_count ? (double)tot / s->op_count : 0);
|
|
|
|
cpu_fprintf(f, "cycles/in byte %0.1f\n",
|
|
|
|
s->code_in_len ? (double)tot / s->code_in_len : 0);
|
|
|
|
cpu_fprintf(f, "cycles/out byte %0.1f\n",
|
|
|
|
s->code_out_len ? (double)tot / s->code_out_len : 0);
|
2018-02-16 14:45:15 +00:00
|
|
|
cpu_fprintf(f, "cycles/search byte %0.1f\n",
|
|
|
|
s->search_out_len ? (double)tot / s->search_out_len : 0);
|
|
|
|
if (tot == 0) {
|
2015-08-21 07:04:50 +00:00
|
|
|
tot = 1;
|
2018-02-16 14:45:15 +00:00
|
|
|
}
|
2015-08-21 07:04:50 +00:00
|
|
|
cpu_fprintf(f, " gen_interm time %0.1f%%\n",
|
|
|
|
(double)s->interm_time / tot * 100.0);
|
|
|
|
cpu_fprintf(f, " gen_code time %0.1f%%\n",
|
|
|
|
(double)s->code_time / tot * 100.0);
|
|
|
|
cpu_fprintf(f, "optim./code time %0.1f%%\n",
|
|
|
|
(double)s->opt_time / (s->code_time ? s->code_time : 1)
|
|
|
|
* 100.0);
|
|
|
|
cpu_fprintf(f, "liveness/code time %0.1f%%\n",
|
|
|
|
(double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
|
|
|
|
cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
|
|
|
|
s->restore_count);
|
|
|
|
cpu_fprintf(f, " avg cycles %0.1f\n",
|
|
|
|
s->restore_count ? (double)s->restore_time / s->restore_count : 0);
|
|
|
|
|
|
|
|
dump_op_count();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
|
|
|
|
{
|
|
|
|
cpu_fprintf(f, "[TCG profiler not compiled]\n");
|
|
|
|
}
|
|
|
|
#endif
|
2018-03-06 17:19:54 +00:00
|
|
|
|
|
|
|
#if !TCG_TARGET_MAYBE_vec
|
2018-03-06 18:45:25 +00:00
|
|
|
void tcg_expand_vec_op(TCGContext *s, TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...)
|
2018-03-06 17:19:54 +00:00
|
|
|
{
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
#endif
|