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unicorn/qemu/target/riscv/cpu.h

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target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
/*
* QEMU RISC-V CPU
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017-2018 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef RISCV_CPU_H
#define RISCV_CPU_H
#include "config.h"
#include "qemu-common.h"
#include "qom/cpu.h"
#include "exec/cpu-defs.h"
target/riscv: rationalise softfloat includes We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h and -helpers.h in cpu.h for the few bits that are global. Backports commit 135b03cb9defbd080b8834b30e3d45bed00c6137 from qemu
2019-11-19 02:17:02 +00:00
#include "fpu/softfloat-types.h"
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
tcg: Split out target/arch/cpu-param.h For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Backports commit 74433bf083b0766aba81534f92de13194f23ff3e from qemu
2019-06-10 23:15:41 +00:00
#define TCG_GUEST_DEFAULT_MO 0
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#define TYPE_RISCV_CPU "riscv-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
target/riscv: Add a base 32 and 64 bit CPU At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Backports commit 8903bf6e6d73d03b988b4a8197132de2ad681ff5 from qemu
2019-05-28 23:11:04 +00:00
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
target/riscv: Restructure deprecatd CPUs Restructure the deprecated CPUs to make it clear in the code that these are depreated. They are already marked as deprecated in qemu-deprecated.texi. There are no functional changes. Backports commit c1fb65e63cfca4506a14b084afd0eca2dc464fe8 from qemu
2019-08-08 20:59:58 +00:00
/* Deprecated */
#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
#if defined(TARGET_RISCV32)
#define RVXLEN RV32
#elif defined(TARGET_RISCV64)
#define RVXLEN RV64
#endif
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RVI RV('I')
#define RVE RV('E') /* E and I are mutually exclusive */
#define RVM RV('M')
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
target/riscv: Add the Hypervisor extension Backports commit af1fa0039c799a350bcde07b3d8a71dfde07d11b from qemu
2020-03-22 05:01:06 +00:00
#define RVH RV('H')
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
is currently no bit in misa to indicate whether an MMU exists or not
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_MISA
};
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
target/riscv: Add the privledge spec version 1.11.0 Add support for the ratified RISC-V privledge spec. Backports commit 6729dbbd420696fcf69cf2c86bdfc66e072058ce from qemu
2019-08-08 21:03:29 +00:00
#define PRIV_VERSION_1_11_0 0x00011100
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
RISC-V: Check PMP during Page Table Walks The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Backports commit 1f447aec787bfbbd078afccae44fc4c92acb4fed from qemu
2019-08-08 20:54:43 +00:00
#define TRANSLATE_PMP_FAIL 2
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
target/riscv: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu
2019-06-12 15:58:56 +00:00
typedef struct CPURISCVState CPURISCVState;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#include "pmp.h"
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
target_ulong pc;
target_ulong load_res;
target_ulong load_val;
target_ulong frm;
target_ulong badaddr;
target/riscv: Implement second stage MMU Backports commit 36a18664bafcfafa5e997b47458387f6fe53d537 from qemu
2020-03-22 06:04:48 +00:00
target_ulong guest_phys_fault_addr;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
target_ulong priv_ver;
target_ulong misa;
target_ulong misa_mask;
uint32_t features;
RISC-V: linux-user support for RVE ABI This change checks elf_flags for EF_RISCV_RVE and if present uses the RVE linux syscall ABI which uses t0 for the syscall number instead of a7. Warn and exit if a non-RVE ABI binary is run on a cpu with the RVE extension as it is incompatible. Backports relevant parts of 5836c3eccedb6dfab16b8f606f2de24b8938b69c from qemu
2019-03-20 03:56:43 +00:00
#ifdef CONFIG_USER_ONLY
uint32_t elf_flags;
#endif
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#ifndef CONFIG_USER_ONLY
target_ulong priv;
target/riscv: Add the virtulisation mode Backports commit ef6bb7b62682badefdcb744831510aaa5971684f from qemu
2020-03-22 05:12:41 +00:00
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
target_ulong resetvec;
target_ulong mhartid;
target_ulong mstatus;
/*
* CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
* by I/O threads. It should be read with atomic_read. It should be updated
* using riscv_cpu_update_mip with the iothread mutex held. The iothread
* mutex must be held because mip must be consistent with the CPU inturrept
* state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
* wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
* mip is 32-bits to allow atomic_read on 32-bit hosts.
*/
target/riscv: Convert MIP CSR to target_ulong The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. Now that we don't use atomics for MIP we can change this back to a xlen CSR. Backports commit 028616130d5f0abc8a3b96f28963da51a875024b from qemu
2020-03-22 04:59:35 +00:00
target_ulong mip;
target/riscv: Add virtual register swapping function Backports commit 66e594f2800ddc55f908830bf9e8dc4cda1304fe from qemu
2020-03-22 05:29:35 +00:00
target/riscv: Add support for the 32-bit MSTATUSH CSR Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu
2020-03-22 06:16:10 +00:00
#ifdef TARGET_RISCV32
target_ulong mstatush;
#endif
RISC-V: Allow interrupt controllers to claim interrupts We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu
2019-03-20 03:47:35 +00:00
uint32_t miclaim;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
target_ulong mie;
target_ulong mideleg;
target_ulong sptbr; /* until: priv-1.9.1 */
target_ulong satp; /* since: priv-1.10.0 */
target_ulong sbadaddr;
target_ulong mbadaddr;
target_ulong medeleg;
target_ulong stvec;
target_ulong sepc;
target_ulong scause;
target_ulong mtvec;
target_ulong mepc;
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
target/riscv: Add the Hypervisor CSRs to CPUState Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Backports commit bd023ce33b85d73791b7bc78fd04a8115c60995e from qemu
2020-03-22 05:05:20 +00:00
/* Hypervisor CSRs */
target_ulong hstatus;
target_ulong hedeleg;
target_ulong hideleg;
target_ulong hcounteren;
target_ulong htval;
target_ulong htinst;
target_ulong hgatp;
target/riscv: Emulate TIME CSRs for privileged mode Currently, TIME CSRs are emulated only for user-only mode. This patch add TIME CSRs emulation for privileged mode. For privileged mode, the TIME CSRs will return value provided by rdtime callback which is registered by QEMU machine/platform emulation (i.e. CLINT emulation). If rdtime callback is not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu
2020-03-22 06:21:27 +00:00
uint64_t htimedelta;
target/riscv: Add the Hypervisor CSRs to CPUState Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Backports commit bd023ce33b85d73791b7bc78fd04a8115c60995e from qemu
2020-03-22 05:05:20 +00:00
/* Virtual CSRs */
target_ulong vsstatus;
target_ulong vstvec;
target_ulong vsscratch;
target_ulong vsepc;
target_ulong vscause;
target_ulong vstval;
target_ulong vsatp;
target/riscv: Add support for the 32-bit MSTATUSH CSR Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu
2020-03-22 06:16:10 +00:00
#ifdef TARGET_RISCV32
target_ulong vsstatush;
#endif
target/riscv: Add the Hypervisor CSRs to CPUState Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Backports commit bd023ce33b85d73791b7bc78fd04a8115c60995e from qemu
2020-03-22 05:05:20 +00:00
target_ulong mtval2;
target_ulong mtinst;
target/riscv: Add virtual register swapping function Backports commit 66e594f2800ddc55f908830bf9e8dc4cda1304fe from qemu
2020-03-22 05:29:35 +00:00
/* HS Backup CSRs */
target_ulong stvec_hs;
target_ulong sscratch_hs;
target_ulong sepc_hs;
target_ulong scause_hs;
target_ulong stval_hs;
target_ulong satp_hs;
target_ulong mstatus_hs;
target/riscv: Add support for the 32-bit MSTATUSH CSR Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu
2020-03-22 06:16:10 +00:00
#ifdef TARGET_RISCV32
target_ulong mstatush_hs;
#endif
target/riscv: Add virtual register swapping function Backports commit 66e594f2800ddc55f908830bf9e8dc4cda1304fe from qemu
2020-03-22 05:29:35 +00:00
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
target_ulong scounteren;
target_ulong mcounteren;
target_ulong sscratch;
target_ulong mscratch;
/* temporary htif regs */
uint64_t mfromhost;
uint64_t mtohost;
uint64_t timecmp;
/* physical memory protection */
pmp_table_t pmp_state;
RISC-V: Add debug support for accessing CSRs. Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
2019-03-20 03:42:44 +00:00
target/riscv: Emulate TIME CSRs for privileged mode Currently, TIME CSRs are emulated only for user-only mode. This patch add TIME CSRs emulation for privileged mode. For privileged mode, the TIME CSRs will return value provided by rdtime callback which is registered by QEMU machine/platform emulation (i.e. CLINT emulation). If rdtime callback is not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu
2020-03-22 06:21:27 +00:00
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void);
RISC-V: Add debug support for accessing CSRs. Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
2019-03-20 03:42:44 +00:00
/* True if in debugger mode. */
bool debugger;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#endif
float_status fp_status;
/* QEMU */
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */
// Unicorn engine
struct uc_struct *uc;
};
#define RISCV_CPU_CLASS(uc, klass) \
OBJECT_CLASS_CHECK(uc, RISCVCPUClass, (klass), TYPE_RISCV_CPU)
#define RISCV_CPU(uc, obj) \
((RISCVCPU*)obj)
#define RISCV_CPU_GET_CLASS(uc, obj) \
OBJECT_GET_CLASS(uc, RISCVCPUClass, (obj), TYPE_RISCV_CPU)
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A RISCV CPU model.
*/
typedef struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} RISCVCPUClass;
/**
* RISCVCPU:
* @env: #CPURISCVState
*
* A RISCV CPU.
*/
typedef struct RISCVCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
cpu: Introduce CPUNegativeOffsetState Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Backports commit 5b146dc716cfd247f99556c04e6e46fbd67565a0 from qemu
2019-06-13 19:05:34 +00:00
CPUNegativeOffsetState neg;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
CPURISCVState env;
RISC-V: Add support for the Zifencei extension fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Backports commit 50fba816cd226001bec3e495c39879deb2fa5432 from qemu
2019-08-08 21:09:00 +00:00
struct {
bool ext_ifencei;
RISC-V: Add support for the Zicsr extension The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Backports commit 591bddea8d874e1500921de0353818e5586618f5 from qemu
2019-08-08 21:10:32 +00:00
bool ext_icsr;
RISC-V: Add support for the Zifencei extension fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Backports commit 50fba816cd226001bec3e495c39879deb2fa5432 from qemu
2019-08-08 21:09:00 +00:00
} cfg;
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
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} RISCVCPU;
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
return (env->misa & ext) != 0;
}
static inline bool riscv_feature(CPURISCVState *env, int feature)
{
return env->features & (1ULL << feature);
}
#include "cpu_user.h"
#include "cpu_bits.h"
extern const char * const riscv_int_regnames[];
extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
target/riscv: Disable guest FP support based on virtual status When the Hypervisor extension is in use we only enable floating point support when both status and vsstatus have enabled floating point support. Backports commit 29409c1d921d607873268671bf11a088efb5558e from qemu
2020-03-22 05:49:03 +00:00
bool riscv_cpu_fp_enabled(CPURISCVState *env);
target/riscv: Add the virtulisation mode Backports commit ef6bb7b62682badefdcb744831510aaa5971684f from qemu
2020-03-22 05:12:41 +00:00
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
target/riscv: Add the force HS exception mode Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when handling interrupts. Backports commit c7b1bbc80fc2af17395d3986c346fd2307e57829 from qemu
2020-03-22 05:16:43 +00:00
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
target/riscv: Convert to CPUClass::tlb_fill Note that env->pc is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from riscv_raise_exception. Backports commit 8a4ca3c10a96be6ed7f023b685b688c4d409bbcb from qemu
2019-05-16 21:23:42 +00:00
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
target/riscv: Implement riscv_cpu_unassigned_access This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Backports commit cbf5827693addaff4e4d2102afedbf078a204eb2 from qemu
2019-08-08 20:45:11 +00:00
void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
bool is_exec, int unused, unsigned size);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler riscv_cpu_signal_handler
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
target/riscv: Add virtual register swapping function Backports commit 66e594f2800ddc55f908830bf9e8dc4cda1304fe from qemu
2020-03-22 05:29:35 +00:00
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
RISC-V: Allow interrupt controllers to claim interrupts We can't allow the supervisor to control SEIP as this would allow the supervisor to clear a pending external interrupt which will result in lost a interrupt in the case a PLIC is attached. The SEIP bit must be hardware controlled when a PLIC is attached. This logic was previously hard-coded so SEIP was always masked even if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts so that the PLIC can register control of SEIP. In the case of models without a PLIC (spike), the SEIP bit remains software controlled. This interface allows for hardware control of supervisor timer and software interrupts by other interrupt controller models. Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu
2019-03-20 03:47:35 +00:00
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
target/riscv: Emulate TIME CSRs for privileged mode Currently, TIME CSRs are emulated only for user-only mode. This patch add TIME CSRs emulation for privileged mode. For privileged mode, the TIME CSRs will return value provided by rdtime callback which is registered by QEMU machine/platform emulation (i.e. CLINT emulation). If rdtime callback is not available then the monitor (i.e. OpenSBI) will trap-n-emulate TIME CSRs in software. We see 25+% performance improvement in hackbench numbers when TIME CSRs are not trap-n-emulated. Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu
2020-03-22 06:21:27 +00:00
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
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#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(struct uc_struct *uc);
int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc);
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
*pc = env->pc;
*cs_base = 0;
#ifdef CONFIG_USER_ONLY
*flags = TB_FLAGS_MSTATUS_FS;
#else
target/riscv: Only set TB flags with FP status if enabled Backports commit e28eaed87902c5e852c3ed043b27204e879aa4e2 from qemu
2020-03-22 05:45:30 +00:00
*flags = cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
*flags |= env->mstatus & MSTATUS_FS;
}
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
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#endif
}
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
RISC-V: Add debug support for accessing CSRs. Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
2019-03-20 03:42:44 +00:00
int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val)
{
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
}
static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
target_ulong val = 0;
riscv_csrrw(env, csrno, &val, 0, 0);
return val;
}
typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
target_ulong *ret_value);
typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
target_ulong new_value);
typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
typedef struct {
riscv_csr_predicate_fn predicate;
riscv_csr_read_fn read;
riscv_csr_write_fn write;
riscv_csr_op_fn op;
} riscv_csr_operations;
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
cpu: Define CPUArchState with typedef For all targets, do this just before including exec/cpu-all.h. Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu
2019-06-12 15:06:27 +00:00
typedef CPURISCVState CPUArchState;
cpu: Define ArchCPU For all targets, do this just before including exec/cpu-all.h. Backports commit 2161a612b4e1d388046320bc464adefd6bba01a0 from qemu
2019-06-12 15:08:38 +00:00
typedef RISCVCPU ArchCPU;
cpu: Define CPUArchState with typedef For all targets, do this just before including exec/cpu-all.h. Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu
2019-06-12 15:06:27 +00:00
target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.
2019-03-08 18:06:28 +00:00
#include "exec/cpu-all.h"
// Unicorn-specific
void riscv_cpu_register_types(void *opaque);
#endif /* RISCV_CPU_H */
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