Commit graph

275 commits

Author SHA1 Message Date
Aleksandar Markovic e2bc3161b4
target/mips: Fix emulation of MSA pack instructions on big endian hosts
Fix emulation of MSA pack instructions on big endian hosts.

Backports commit 51229582583a4b64e93f2655153d905e4d8583d2 from qemu
2019-08-08 19:51:34 -04:00
Aleksandar Markovic 812f3e4fed
target/mips: Add 'fall through' comments for handling nanoMips' SHXS, SWXS
This was found by GCC 8.3 static analysis.

Missed in commit fb32f8c8560.

Backports commit 45152d050213a1221a5a900283976454bf6308bf from qemu
2019-08-08 19:45:25 -04:00
Aleksandar Markovic 572c95e709
target/mips: Add missing 'break' for certain cases of MTTR handling
This was found by GCC 8.3 static analysis.

Fixes: ead9360e2fb

Backports commit 0d0304f2c4967c892a3216638fc4cb078afa2b44 from qemu
2019-08-08 19:38:18 -04:00
Aleksandar Markovic 720aff63da
target/mips: Add missing 'break' for certain cases of MFTR handling
This was found by GCC 8.3 static analysis.

Fixes: ead9360e2fb

Backports commit f1fadbb27af04115c9d24e0902d88a38d0266854 from qemu
2019-08-08 19:37:34 -04:00
Aleksandar Markovic b2aa75be33
target/mips: Add missing 'break' for a case of MTHC0 handling
This was found by GCC 8.3 static analysis.

Fixes: 5fb2dcd1792

Backports commit ab8c34105a0ddd0c05159fb76919a18de8df4e8f from qemu
2019-08-08 19:36:39 -04:00
Aleksandar Markovic 1e148beb0e
target/mips: Correct helper for MSA FCLASS.<W|D> instructions
Correct helper for MSA FCLASS.<W|D> instructions.

Backports commit 698c5752c4e618dc17b4c78dfa566896c7bce5ef from qemu
2019-08-08 16:30:15 -04:00
Aleksandar Markovic bf194f980c
target/mips: Unroll loops for MSA float max/min instructions
Slight preformance improvement for MSA float max/min instructions.

Backports commit 807e6773a5eba62054843b13d96ff778b90aba09 from qemu
2019-08-08 16:28:49 -04:00
Aleksandar Markovic dd747162e5
target/mips: Correct comments in msa_helper.c
Fix some errors in comments for MSA helpers.

Backports commit 44da090ba02e60515aa0dc72b30ecc6f56aea771 from qemu
2019-08-08 16:24:47 -04:00
Aleksandar Markovic 87edd2a82a
target/mips: Correct comments in translate.c
Fix some checkpatch comment-related warnings.

Backports commit 7480515fcc1b0f7119953d89e93b8507127aeb62 from qemu
2019-08-08 16:23:02 -04:00
Aleksandar Markovic 977e53b921
target/mips: Fix emulation of ILVR.<B|H|W> on big endian host
Fix emulation of ILVR.<B|H|W> on big endian host by applying
mapping of data element indexes from one endian to another.

Backports commit 14f5d874bcd533054648bb7cc767c7169eaf2f1c from qemu
2019-06-30 20:03:23 -04:00
Aleksandar Markovic f7fc20c9ee
target/mips: Fix emulation of ILVL.<B|H|W> on big endian host
Fix emulation of ILVL.<B|H|W> on big endian host by applying
mapping of data element indexes from one endian to another.

Backports commit 8e74bceb00120b23f0931e4e4478d1b10e0970d4 from qemu
2019-06-30 20:02:12 -04:00
Aleksandar Markovic 929bd90968
target/mips: Fix emulation of ILVOD.<B|H|W> on big endian host
Fix emulation of ILVOD.<B|H|W> on big endian host by applying
mapping of data element indexes from one endian to another.

Backports commit b000169e4ed44a3925b6fd22fa0dd6e22bb02b81 from qemu
2019-06-30 19:54:35 -04:00
Aleksandar Markovic 17dd65b771
target/mips: Fix emulation of ILVEV.<B|H|W> on big endian host
Fix emulation of ILVEV.<B|H|W> on big endian host by applying
mapping of data element indexes from one endian to another.

Backports commit 98880cb5a669a35b5bc75432027f2b9fff566aea from qemu
2019-06-30 19:52:14 -04:00
Aleksandar Markovic e9dc22c280
target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c
Remove if-else-switch-case-arms-related checkpatch errors.

Backports commit 1f8929d241c5461f3e98d52f54bcdadd35554448 from qemu
2019-06-30 19:42:16 -04:00
Aleksandar Markovic 1e52cb8fa1
target/mips: Fix some space checkpatch errors in translate.c
Remove some space-related checkpatch warning.

Backports commit 235785e8347558f36be21aa99efa1ba517ecc827 from qemu
2019-06-30 19:34:41 -04:00
Richard Henderson 8f53f09a05
cpu: Introduce CPUNegativeOffsetState
Nothing in there so far, but all of the plumbing done
within the target ArchCPU state.

Backports commit 5b146dc716cfd247f99556c04e6e46fbd67565a0 from qemu
2019-06-13 15:08:25 -04:00
Richard Henderson a672b89e3b
cpu: Introduce cpu_set_cpustate_pointers
Consolidate some boilerplate from foo_cpu_initfn.

Backports commit 7506ed902eb97fe4e2a1dd16766c621d32ecc40d from qemu
2019-06-12 12:27:16 -04:00
Richard Henderson ac176ccb38
cpu: Move ENV_OFFSET to exec/gen-icount.h
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.

Backports commit 677c4d69ac21961e76a386f9bfc892a44923acc0 from qemu
2019-06-12 12:20:21 -04:00
Richard Henderson 5790c1648d
target/mips: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace mips_env_get_cpu with env_archcpu. The combination
CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Backports commit 5a7330b35cabc9e2fd3a8577b7004b63af8c57f3 from qemu
2019-06-12 11:55:43 -04:00
Richard Henderson fbf91a6535
cpu: Replace ENV_GET_CPU with env_cpu
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.

Backports commit 29a0af618ddd21f55df5753c3e16b0625f534b3c from qemu
2019-06-12 11:16:16 -04:00
Richard Henderson ae94fb5992
cpu: Define ArchCPU
For all targets, do this just before including exec/cpu-all.h.

Backports commit 2161a612b4e1d388046320bc464adefd6bba01a0 from qemu
2019-06-12 11:08:39 -04:00
Richard Henderson e3f1f25996
cpu: Define CPUArchState with typedef
For all targets, do this just before including exec/cpu-all.h.

Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu
2019-06-12 11:06:36 -04:00
Richard Henderson df2a890bd7
tcg: Split out target/arch/cpu-param.h
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.

Include this new file from exec/cpu-defs.h.

This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the
bulk of the includes within target/arch/cpu.h to the top.

Backports commit 74433bf083b0766aba81534f92de13194f23ff3e from qemu
2019-06-10 19:35:46 -04:00
Aleksandar Markovic 93473b2e09
target/mips: Unroll loops in helpers for MSA logic instructions
Unroll loops in helpers for MSA logic instructions for better
performance.

Backports commit 5d161bc81877327bc0b2a6d8974e07ffdc6881a5 from qemu
2019-06-10 13:56:04 -04:00
Aleksandar Markovic 8ec1ab6807
target/mips: Outline places for future MSA helpers
Outline places for future MSA helpers to follow the same organization
as in MSA tests.

Backports commit 7471df9f9eaca7c4495d77265864d56644a08b23 from qemu
2019-06-10 13:55:12 -04:00
Aleksandar Markovic 10b0f86caf
target/mips: Fix block-comment-related issues in msa_helper.c
Fix block-comment-related issues reported by checkpatch for file
msa_helper.c.

Backports commit 7cc8a7220de39d77894edcb376378f280ec9c4c2 from qemu
2019-06-10 13:53:45 -04:00
Aleksandar Markovic b9d8008931
target/mips: Fix space-related format issues in msa_helper.c
Fix space-related format issues reported by checkpatch in file
msa_helper.c.

Backports commit de1700d316c18edcca0d5264b69863edb8c9bf0d from qemu
2019-06-10 13:52:04 -04:00
Mateja Marjanovic c356f78e89
target/mips: Improve performance of certain MSA instructions
Eliminate loops for better performance.

Following MSA instructions from "UNOP" group are affected:

- NLZC.<B|H|W|D>
- NLOC.<B|H|W|D>
- PCNT.<B|H|W|D>

Following MSA instructions from "BINOP" group are affected:

- ADD_A.<B|H|W|D>
- ADDS_A.<B|H|W|D>
- ADDS_S.<B|H|W|D>
- ADDS_U.<B|H|W|D>
- ADDV.<B|H|W|D>
- ASUB_S.<B|H|W|D>
- ASUB_U.<B|H|W|D>
- AVE_S.<B|H|W|D>
- AVE_U.<B|H|W|D>
- AVER_S.<B|H|W|D>
- AVER_U.<B|H|W|D>
- BCLR.<B|H|W|D>
- BNEG.<B|H|W|D>
- BSET.<B|H|W|D>
- CEQ.<B|H|W|D>
- CLE_S.<B|H|W|D>
- CLE_U.<B|H|W|D>
- CLT_S.<B|H|W|D>
- CLT_U.<B|H|W|D>
- DIV_S.<B|H|W|D>
- DIV_U.<B|H|W|D>
- DOTP_S.<B|H|W|D>
- DOTP_U.<B|H|W|D>
- HADD_S.<B|H|W|D>
- HADD_U.<B|H|W|D>
- HSUB_S.<B|H|W|D>
- HSUB_U.<B|H|W|D>
- MAX_A.<B|H|W|D>
- MAX_S.<B|H|W|D>
- MAX_U.<B|H|W|D>
- MIN_A.<B|H|W|D>
- MIN_S.<B|H|W|D>
- MIN_U.<B|H|W|D>
- MOD_S.<B|H|W|D>
- MOD_U.<B|H|W|D>
- MUL_Q.<B|H|W|D>
- MULR_Q.<B|H|W|D>
- MULV.<B|H|W|D>
- SLL.<B|H|W|D>
- SRA.<B|H|W|D>
- SRAR.<B|H|W|D>
- SRL.<B|H|W|D>
- SRLR.<B|H|W|D>
- SUBS_S.<B|H|W|D>
- SUBS_U.<B|H|W|D>
- SUBSUS_U.<B|H|W|D>
- SUBSUU_S.<B|H|W|D>
- SUBV.<B|H|W|D>

Following MSA instructions from "TEROP" group are affected:

- BINSL.<B|H|W|D>
- BINSR.<B|H|W|D>
- DPADD_S.<B|H|W|D>
- DPADD_U.<B|H|W|D>
- DPSUB_S.<B|H|W|D>
- DPSUB_U.<B|H|W|D>
- MADD_Q.<B|H|W|D>
- MADDR_Q.<B|H|W|D>
- MADDV.<B|H|W|D>
- MSUB_Q.<B|H|W|D>
- MSUBR_Q.<B|H|W|D>
- MSUBV.<B|H|W|D>

Additionally, following MSA instructionas are also affected:

- ILVL.<B|H|W|D>
- ILVR.<B|H|W|D>
- ILVEV.<B|H|W|D>
- ILVOD.<B|H|W|D>
- PCKEV.<B|H|W|D>
- PCKOD.<B|H|W|D>

Backports commit 0df911fd7f482b796c9f10aa8e086fb3fb9f0f18 from qemu
2019-06-03 11:21:05 -04:00
Aleksandar Markovic 115e0f20c5
target/mips: Clean up lmi_helper.c
Remove several minor checkpatch warnings and errors.

Backports commit baf50011157bf5747c623f171f93f9e3d9dff615 from qemu
2019-06-03 11:15:34 -04:00
Aleksandar Markovic 1c8614c303
target/mips: Clean up dsp_helper.c
Remove several minor checkpatch warnings and errors.

Backports commit f49ab2e1e6ca4f218cc970c937f91f9c69c95dd3 from qemu
2019-06-03 11:14:31 -04:00
Mateja Marjanovic 4b272cbe93
target/mips: Add emulation of MMI instruction PCPYUD
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Backports commit fd487f83ea92d790559813c5a0a719c30ca9ecde from qemu
2019-06-03 11:08:37 -04:00
Mateja Marjanovic c5e3fc601c
target/mips: Add emulation of MMI instruction PCPYLD
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Backports commit b87eef31f2f8047077d79c3180e9c8e762d2a50f from qemu
2019-06-03 11:05:50 -04:00
Mateja Marjanovic 7443387030
target/mips: Add emulation of MMI instruction PCPYH
Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Backports commit d3434d9f785ddaf40e0fd521ded400643ac4be09 from qemu
2019-06-03 11:03:07 -04:00
Jules Irenge 9c7f2f2e78
target/mips: realign comments to fix checkpatch warnings
Realign comments to fix warnings issued by checkpatc.pl tool
"WARNING: Block comments use a leading /* on a separate line"
within "target/mips/cpu.h" file.

Backports commit 9e72f33d854b0a817c0d2fe4bca693b76f0fe776 from qemu
2019-05-28 19:49:59 -04:00
Jules Irenge cf39970750
target/mips: add or remove space to fix checkpatch errors
Add or remove space to fix errors issued by checkpatch.pl tool
"ERROR: spaces required around that..."
"ERROR: space required after that..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that..."
"ERROR: space prohibited between function name and open parenthesis"
"ERROR: code indent should never use tabs"
"ERROR: line over 90 characters"
within "target/mips/cpu.h" file.

Backports commit 8ebf2e1a68408068c0bcd0d02a783fd12f6a9cb5 from qemu
2019-05-28 19:48:11 -04:00
Jakub Jermář 5b25eb80af
mips: Decide to map PAGE_EXEC in map_address
This commit addresses QEMU Bug #1825311:

mips_cpu_handle_mmu_fault renders all accessed pages executable

It allows finer-grained control over whether the accessed page should
be executable by moving the decision to the underlying map_address
function, which has more information for this.

As a result, pages that have the XI bit set in the TLB and are accessed
for read/write, don't suddenly end up being executable.

Fixes: https://bugs.launchpad.net/qemu/+bug/1825311
Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry')

Backports commit 7353113fa482e697a77575086a41f429a01f8dc0 from qemu
2019-05-28 19:44:28 -04:00
Mateja Marjanovic 9e8aed043e
target/mips: Refactor and fix INSERT.<B|H|W|D> instructions
The old version of the helper for the INSERT.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Backports commit c1c9a10fb1f7a6782711817c167a2c20b000fc12 from qemu
2019-05-28 19:42:28 -04:00
Mateja Marjanovic d6a8d25015
target/mips: Refactor and fix COPY_U.<B|H|W> instructions
The old version of the helper for the COPY_U.<B|H|W> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Backports commit 41d288582782cf8d63241ecb6efa1e4160fe78f7 from qemu
2019-05-28 19:39:22 -04:00
Mateja Marjanovic 54a33d1db3
target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Backports commit 631c467461496dcf6d6a3e4c3d27a1433e96868e from qemu
2019-05-28 19:36:14 -04:00
Mateja Marjanovic 6dd651af3a
target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
Fix the case when the host is a big endian machine, and change
the approach toward ST.<B|H|W|D> instruction helpers.

Backports commit 6decc572dcedbf298ae30f8213b39c8b842a595a from qemu
2019-05-28 19:29:27 -04:00
Mateja Marjanovic 3ee6295d7f
target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
Fix the case when the host is a big endian machine, and change
the approach toward LD.<B|H|W|D> instruction helpers.

Backports commit 83be6b54123a8f3c529554139f1d1e43356edf8d from qemu
2019-05-28 19:27:05 -04:00
Mateja Marjanovic 1527b25428
target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware
MSA instructions MOD_<U|S>.<B|H|W|D> when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 255, 256).

[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module, Revision 1.12

Backports commit cf122bf8d2732d5d8647901ebaea596668aaaa3a from qemu
2019-05-28 19:25:00 -04:00
Mateja Marjanovic d712d3f226
target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware
MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 141, 142).

[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module, Revision 1.12

Backports commit d2a40a5f6938f30f44b536e997e1e89bb62b971c from qemu
2019-05-28 19:24:26 -04:00
Richard Henderson dab0061a0d
tcg: Use CPUClass::tlb_fill in cputlb.c
We can now use the CPUClass hook instead of a named function.

Create a static tlb_fill function to avoid other changes within
cputlb.c. This also isolates the asserts within. Remove the
named tlb_fill function from all of the targets.

Backports commit c319dc13579a92937bffe02ad2c9f1a550e73973 from qemu
2019-05-16 17:35:37 -04:00
Richard Henderson 14d48974a4
target/mips: Convert to CPUClass::tlb_fill
Note that env->active_tc.PC is removed from the qemu_log as that value
is garbage. The PC isn't recovered until cpu_restore_state, called from
cpu_loop_exit_restore, called from do_raise_exception_err.

Backports commit 931d019f5b2e7bbacb162869497123be402ddd86 from qemu
2019-05-16 17:19:47 -04:00
Richard Henderson 49cb8cfe5b
target/mips: Tidy control flow in mips_cpu_handle_mmu_fault
Since the only non-negative TLBRET_* value is TLBRET_MATCH,
the subsequent test for ret < 0 is useless. Use early return
to allow subsequent blocks to be unindented.

Backports commit e38f4eb63020075432cb77bf48398187809cf4a3 from qemu
2019-05-16 17:15:33 -04:00
Richard Henderson f175e89ca2
target/mips: Pass a valid error to raise_mmu_exception for user-only
At present we give ret = 0, or TLBRET_MATCH. This gets matched
by the default case, which falls through to TLBRET_BADADDR.
However, it makes more sense to use a proper value. All of the
tlb-related exceptions are handled identically in cpu_loop.c,
so TLBRET_BADADDR is as good as any other. Retain it.

Backports commit 995ffde9622c01f5b307cab47f9bd7962ac09db2 from qemu
2019-05-16 17:14:02 -04:00
Richard Henderson bca82cde84
tcg: Hoist max_insns computation to tb_gen_code
In order to handle TB's that translate to too much code, we
need to place the control of the length of the translation
in the hands of the code gen master loop.

Backports commit 8b86d6d25807e13a63ab6ea879f976b9f18cc45a from qemu
2019-04-30 09:49:57 -04:00
Lioncash d844d7cc9d
exec: Backport tb_cflags accessor 2019-04-22 06:12:59 -04:00
Lioncash 1ddbb253e2
target/mips: Restore Qemu's organization of CPU definitions
Like 5075a0158a, this restores Qemu's
formatting of the processor tables to make it significantly less
annoying to maintain.
2019-03-08 01:40:50 -05:00