Commit graph

3773 commits

Author SHA1 Message Date
Emilio G. Cota 9f08fb35bc
softfloat: remove float64_trunc_to_int
It has not had users since f83311e476 ("target-m68k: use floatx80
internally", 2017-06-21).

Note that no other bit-width has floatX_trunc_to_int.

Backports commit c953da8f0be5e026d1c9128660736d72294feb3e from qemu
2018-10-08 14:15:11 -04:00
Marc-André Lureau df8790284f
qom/object: register 'type' property as class property
Let's save a few byte in each object instance.

Backports commit 7439a036d58f0def85751d6d4d3232461a35ebee from qemu
2018-10-08 14:14:45 -04:00
Lioncash cc3d618e61
tcg: Remove unnecessary MSVC ifdef
All relevant arrays have at least one member in them now, making this
unnecessary.
2018-10-06 05:08:17 -04:00
Catena cyber 4199ce83bb
Removes accessible assert
Backports commit 333bfdf65e55bcf6e3b03526a50f8c43aa6d4ca5 from qemu
2018-10-06 05:02:20 -04:00
Catena cyber 2c9b6df879
Mips undefined shift fix
Backports commit 46999575fb9e82ccd925e835d0d7db47200e010d from unicorn
2018-10-06 05:00:27 -04:00
Catena cyber e3b8ea18bf
Prevents abort with m68K
* Prevents abort with m68K

Raises exception instead

* M68K remove one uses of abort

* Less aborts and logs instead for M68K

Backports commit 910999d3969b682d8376db1266f9885866cd785c from unicorn
2018-10-06 04:59:11 -04:00
Catena cyber 43c48b72ea
Initializes i386 prefix value
Backports commit 4a86318cf45b7f0b8e01748ce700de1b7688d1e3 from unicorn
2018-10-06 04:57:06 -04:00
Catena cyber 6bcc61f082
Sparc increase ttl number
Backports commit b8df0675145c592da3777395f23b4ee91c09b46c from unicorn
2018-10-06 04:55:52 -04:00
Lioncash b62e892b20
mips: Use DisasContext for parameters in place of TCGContext where applicable
This is more future-friendly with qemu's main repo, as it's more
generic.
2018-10-06 04:37:28 -04:00
Lioncash 47b45f1bc2
arm: Take DisasContext as a parameter instead of TCGContext where applicable
This is more future-friendly with qemu, as it's more generic.
2018-10-06 04:17:12 -04:00
Lioncash 766c70f608
arm: Move cpu_M0 to DisasContext 2018-10-06 03:32:39 -04:00
Lioncash 787fd448b1
arm: Move cpu_V1 to DisasContext 2018-10-06 03:28:42 -04:00
Lioncash 1aa20da917
arm: Move cpu_V0 to DisasContext 2018-10-06 03:26:52 -04:00
Lioncash 06c21baaa4
arm: Move cpu_F1d to DisasContext 2018-10-06 03:11:54 -04:00
Lioncash 5f3dd68f9c
arm: Move cpu_F0d to DisasContext 2018-10-06 03:07:42 -04:00
Lioncash e457ce8ccc
arm: Move cpu_F1s to DisasContext 2018-10-06 03:02:06 -04:00
Lioncash a4f23de55f
arm: Move cpu_F0 to DisasContext
Decreases the size of the TCGContext struct for targets that don't need
to use this variable.
2018-10-06 02:58:11 -04:00
Lioncash 97a5955a2a
tcg: Remove leftover unused variable from TCGContext
This was previously used by the i386 target, however all of the locals
were moved to the DisasContext struct, leaving this unused.
2018-10-06 02:46:27 -04:00
Lioncash a61df86ef5
m68k/translate: Remove commented out code in m68k_tcg_init()
This isn't even in the main qemu repo, so we can get rid of this.
2018-10-06 02:41:09 -04:00
Peter Maydell a0a846a5d7
docs/devel/memory.txt: Document _with_attrs accessors
When we added the _with_attrs accessors we forgot to mention
them in the documentation.

Backports commit 687ac05d71bbb3172e0546248e40483ef43a4813 from qemu
2018-10-04 04:46:26 -04:00
Peter Maydell 01683fe97e
memory: Remove old_mmio accessors
Now that all the users of old_mmio MemoryRegion accessors
have been converted, we can remove the core code support.

Backports commit 62a0db942dec6ebfec19aac2b604737d3c9a2d75 from qemu
2018-10-04 04:45:30 -04:00
Philippe Mathieu-Daudé a3938167d4
memory: Fix access_with_adjusted_size(small size) on big-endian memory regions
Memory regions configured as DEVICE_BIG_ENDIAN (or DEVICE_NATIVE_ENDIAN on
big-endian guest) behave incorrectly when the memory access 'size' is smaller
than the implementation 'access_size'.

In the following code segment from access_with_adjusted_size():

if (memory_region_big_endian(mr)) {
    for (i = 0; i < size; i += access_size) {
        r |= access_fn(mr, addr + i, value, access_size,
                       (size - access_size - i) * 8, access_mask, attrs);
}

(size - access_size - i) * 8 is the number of bits that will arithmetic
shift the current value.

Currently we can only 'left' shift a read() access, and 'right' shift a write().

When the access 'size' is smaller than the implementation, we get a negative
number of bits to shift.

For the read() case, a negative 'left' shift is a 'right' shift :)
However since the 'shift' type is unsigned, there is currently no way to
right shift.

Fix this by changing the access_fn() prototype to handle signed shift values,
and modify the memory_region_shift_read|write_access() helpers to correctly
arithmetic shift the opposite direction when the 'shift' value is negative.
2018-10-04 04:40:42 -04:00
Philippe Mathieu-Daudé de28c93299
memory: Refactor common shifting code from accessors
Backports commit 3c754a9383ac70f316f1b98aec203182de250c42 from qemu
2018-10-04 04:39:29 -04:00
Philippe Mathieu-Daudé 7f0b91c261
memory: Use MAKE_64BIT_MASK()
Backports commit 36960b4d66d2dd59174f230766d1f4eaffec60a3 from qemu
2018-10-04 04:33:54 -04:00
Pavel Dovgalyuk 461fbaa9eb
target/i386: fix translation for icount mode
This patch fixes the checking of boundary crossing instructions.
In icount mode only first instruction of the block may cross
the page boundary to keep the translation deterministic.
These conditions already existed, but compared the wrong variable.

Backports commit 41d54dc09f1f327dedc79d5ba0b1b437ab7b0e94 from qemu
2018-10-04 04:32:26 -04:00
Marc-André Lureau 710467e034
qom/object: add some interface asserts
An interface can't have any instance size or callback, or itself
implement other interfaces (this is unsupported).

Backports commit 422ca1432f7b44f2a9f3ad94a65d36927da021fa from qemu
2018-10-04 04:30:42 -04:00
Paolo Bonzini 752aea8379
target/i386: rename HF_SVMI_MASK to HF_GUEST_MASK
This flag will be used for KVM's nested VMX migration; the HF_GUEST_MASK name
is already used in KVM, adopt it in QEMU as well.

Backports commit f8dc4c645ec2956a6cd97e0ca0fdd4753181f735 from qemu
2018-10-04 04:24:39 -04:00
Paolo Bonzini 0bc0ff320c
target/i386: unify masking of interrupts
Interrupt handling depends on various flags in env->hflags or env->hflags2,
and the exact detail were not exactly replicated between x86_cpu_has_work
and x86_cpu_exec_interrupt. Create a new function that extracts the
highest-priority non-masked interrupt, and use it in both functions.

Backports commit 92d5f1a4147c3722b5e9a8bcfb7dc261b7a8b855 from qemu
2018-10-04 04:19:57 -04:00
Igor Mammedov 68356c69fc
memory: cleanup side effects of memory_region_init_foo() on failure
if MemoryRegion intialization fails it's left in semi-initialized state,
where it's size is not 0 and attached as child to owner object.
And this leds to crash in following use-case:
    (monitor) object_add memory-backend-file,id=mem1,size=99999G,mem-path=/tmp/foo,discard-data=yes
    memory.c:2083: memory_region_get_ram_ptr: Assertion `mr->ram_block' failed
    Aborted (core dumped)
it happens due to assumption that memory region is intialized when
memory_region_size() != 0
and therefore it's ok to access it in
file_backend_unparent()
    if (memory_region_size() != 0)
        memory_region_get_ram_ptr()

which happens when object_add fails and unparents failed backend making
file_backend_unparent() access invalid memory region.

Fix it by making sure that memory_region_init_foo() APIs cleanup externally
visible side effects on failure (like set size to 0 and unparenting object)
2018-10-04 04:15:29 -04:00
Pavel Dovgalyuk 0242d19e79
translator: fix breakpoint processing
QEMU cannot pass through the breakpoints when 'si' command is used
in remote gdb. This patch disables inserting the breakpoints
when we are already single stepping though the gdb remote protocol.
This patch also fixes icount calculation for the blocks that include
breakpoints - instruction with breakpoint is not executed and shouldn't
be used in icount calculation.

Backports commit f9f1f56e4da088b993ce28775c271d5bcdcf49ae from qemu
2018-10-04 04:04:57 -04:00
Emilio G. Cota b9bb6cead9
target/i386: move x86_64_hregs to DisasContext
And convert it to a bool to use an existing hole
in the struct.

Backports commit 1dbe15ef57abdf7b6a26c8e638abf6413a4b9d0c from qemu
2018-10-04 04:02:50 -04:00
Emilio G. Cota 90e189ca24
target/i386: move cpu_tmp1_i64 to DisasContext
Backports commit 776678b2961848a80387509c433dc04b0f761592 from qemu
2018-10-04 03:59:13 -04:00
Emilio G. Cota 04530acab2
target/i386: move cpu_tmp3_i32 to DisasContext
Backports commit 4f82446de695f080ed148a0e47fc141e928665af from qemu
2018-10-04 03:56:05 -04:00
Emilio G. Cota 781e6bde41
target/i386: move cpu_tmp2_i32 to DisasContext
Backports commit 6bd48f6f206b6f32a5bbeebc3ae6886d4f587981 from qemu
2018-10-04 03:53:31 -04:00
Emilio G. Cota c13337d1bc
target/i386: move cpu_ptr1 to DisasContext
Backports commit 6387e8303ffb26cfb40b0f93372f1519229b4d2c from qemu
2018-10-04 03:48:09 -04:00
Emilio G. Cota 3e442d4480
target/i386: move cpu_ptr0 to DisasContext
Backports commit 2ee2646491a293a92d1c85e90e12419a8c199ed0 from qemu
2018-10-04 03:46:53 -04:00
Emilio G. Cota cc872aa711
target/i386: move cpu_tmp4 to DisasContext
Backports commit 5022f28f1e4033eb369b744ad61b96d086beca1b from qemu
2018-10-04 03:45:28 -04:00
Emilio G. Cota d2752ebc42
target/i386: move cpu_tmp0 to DisasContext
Backports commit fbd80f02df3fe272ba0f4825df27b8459dafbc14 from qemu
2018-10-04 03:41:13 -04:00
Emilio G. Cota b704b6c205
target/i386: move cpu_T1 to DisasContext
Backports commit b48597b0eda32d4c7ade2ba3f98f06f62289e3e2 from qemu
2018-10-04 03:35:10 -04:00
Emilio G. Cota 70b327dc82
target/i386: move cpu_T0 to DisasContext
Backports commit c66f97273f677d76afaaeb0e688eb08499701b1b from qemu
2018-10-04 03:29:13 -04:00
Emilio G. Cota c1d70758ea
target/i386: move cpu_A0 to DisasContext
Backports commit 6b672b5d6b14422c131969c5725f738751e12847 from qemu
2018-10-04 01:16:35 -04:00
Emilio G. Cota 30c66bcca3
target/i386: move cpu_cc_srcT to DisasContext
Backports commit 93a3e108eb6a9bb781ab7db6e92d91528e482030 from qemu
2018-10-04 00:59:00 -04:00
Daniel P. Berrangé ea64a4629f
configure: preserve various environment variables in config.status
The config.status script is auto-generated by configure upon
completion. The intention is that config.status can be later invoked by
the developer directly, or by make indirectly, to re-detect the same
environment that configure originally used.

The current config.status script, however, only contains a record of the
command line arguments to configure. Various environment variables have
an effect on what configure will find. In particular PKG_CONFIG_LIBDIR &
PKG_CONFIG_PATH vars will affect what libraries pkg-config finds. The
PATH var will affect what toolchain binaries and XXXX-config scripts are
found. The LD_LIBRARY_PATH var will affect what libraries are
found. Most commands have env variables that will override the name/path
of the default version configure finds.

All these key env variables should be recorded in the config.status script.

Autoconf would also preserve CFLAGS, LDFLAGS, LIBS, CPPFLAGS, but QEMU
deals with those differently, expecting extra flags to be set using
configure args, rather than env variables. At the end of the script we
also don't have the original values of those env vars, as we modify them
during configure.

Backports commit e811da7fe229cc17d98b230bdfeaf6d0631ea987 from qemu
2018-10-04 00:46:48 -04:00
Emilio G. Cota f3f22c94e1
atomic: fix comment s/x64_64/x86_64/
Backports commit 119c440c3c599778bfb4f90d8e39fda132925813 from qemu
2018-10-04 00:44:48 -04:00
Roman Kapl 33e69342e3
tcg/i386: fix vector operations on 32-bit hosts
The TCG backend uses LOWREGMASK to get the low 3 bits of register numbers.
This was defined as no-op for 32-bit x86, with the assumption that we have
eight registers anyway. This assumption is not true once we have xmm regs.

Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes
and have overflown into other opcode fields, wreaking havoc.

To trigger these problems, you can try running the "movi d8, #0x0" AArch64
instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated,
but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2".

Fixes: 770c2fc7bb ("Add vector operations")

Backports commit 93bf9a42733321fb632bcb9eafd049ef0e3d9417 from qemu
2018-10-02 04:22:35 -04:00
Peter Maydell 04fead0dcb
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)

Backports commit 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf from qemu
2018-09-25 21:19:44 -04:00
Richard Henderson 994038c817
target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
Not only are the sve-related tb_flags fields unused when SVE is
disabled, but not all of the cpu registers are initialized properly
for computing same. This can corrupt other fields by ORing in -1,
which might result in QEMU crashing.

This bug was not present in 3.0, but this patch is cc'd to
stable because adf92eab90e3f5f34c285 where the bug was
introduced was marked for stable.

Backports commit e79b445d896deb61909be52b61b87c98a9ed96f7 from qemu
2018-09-25 21:17:32 -04:00
Markus Armbruster 8446222237
qapi: Emit a blank line before dummy declaration
We emit a dummy variable in each .c file "to shut up OSX toolchain
warnings about empty .o files" (commit 252dc3105fc). Separate it from
the code preceding it (if any) with a blank line.

Backports commit 5f1450f5444b42cde4b1edc61ea5fdcd57404d3e from qemu
2018-09-25 21:12:16 -04:00
Peter Xu 9c05496958
qapi: Drop qapi_event_send_FOO()'s Error ** argument
The generated qapi_event_send_FOO() take an Error ** argument. They
can't actually fail, because all they do with the argument is passing it
to functions that can't fail: the QObject output visitor, and the
@qmp_emit callback, which is either monitor_qapi_event_queue() or
event_test_emit().

Drop the argument, and pass &error_abort to the QObject output visitor
and @qmp_emit instead.

Backports commit 3ab72385b21d8d66df3f5fea42097ce264dc9d6b from qemu
2018-09-25 21:11:35 -04:00
Markus Armbruster 4a8e094958
qapi: Fix build_params() for empty parameter list
build_params() returns '' instead of 'void' when there are no
parameters. Can't happen now, but the next commit will change that.

Backports commit bdd2d42b890b3a908fa3fbdc9661541e1b57eb15 from qemu
2018-09-25 21:09:42 -04:00
Andrew Dutcher 81f8a1be80
eflags patch
Preserves EFLAGS across basic blocks.

Reapplies commit 3a1f231e8f from qemu
2018-09-07 22:01:24 -04:00
vardyh 8ca718367f
x86::trans: handle illegal case for opc c6/c7
Reference Intel software developer manual vol2 Appendix A Table A-6 for
detailed decoding information.

Re-applies commit ad767abda8 from qemu
2018-09-07 19:28:01 -04:00
Lioncash 48d98a76e7
hw/mips/mips_r4k: Fix initialization of MIPS target CPUs
MIPS emulation is now possible after this basic fix. Still a few kinks
to work out, but at least we hit the translation loop.
2018-09-03 17:40:08 -04:00
Lioncash fa8f566635
target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:36:23 -04:00
Lioncash e81fa596bc
target/arm/cpu: Use type_register instead of type_register_static() in arm_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:34:08 -04:00
Lioncash 34b22968a4
target/i386/cpu: Use type_register instead of type_register_static in x86_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:28:54 -04:00
Lioncash 0a759bf7f3
target/sparc: Fix SPARC target initialization
Brings up the SPARC target so it's able to be used for emulation
purposes.
2018-09-03 17:26:00 -04:00
Lioncash 44ca501cd3
target/m68k: Fix initialization of m68k targets
m68k is now able to be used for emulation again. It just needed to
properly have the unicorn context be set within the base type for the
CPUs
2018-09-03 17:04:42 -04:00
MerryMage 9b87d0f61a unicorn_arm: Allow for read/write of UC_ARM_REG_FPSCR 2018-09-03 21:03:55 +01:00
Lioncash fffc31e7e2
target/i386/translate: Synchronize EIP if read/write callbacks are set
This is another feature that was left by the wayside when upgrading
qemu. It's fairly trivial to restore.
2018-09-03 14:40:46 -04:00
Lioncash 0d0d8b6db9
target/i386/translate: Report proper instruction size in code hooks
This was intentionally broken to make updating qemu as quick as possible
when it was woefully out of date, particularly because the interface of
qemu's TCG changed quite a bit, so this code would have needed to be
changed anyways.

Now that qemu is up to date for this variant of Unicorn, we can repair
this functionality and also--and I put massive emphasis on this, since
this wasn't done in the original Unicorn repo--*actually document what
the heck we're doing in this case*, so it's not a pain to change in the
future if we actually need to do that. It makes it much, much, simpler
for people not involved with qemu to understand what is going on in this
case.
2018-09-03 14:09:05 -04:00
Lioncash dce6dde483
target/i386/translate: Remove unnecessary (and incorrect) pointer casts from some gen_op functions
These used to be necessary, as the relevant variables used to be void*,
thus making the casts necessary. Given they were changed to concrete
types over the course of backporting, these are unnecessary.
2018-09-03 10:44:55 -04:00
Lioncash 73c7c9aadc
unicorn_common: Fix unicorn memory functions failing
These functions, over the course of backporting qemu's newer changes,
were altered to return non-zero in the case of success, so we need to
update the cpu read/write functions as necessary.
2018-09-03 10:40:14 -04:00
Lioncash a97d643944
qemu/int128: Disable assert in int128.h
This mirrors the int128_get64() variant for the case when CONFIG_INT128
is not defined as 1, which was pre-existing in unicorn.
2018-09-03 09:54:59 -04:00
Lioncash 2beb139304
i386: Fix initialization of x86 targets 2018-09-03 09:14:35 -04:00
Nguyen Anh Quynh d149648f2f
x86: fix #968. also fix potential bug of not clearing high bytes when updateing EIP
Backports commit 4d0157eb4a4891fe9101ac84accbd11cd4277794 from qemu
2018-09-03 07:58:16 -04:00
Alex von Gluck IV 80b94a546f
Haiku support patches (#989)
* Haiku: fix broken gcc strong stack protector

* qemu: Backport minor Haiku fix

We need to push this fix upstream to qemu. If we don't
get it upstreamed, i'll circle back and patch it if
Unicorn updates its qemu version.

Backports commit c7be4a2160e15089563f207752fb346a38db18ec from unicorn
2018-09-03 07:55:51 -04:00
toshiMSFT b4bb7edfe8
Makes SYSENTER hookable again on x86
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing

Fixes unicorn-engine/unicorn#995

Backports commit 0f14c473445661a633ca5bda3a91ba1a87c35c64 from unicorn
2018-09-03 07:53:48 -04:00
Mat M e87df070d9
Merge pull request #11 from MerryMage/arm-aa32_vfp_dreg
Unicorn VFP access patches
2018-09-03 07:25:47 -04:00
MerryMage a13d51f756 unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
MerryMage 896a8e1320 unicorn_arm: Use ARM offset not ARM64 offset
Was introduced by 5439b4a542
2018-09-03 07:44:29 +01:00
Lioncash f419c5f554
hw/arm/tosa: Enable all CPU features by using the max target for A-class CPUs
This mirrors the current behavior for the AArch64 CPUs, where we also
use the max target.
2018-09-02 16:19:28 -04:00
Lioncash 0ad97c7ee3
hw/tosa: Fix initialization of AArch32 CPUs
We have to ensure that we pass the proper formatted name into cpu_new()
2018-09-02 16:02:26 -04:00
Stefan Markovic c870339a10
target/mips: Add definition of nanoMIPS I7200 CPU
Add definition of the first nanoMIPS processor in QEMU.

Backports commit d45942d908edee175a90f915ab92ac302eedf33a from qemu
2018-08-27 15:08:12 -04:00
Yongbok Kim d53c021cea
target/mips: Fix ERET/ERETNC behavior related to ADEL exception
Fix ERET/ERETNC so that ADEL exception can be raised.

Backports commit 26324ded91a5ad08a5de8f32b8ed5e5e243154cf from qemu
2018-08-27 15:00:59 -04:00
Stefan Markovic 7473e6dbe6
target/mips: Add updating BadInstr and BadInstrX for nanoMIPS
Update BadInstr and BadInstrX registers for nanoMIPS. The same
support for pre-nanoMIPS remains unimplemented.

Backports commit 7a5f784aa215df6bf5d674b4003f8df43bf3b2d4 from qemu
2018-08-27 15:00:05 -04:00
Dimitrije Nikolic 7e0342c9f6
target/mips: Add availability control via bit NMS
A set of nanoMIPS instructions is not available if Config5 bit NMS
is set.

Backports commit fb32f8c8560be7ca4e323cee1b839701126401d1 from qemu
2018-08-27 14:59:15 -04:00
Stefan Markovic 38f2640a34
target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
Add emulation of DSP ASE instructions for nanoMIPS - part 6.

Backports commit 0b591184a2d0686b8f2c5fb27cc9fe2f60752d57 from qemu
2018-08-27 06:47:59 -04:00
Stefan Markovic ba7d8bc0ab
target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
Add emulation of DSP ASE instructions for nanoMIPS - part 5.

Backports commit 4c75c985d9b4d2ac7e0183083e31c243b06a3f2b from qemu
2018-08-27 06:45:25 -04:00
Stefan Markovic 73a5efd599
target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
Add emulation of DSP ASE instructions for nanoMIPS - part 4.

Backports commit 8b3698b2947610e0645a65ace4822164d55dd76b from qemu
2018-08-27 06:43:34 -04:00
Stefan Markovic b6602fff1f
target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
Add emulation of DSP ASE instructions for nanoMIPS - part 3.

Backports commit 2ed42efaae9516b71b7edf669b120cad718ba37b from qemu
2018-08-27 06:34:14 -04:00
Stefan Markovic 33dee2e5f3
target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
Add emulation of DSP ASE instructions for nanoMIPS - part 2.

Backports commit 6d033ca7513d85562f1b6bbb002a38b1c2541e5d from qemu
2018-08-27 05:53:17 -04:00
Stefan Markovic 49f448af3c
target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
Add emulation of DSP ASE instructions for nanoMIPS - part 1.

Backports commit 3285a3e4445be70d5f2dbdd29249e1e2627a5216 from qemu
2018-08-27 05:52:12 -04:00
Stefan Markovic 795d903f1c
target/mips: Implement MT ASE support for nanoMIPS
Add emulation of MT ASE instructions for nanoMIPS.

Backports commit 0a1a6ed78ae13a87f23810899a838f8d0c0fa2a5 from qemu
2018-08-27 05:39:15 -04:00
Aleksandar Rikalo 8c0248696a
target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
This is done by adding a field in hflags for MT bit, and adding
functions check_mt() and check_cp0_mt().

Backports commit 9affc1c59279f482ff145e0371926f79b6448e3e from qemu
2018-08-27 05:36:38 -04:00
Stefan Markovic 93f7cd2307
target/mips: Add emulation of nanoMIPS 32-bit branch instructions
Add emulation of various flavors of nanoMIPS 32-bit branch
instructions.

Backports commit 11d0fc10b7efe3d0404a71e855c0d9f521ce3d66 from qemu
2018-08-27 05:34:52 -04:00
Aleksandar Rikalo 371bb5a134
target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside
adding core functionality of these instructions, this patch adds
support for availability control via configuration bit XNP.

Backports commit 0b16dcd180bdbe3add9edea42c2374d427882661 from qemu
2018-08-27 05:25:14 -04:00
Dimitrije Nikolic 128bfa00d2
target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.

Backports commit ab77fc611bf004dfd25ecad5b2c11261e32012e9 from qemu
2018-08-27 05:20:26 -04:00
Yongbok Kim e18c921501
target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
Add emulation of various nanoMIPS load and store instructions.

Backports commit 8f1d9b6d63978b80971b15fef16636f454241879 from qemu
2018-08-27 05:18:55 -04:00
James Hogan bcdee16199
target/mips: Implement emulation of nanoMIPS EXTW instruction
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).

Backports commit 821f2008c3c708e0e33158039ab55673a0f04519 from qemu
2018-08-27 05:14:54 -04:00
Matthew Fortune 06e5835cc7
target/mips: Implement emulation of nanoMIPS ROTX instruction
Added a helper for ROTX based on the pseudocode from the
architecture spec. This instraction was not present in previous
MIPS instruction sets.

Backports commit e222f5067269392af489731221750976d0cf3c05 from qemu
2018-08-27 05:11:14 -04:00
Yongbok Kim e9442a5ca9
target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.

Backports commit eac5266459fb83e70fbf33f95c7c846f89df5c6a from qemu
2018-08-27 05:07:40 -04:00
Yongbok Kim db0ca1924e
target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
Add emulation of misc nanoMIPS instructions situated in pool32axf.

Backports commit 642241870a029da1525ad1641e1c99d434580817 from qemu
2018-08-27 05:02:08 -04:00
Yongbok Kim a2ff65acec
target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)
Add emulation of nanoMIPS instructions that are situated in pool32a0.

Backports commit e0cf0e6586d6a2c7e56b58bdfb5a67cec04c2999 from qemu
2018-08-27 04:59:06 -04:00
Yongbok Kim aee648c5ee
target/mips: Add emulation of nanoMIPS FP instructions
Add emulation of basic floating point arithmetic for nanoMIPS.

Backports commit 579b8ea97a0a4b8e4b9e18d282ab0dc7138d41d1 from qemu
2018-08-27 04:55:19 -04:00
Yongbok Kim d77363e1ae
target/mips: Add emulation of nanoMIPS 48-bit instructions
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.

Backports commit 7ef009b2dd72852505c7348c0bd1f8eb1e62a064 from qemu
2018-08-27 04:53:02 -04:00
Yongbok Kim 6c31da99e3
target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV
Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV.

Backports commit 4d18232ca0f903df099d243ccfe28b0e545dc92d from qemu
2018-08-27 04:50:32 -04:00
Yongbok Kim 48d61aee0b
target/mips: Add emulation of some common nanoMIPS 32-bit instructions
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,
ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.

Backports commit c0280983034627a336248409711e969eb2ea8325 from qemu
2018-08-27 04:48:39 -04:00
Stefan Markovic 6b5dbbf6a3
target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions
Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines
gen_save(), gen_restore(), and gen_adjust_sp() are provided to support
this feature.

This patch at the same time provides function gen_op_addr_addi(). This
function will be used in emulation of some other nanoMIPS instructions.

Backports commit bf0718c59a4b27dd01346a7b5b9a183ed1b18fb7 from qemu
2018-08-27 04:43:27 -04:00
Yongbok Kim b4fa0bfbba
target/mips: Add emulation of nanoMIPS 16-bit logic instructions
Add emulation of NOT16, AND16, XOR16, OR16 instructions.

Backports commit 80845edf37bac0c1e8d378046bd2b741e4deefc8 from qemu
2018-08-27 04:35:58 -04:00