Commit graph

5906 commits

Author SHA1 Message Date
Frank Chang 61d69c8175 target/riscv: fix return value of do_opivx_widen()
do_opivx_widen() should return false if check function returns false.

Backports a69f97c1110205bc173657c77ce2d16877cad683
2021-03-08 12:13:16 -05:00
Frank Chang 98982dbe49 target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Backports 1989205c4e973bc7f9fac0ce0700993f30582538
2021-03-08 12:12:36 -05:00
Frank Chang d75c8e7fcf target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.

Backports 7acafcfa844fd93f5ff073077007627338bd6739
2021-03-08 12:11:38 -05:00
Philippe Mathieu-Daudé 798ce750d5 target/arm/cpu: Update coding style to make checkpatch.pl happy
Backports dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6
2021-03-08 11:35:28 -05:00
Peter Collingbourne de7bcbae57 target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
Section D6.7 of the ARM ARM states:

For the purpose of determining Tag Check Fault handling, unprivileged
load and store instructions are treated as if executed at EL0 when
executed at either:
- EL1, when the Effective value of PSTATE.UAO is 0.
- EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}
and the Effective value of PSTATE.UAO is 0.

ARM has confirmed a defect in the pseudocode function
AArch64.TagCheckFault that makes it inconsistent with the above
wording. The remedy is to adjust references to PSTATE.EL in that
function to instead refer to AArch64.AccessUsesEL(acctype), so
that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1.
The exception type for synchronous tag check faults remains unchanged.

This patch implements the described change by partially reverting
commits 50244cc76abc and cc97b0019bb5.

Backports 2d928adf8a9148510e1b2041145b8a873f4d26df
2021-03-08 11:34:03 -05:00
Richard Henderson 03c8d3ff00 target/arm: Speed up aarch64 TBL/TBX
Always perform one call instead of two for 16-byte operands.
Use byte loads/stores directly into the vector register file
instead of extractions and deposits to a 64-bit local variable.

In order to easily receive pointers into the vector register file,
convert the helper to the gvec out-of-line signature. Move the
helper into vec_helper.c, where it can make use of H1 and clear_tail.

Backports 519183d3fee58e52f7b51cf146c9dc9edc565059
2021-03-08 11:31:24 -05:00
Rebecca Cran 2e508af5d5 target/arm: Set ID_PFR2.SSBS to 1 for max 32-bit CPU
Enable FEAT_SSBS for the "max" 32-bit CPU.

Backports ed84a60ca80c403749c1fc1bab27c85d8edba39d
2021-03-08 11:27:02 -05:00
Rebecca Cran 0f7620f7cc target/arm: Enable FEAT_SSBS for max AARCH64 CPU
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.

Backports 89455d1ba6ed190e840cb732e63958755ea42a07
2021-03-08 11:26:20 -05:00
Rebecca Cran 01105515c7 target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.

Backports f2f68a78b793808b84367bc708d632969d4440aa
2021-03-08 11:23:50 -05:00
Lioncash 23dc2fb4a2 target/riscv: Enable vector extensions 2021-03-08 11:18:36 -05:00
LIU Zhiwei dba0d32708 target/riscv: vector compress instruction
Backports 31bf42a26cf8b1e02f27acd302ee0ef14e877682
2021-03-07 12:47:46 -05:00
LIU Zhiwei a68f111390 target/riscv: vector register gather instruction
Backports e4b83d5c0928507cc27a0f613675b117db9993e4
2021-03-07 12:45:36 -05:00
LIU Zhiwei 162ae6efd7 target/riscv: vector slide instructions
Backports ec17e03688ce4d0ae188db6d90b185b92a9a2087
2021-03-07 12:43:14 -05:00
LIU Zhiwei 0e0ac052cd target/riscv: floating-point scalar move instructions
Backports 2843420a562c107801bae20f74579e4fe540316f
2021-03-07 12:41:23 -05:00
LIU Zhiwei b75de9504c target/riscv: integer scalar move instruction
Backports 9fc08be626a96ae1ac0cffb22f30ae652c1c645a
2021-03-07 12:38:41 -05:00
LIU Zhiwei d61c1e91a8 target/riscv: integer extract instruction
Backports 90355f391d979ccd95d09ab42f647f103a3dbe69
2021-03-07 12:36:01 -05:00
LIU Zhiwei 5ff1871e32 target/riscv: vector element index instruction
Backports 126bec3f6ff3379e1a49f4a7d36922bfd079a3cc
2021-03-07 12:29:13 -05:00
LIU Zhiwei 2f7cdaee7b target/riscv: vector iota instruction
Backports 78d90cfe859c8f5bd7baa0d41a4b5126e08eac24
2021-03-07 12:27:10 -05:00
LIU Zhiwei ec24e09ce7 target/riscv: set-X-first mask bit
Backports 81fbf7daf2eccadd6480b90db95a2e8c410d4414
2021-03-07 12:25:09 -05:00
LIU Zhiwei 92d5ce9b66 target/riscv: vmfirst find-first-set mask bit
Backports 0db67e1c0c49011eb09c4f5b790eef15a2b4c351
2021-03-07 12:22:13 -05:00
LIU Zhiwei 782835889c target/riscv: vector mask population count vmpopc
Backports 2e88f551df8fe6af81c0f920b7341ae2c75d00f2
2021-03-07 12:20:01 -05:00
LIU Zhiwei 68765e92c0 target/riscv: vector mask-register logical instructions
c21f34aebfb15c112131e36f425986170a3fcae9
2021-03-07 12:16:44 -05:00
LIU Zhiwei 4cbb4ae73d target/riscv: vector widening floating-point reduction instructions
Backports 696b0c260a0312c865cd0e4a8f09d0b9f13b07c9
2021-03-07 12:12:49 -05:00
LIU Zhiwei ebe125af76 target/riscv: vector single-width floating-point reduction instructions
Backports 523547f19e3914f11543e2da03907c724f15cd5e
2021-03-07 12:11:01 -05:00
LIU Zhiwei 798c1682f8 target/riscv: vector wideing integer reduction instructions
Backports bba718200b2d2aac6ab5031817f7125571c983a1
2021-03-07 12:09:15 -05:00
LIU Zhiwei 4b1e548fd0 target/riscv: vector single-width integer reduction instructions
Backports fe5c9ab1fc185e96bf7e034954127429ca74d386
2021-03-07 12:07:51 -05:00
LIU Zhiwei e925927e23 target/riscv: narrowing floating-point/integer type-convert instructions
Backports 878d406ec28f945d262af4ffbea50b825d7a0825
2021-03-07 12:05:59 -05:00
LIU Zhiwei 0c80c49b1b target/riscv: widening floating-point/integer type-convert instructions
Backports 4514b7b12390525e59e335e7ca58fd44f6e69272
2021-03-07 12:02:56 -05:00
LIU Zhiwei 8b06759ba4 target/riscv: vector floating-point/integer type-convert instructions
Backports 921009732614fd620c75f05496597796719544cf
2021-03-07 12:00:36 -05:00
LIU Zhiwei fabc8bab77 target/riscv: vector floating-point merge instructions
Backports 64ab5846974140118c64e4d94ff2696932a0a58b
2021-03-07 11:58:41 -05:00
LIU Zhiwei f9c9716534 target/riscv: vector floating-point classify instructions
Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c
2021-03-07 11:55:45 -05:00
LIU Zhiwei b859be12b9 target/riscv: vector floating-point compare instructions
Backports 2a68e9e568faddf4d689a37fa6895bcb8404a677
2021-03-07 11:47:51 -05:00
LIU Zhiwei 31978f270b target/riscv: vector floating-point sign-injection instructions
Backports 1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
2021-03-07 11:43:47 -05:00
LIU Zhiwei f7f0425a4d target/riscv: vector floating-point min/max instructions
Backports 230b53ddd706c8b18a6d9beed1a0153b276d7037
2021-03-07 11:42:05 -05:00
LIU Zhiwei 69c73cfc4e target/riscv: vector floating-point square-root instruction
Backports d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
2021-03-07 11:40:04 -05:00
LIU Zhiwei 95a6d78121 target/riscv: vector widening floating-point fused multiply-add instructions
Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
2021-03-07 11:37:23 -05:00
LIU Zhiwei 42116609f0 target/riscv: vector single-width floating-point fused multiply-add instructions
Backports 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
2021-03-07 11:34:56 -05:00
LIU Zhiwei 14cbabde4f target/riscv: vector widening floating-point multiply
Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
2021-03-07 11:32:19 -05:00
LIU Zhiwei 5e4b142c31 target/riscv: vector single-width floating-point multiply/divide instructions
Backports 0e0057cbe2169195a08ae8247504e69f9b80542b
2021-03-07 11:30:14 -05:00
LIU Zhiwei 0de56731ae target/riscv: vector widening floating-point add/subtract instructions
eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
2021-03-07 11:27:33 -05:00
LIU Zhiwei 06092b88b9 target/riscv: vector single-width floating-point add/subtract instructions
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
2021-03-05 09:50:56 -05:00
LIU Zhiwei 5fb589cdd7 target/riscv: vector narrowing fixed-point clip instructions
Backports 9ff3d28739b760970f5e542c74a033470dca3f9b
2021-03-05 09:34:11 -05:00
LIU Zhiwei 241deddb50 target/riscv: vector single-width scaling shift instructions
Backports 04a614062dd5fb43f00bd955f44f7a2c3def016d
2021-03-05 09:32:15 -05:00
LIU Zhiwei e7582a5d74 target/riscv: vector widening saturating scaled multiply-add
Backports 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
2021-03-05 09:29:42 -05:00
LIU Zhiwei e27aadfa4f target/riscv: vector single-width fractional multiply with rounding and saturation
Backports 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
2021-03-05 09:26:56 -05:00
LIU Zhiwei 2343892c2e target/riscv: vector single-width averaging add and subtract
Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
2021-03-05 09:25:09 -05:00
LIU Zhiwei 87db3eb130 target/riscv: vector single-width saturating add and subtract
Backports eb2650e35ec1ed60ff302ce3330bd6c770640833
2021-03-05 09:23:17 -05:00
LIU Zhiwei 025aa6fd39 target/riscv: vector integer merge and move instructions
Backports 	f020a7a14505d6996497693e63331ab609847d93
2021-03-05 09:20:34 -05:00
LIU Zhiwei 9d14cc8d35 target/riscv: vector widening integer multiply-add instructions
Backports 2b587b335050dbc0cb3823758341f145c0375312
2021-03-05 09:13:03 -05:00
LIU Zhiwei 58891e213d target/riscv: vector single-width integer multiply-add instructions
Backports 54df813a331d3badfb83604c36bef7cb1de4315a
2021-03-05 09:11:33 -05:00
LIU Zhiwei 436e092e36 target/riscv: vector widening integer multiply instructions
Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428
2021-03-05 09:09:08 -05:00
LIU Zhiwei d144afdc45 target/riscv: vector integer divide instructions
Backports 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
2021-03-05 09:05:00 -05:00
Lioncash 14d06ee38c sparc: Fix build 2021-03-05 08:54:43 -05:00
Lioncash 704353c758 mips: Fix build 2021-03-05 08:51:51 -05:00
Lioncash dec4c70142 i386: Fix build 2021-03-05 08:35:14 -05:00
Lioncash 5436b713ce m68k: Fix build
A bunch of changes to the memory functions recently broke the build.
This fixes it.
2021-03-05 08:29:53 -05:00
Zheng Zhan Liang dfd53d7573 tcg/i386: rdpmc: fix the the condtions
Backports c45b426acd1ad8e30fbe1b9af8c07b2889c28c6b
2021-03-04 18:50:48 -05:00
Chenyi Qiang d7adcf1d7f target/i386: Add bus lock debug exception support
Bus lock debug exception is a feature that can notify the kernel by
generate an #DB trap after the instruction acquires a bus lock when
CPL>0. This allows the kernel to enforce user application throttling or
mitigations.

This feature is enumerated via CPUID.(EAX=7,ECX=0).ECX[bit 24].

Backports 06e878b413766778a53be3d25c0373a23679d039
2021-03-04 18:50:00 -05:00
Richard Henderson d044062b26 target/arm: Enable MTE for user-only
Backports e32328645ed6fc4f20f0164dfc9ce1bf7e667cc4
2021-03-04 18:46:47 -05:00
Richard Henderson c588c150e4 target/arm: Add allocation tag storage for user mode
Use the now-saved PAGE_ANON and PAGE_MTE bits,
and the per-page saved data.

Backports a11d3830d96ad8077440ce4e0aa60608f1f12dde
2021-03-04 18:46:13 -05:00
Richard Henderson f03656b5c3 target/arm: Split out syndrome.h from internals.h
Move everything related to syndromes to a new file,
which can be shared with linux-user.

Backports 1fe27859427bd377a45708310947de54c687d9ff
2021-03-04 18:44:07 -05:00
Richard Henderson 84368d2d6d target/arm: Use the proper TBI settings for linux-user
We were fudging TBI1 enabled to speed up the generated code.
Now that we've improved the code generation, remove this.
Also, tidy the comment to reflect the current code.

The pauth test was testing a kernel address (-1) and making
incorrect assumptions about TBI1; stick to userland addresses.

Backports 16c849784873d10d0da257d698e391fddea1f0e4
2021-03-04 18:41:49 -05:00
Richard Henderson de982a8346 target/arm: Improve gen_top_byte_ignore
Use simple arithmetic instead of a conditional
move when tbi0 != tbi1.

Backports 2169b5c6f7a791ef9c43c72412efaafae3245114
2021-03-04 18:39:43 -05:00
Peter Maydell ab07f048d8 bswap.h: Remove unused float-access functions
The float-access functions stfl_*, stfq*, ldfl* and ldfq* are now
unused; remove them. (Accesses to float64 and float32 types can be
made with the ldl/stl/ldq/stq functions, as float64 and float32 are
guaranteed to be typedefs for normal integer types.)

Backports f930224fffead81e23e699517d1351e33890b6f7
2021-03-04 18:37:02 -05:00
Daniel Müller 642a683d7a target/arm: Correctly initialize MDCR_EL2.HPMN
When working with performance monitoring counters, we look at
MDCR_EL2.HPMN as part of the check whether a counter is enabled. This
check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no
counters are "enabled" for < EL2.
That's in violation of the Arm specification, which states that

> On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in
> PMCR_EL0.N

That's also what a comment in the code acknowledges, but the necessary
adjustment seems to have been forgotten when support for more counters
was added.
This change fixes the issue by setting the reset value to PMCR.N, which
is four.

Backports d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621
2021-03-04 18:34:06 -05:00
Peter Maydell 2c926832bb accel/tcg: Add URL of clang bug to comment about our workaround
In cpu_exec() we have a longstanding workaround for compilers which
do not correctly implement the part of the sigsetjmp()/siglongjmp()
spec which requires that local variables which are not changed
between the setjmp and the longjmp retain their value.

I recently ran across the upstream clang bug report for this; add a
link to it to the comment describing the workaround, and generally
expand the comment, so that we have a reasonable chance in future of
understanding why it's there and determining when we can remove it,
assuming clang eventually fixes the bug.

Remove the /* buggy compiler */ comments on the #else and #endif:
they don't add anything to understanding and are somewhat misleading
since they're sandwiching the code path for *non*-buggy compilers.

Backports e6a41a045c298538d303cd8fe8d7ae29a0c066ad
2021-03-04 18:32:51 -05:00
Rebecca Cran 93b0428f48 target/arm: Set ID_PFR0.DIT to 1 for max 32-bit CPU
Enable FEAT_DIT for the "max" 32-bit CPU.

Backports 5385320c2b3183f2e18dbc55c23ecba9272500c2
2021-03-04 18:31:36 -05:00
Rebecca Cran 66d96057a4 target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for max AA64 CPU
Enable FEAT_DIT for the "max" AARCH64 CPU.

Backports 2bf1eff9e9125a3d73901991dcfb9cb2ace03be1
2021-03-04 18:30:59 -05:00
Rebecca Cran f7424d89e2 target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.

This allows us to add support for CPSR_DIT, adding helper functions
to merge SPSR_ELx to and from CPSR.

Backports f944a854ce4007000accf7c191b5b52916947198
2021-03-04 18:24:57 -05:00
Rebecca Cran d8458f14af target/arm: Add support for FEAT_DIT, Data Independent Timing
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.

Backports dc8b18534ea1dcc90d80ad9a61a3b0aa7eb312fb
2021-03-04 18:19:32 -05:00
Mike Nawrocki 4e482764e2 target/arm: Fix SCR RES1 handling
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.

The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.

Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
is supported at EL1 or above.

Backports 10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5
2021-03-04 18:15:39 -05:00
Chenyi Qiang 807d541e19 target/i386: Expose VMX entry/exit load pkrs control bits
Expose the VMX exit/entry load pkrs control bits in
VMX_TRUE_EXIT_CTLS/VMX_TRUE_ENTRY_CTLS MSRs to guest, which supports the
PKS in nested VM.

Backports 52a44ad2b92ba4cd81c2b271cd5e4a2d820e91fc
2021-03-04 18:13:36 -05:00
Paolo Bonzini 834e2b2643 target/i86: implement PKS
Protection Keys for Supervisor-mode pages is a simple extension of
the PKU feature that QEMU already implements. For supervisor-mode
pages, protection key restrictions come from a new MSR. The MSR
has no XSAVE state associated to it.

PKS is only respected in long mode. However, in principle it is
possible to set the MSR even outside long mode, and in fact
even the XSAVE state for PKRU could be set outside long mode
using XRSTOR. So do not limit the migration subsections for
PKRU and PKRS to long mode.

Backports e7e7bdababeefff10736c6adf410c66d2f0d46fe
2021-03-04 18:12:44 -05:00
David Greenaway 0c1c359b5c target/i386: Fix decoding of certain BMI instructions
This patch fixes a translation bug for a subset of x86 BMI instructions
such as the following:

c4 e2 f9 f7 c0 shlxq %rax, %rax, %rax

Currently, these incorrectly generate an undefined instruction exception
when SSE is disabled via CR4, while instructions like "shrxq" work fine.

The problem appears to be related to BMI instructions encoded using VEX
and with a mandatory prefix of "0x66" (data). Instructions with this
data prefix (such as shlxq) are currently rejected. Instructions with
other mandatory prefixes (such as shrxq) translate as expected.

This patch removes the incorrect check in "gen_sse" that causes the
exception to be generated. For the non-BMI cases, the check is
redundant: prefixes are already checked at line 3696.

Buglink: https://bugs.launchpad.net/qemu/+bug/1748296

Backports 51909241d26fe6fe18a08def93ccc8273f61a8b3
2021-03-04 18:08:47 -05:00
Paolo Bonzini 56afe9f919 target/i386: do not set LM for 32-bit emulation '-cpu host/max'
32-bit targets by definition do not support long mode; therefore, the
bit must be masked in the features supported by the accelerator.

As a side effect, this avoids setting up the 0x80000008 CPUID leaf
for

qemu-system-i386 -cpu host

which since commit 5a140b255d ("x86/cpu: Use max host physical address
if -cpu max option is applied") would have printed this error:

qemu-system-i386: phys-bits should be between 32 and 36 (but is 48)

Backports 5ea9e9e239db83391a39c09f1de63c4099c20df5
2021-03-04 18:07:38 -05:00
Claudio Fontana 18100d1a3b cpu: move debug_check_watchpoint to tcg_ops
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.

Make debug_check_watchpoint optional, and move it to tcg_ops.

Backports c73bdb35a91fb6b17c2c93b1ba381fc88a406f8d
2021-03-04 17:30:20 -05:00
Claudio Fontana 7b0c98c236 cpu: move adjust_watchpoint_address to tcg_ops
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")

introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.

Make adjust_watchpoint_address optional and move it to tcg_ops.

Backports 9ea9087bb4a86893e4ac6ff643837937dc9e5849
2021-03-04 17:24:32 -05:00
Claudio Fontana ddfed5f3a6 cpu: move do_unaligned_access to tcg_ops
make it consistently SOFTMMU-only.

Backports 8535dd702dd054a37a85e0c7971cfb43cc7b50e3
2021-03-04 17:20:02 -05:00
Claudio Fontana ec08ac4995 cpu: move cc->transaction_failed to tcg_ops
Backports cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c
2021-03-04 17:16:41 -05:00
Claudio Fontana ee73443c7d cpu: move cc->do_interrupt to tcg_ops
Backports 0545608056a6161e7020cd7b9368d9636fa80051
2021-03-04 17:10:14 -05:00
Eduardo Habkost bc86f4377c cpu: Move debug_excp_handler to tcg_ops
Backports e9ce43e97a19090ae8975ef168b95ba3d29be991
2021-03-04 17:05:57 -05:00
Eduardo Habkost 76a10fa8e0 cpu: Move tlb_fill to tcg_ops
Backports e124536f37377cff5d68925d4976ad604d0ebf3a
2021-03-04 17:01:55 -05:00
Eduardo Habkost 03cc62e39c cpu: Move cpu_exec_* to tcg_ops
Backports 48c1a3e303b5a2cca48679645ad3fbb914db741a
2021-03-04 16:56:55 -05:00
Eduardo Habkost eb38ac1809 cpu: Move synchronize_from_tb() to tcg_ops
Backports ec62595bab1873c48a34849de70011093177e769
2021-03-04 16:48:27 -05:00
Claudio Fontana 21375463ea target/riscv: remove CONFIG_TCG, as it is always TCG
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.

Backports 6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff
2021-03-04 16:40:33 -05:00
Eduardo Habkost b9b711afe3 cpu: Introduce TCGCpuOperations struct
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().

The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.

Backports e9e51b7154404efc9af8735ab87c658a9c434cfd
2021-03-04 16:38:25 -05:00
Claudio Fontana 11ae599cb8 target/arm: do not use cc->do_interrupt for KVM directly
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,

but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture state in a
similar way where userspace code has identified that it needs to
deliver an exception to the guest.

In the case of ARM, that includes:

1) the vcpu thread got a SIGBUS indicating a memory error,
and we need to deliver a Synchronous External Abort to the guest to
let it know about the error.
2) the kernel told us about a debug exception (breakpoint, watchpoint)
but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
so it must be a breakpoint the guest itself has set up, therefore
we need to deliver it to the guest.

So in order to reuse code, the same arm_do_interrupt function is used.
This is all fine, but we need to avoid calling it using the callback
registered in CPUClass, since that one is now TCG-only.

Fortunately this is easily solved by replacing calls to
CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().

Backports 853bfef4e6d60244fd131ec55bbf1e7caa52599b. We don't support
KVM, so we just bring the comment addition over.
2021-03-04 16:33:23 -05:00
Richard Henderson 3e81f9dd20 tcg: Remove TCG_TARGET_CON_SET_H
All backends have now been converted to tcg-target-con-set.h,
so we can remove the fallback code.

Backports 0c823e596877a30fd6c17a1ae9f98218a53055ea
2021-03-04 16:29:16 -05:00
Lioncash 5fc6840277 tcg: Remove unsupported backends
I really don't want to support all these backends on an ARM-focused
backend.

Also the notion of someone saying
"yes, I would like to compute things using MIPS/SPARC/PPC instead of
literally anything else" is wild to me.

Thus, I will solve the problem by simply not thinking about it
whatsoever.
2021-03-04 16:27:15 -05:00
Richard Henderson 2a4e444688 tcg/arm: Split out constraint sets to tcg-target-con-set.h
Backports 7166eebb9bbe05fd956bd46b13643e1ae04c00ec
2021-03-04 16:23:06 -05:00
Richard Henderson 3b0cc6a8a8 tcg/aarch64: Split out constraint sets to tcg-target-con-set.h
Backports 39e7522b4ac86636e09ccb43487b14fe690f1658
2021-03-04 16:19:33 -05:00
Richard Henderson 8e4f432706 tcg/i386: Split out constraint sets to tcg-target-con-set.h
This exports the constraint sets from tcg_target_op_def to
a place we will be able to manipulate more in future.

Backports 4c22e840880e935ea07f1c4352bd8c54febff4df
2021-03-04 16:14:02 -05:00
Richard Henderson 570dc4a287 tcg: Remove TCG_TARGET_CON_STR_H
All backends have now been converted to tcg-target-con-str.h,
so we can remove the fallback code.

Backports 8c07f3262ebb3bb01041a812354399dfa96a4c1f
2021-03-04 16:06:18 -05:00
Richard Henderson af77ca2679 tcg/sparc: Split out target constraints to tcg-target-con-str.h
Backports 77f268e80b40f005e984b0818d9e01862e72f393
2021-03-04 16:04:54 -05:00
Richard Henderson a10afe6cff tcg/s390: Split out target constraints to tcg-target-con-str.h
Backports c947deb13ea1a5c7b127177a3b5cc7d2f8607ab2
2021-03-04 16:02:31 -05:00
Richard Henderson 154faa6df6 tcg/mips: Split out target constraints to tcg-target-con-str.h
Backports 51800e434679a88bff8b48f62e55ab14642d223e
2021-03-04 16:01:20 -05:00
Richard Henderson 6632fe21bd tcg/ppc: Split out target constraints to tcg-target-con-str.h
Backports 85d251d7ec47382171a292e741385bd25505d182
2021-03-04 15:59:59 -05:00
Richard Henderson 8c9f44342e tcg/aarch64: Split out target constraints to tcg-target-con-str.h
Backports abc730e18e34ca6282f412f1a20410b76f2d74b7
2021-03-04 15:58:26 -05:00
Richard Henderson 09890ddcb3 tcg/arm: Split out target constraints to tcg-target-con-str.h
Backports 3440d583d64dedf82e2774b266bcae46253d6b06
2021-03-04 15:56:55 -05:00
Richard Henderson 846fa770d6 tcg/i386: Split out target constraints to tcg-target-con-str.h
This eliminates the target-specific function target_parse_constraint
and folds it into the single caller, process_op_defs. Since this is
done directly into the switch statement, duplicates are compilation
errors rather than silently ignored at runtime.

Backports 358b492392ad91d45a9714f7cd28fc1d83ffd8b
2021-03-04 15:53:55 -05:00