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187 commits

Author SHA1 Message Date
LIU Zhiwei 42116609f0 target/riscv: vector single-width floating-point fused multiply-add instructions 
Backports 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
 2021-03-07 11:34:56 -05:00
LIU Zhiwei 14cbabde4f target/riscv: vector widening floating-point multiply 
Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
 2021-03-07 11:32:19 -05:00
LIU Zhiwei 5e4b142c31 target/riscv: vector single-width floating-point multiply/divide instructions 
Backports 0e0057cbe2169195a08ae8247504e69f9b80542b
 2021-03-07 11:30:14 -05:00
LIU Zhiwei 0de56731ae target/riscv: vector widening floating-point add/subtract instructions 
eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
 2021-03-07 11:27:33 -05:00
LIU Zhiwei 06092b88b9 target/riscv: vector single-width floating-point add/subtract instructions 
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
 2021-03-05 09:50:56 -05:00
LIU Zhiwei 5fb589cdd7 target/riscv: vector narrowing fixed-point clip instructions 
Backports 9ff3d28739b760970f5e542c74a033470dca3f9b
 2021-03-05 09:34:11 -05:00
LIU Zhiwei 241deddb50 target/riscv: vector single-width scaling shift instructions 
Backports 04a614062dd5fb43f00bd955f44f7a2c3def016d
 2021-03-05 09:32:15 -05:00
LIU Zhiwei e7582a5d74 target/riscv: vector widening saturating scaled multiply-add 
Backports 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
 2021-03-05 09:29:42 -05:00
LIU Zhiwei e27aadfa4f target/riscv: vector single-width fractional multiply with rounding and saturation 
Backports 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
 2021-03-05 09:26:56 -05:00
LIU Zhiwei 2343892c2e target/riscv: vector single-width averaging add and subtract 
Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
 2021-03-05 09:25:09 -05:00
LIU Zhiwei 87db3eb130 target/riscv: vector single-width saturating add and subtract 
Backports eb2650e35ec1ed60ff302ce3330bd6c770640833
 2021-03-05 09:23:17 -05:00
LIU Zhiwei 025aa6fd39 target/riscv: vector integer merge and move instructions 
Backports 	f020a7a14505d6996497693e63331ab609847d93
 2021-03-05 09:20:34 -05:00
LIU Zhiwei 9d14cc8d35 target/riscv: vector widening integer multiply-add instructions 
Backports 2b587b335050dbc0cb3823758341f145c0375312
 2021-03-05 09:13:03 -05:00
LIU Zhiwei 58891e213d target/riscv: vector single-width integer multiply-add instructions 
Backports 54df813a331d3badfb83604c36bef7cb1de4315a
 2021-03-05 09:11:33 -05:00
LIU Zhiwei 436e092e36 target/riscv: vector widening integer multiply instructions 
Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428
 2021-03-05 09:09:08 -05:00
LIU Zhiwei d144afdc45 target/riscv: vector integer divide instructions 
Backports 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
 2021-03-05 09:05:00 -05:00
Claudio Fontana ddfed5f3a6 cpu: move do_unaligned_access to tcg_ops 
make it consistently SOFTMMU-only.

Backports 8535dd702dd054a37a85e0c7971cfb43cc7b50e3
 2021-03-04 17:20:02 -05:00
Claudio Fontana ee73443c7d cpu: move cc->do_interrupt to tcg_ops 
Backports 0545608056a6161e7020cd7b9368d9636fa80051
 2021-03-04 17:10:14 -05:00
Eduardo Habkost 76a10fa8e0 cpu: Move tlb_fill to tcg_ops 
Backports e124536f37377cff5d68925d4976ad604d0ebf3a
 2021-03-04 17:01:55 -05:00
Eduardo Habkost eb38ac1809 cpu: Move synchronize_from_tb() to tcg_ops 
Backports ec62595bab1873c48a34849de70011093177e769
 2021-03-04 16:48:27 -05:00
Claudio Fontana 21375463ea target/riscv: remove CONFIG_TCG, as it is always TCG 
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.

Backports 6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff
 2021-03-04 16:40:33 -05:00
Eduardo Habkost b9b711afe3 cpu: Introduce TCGCpuOperations struct 
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().

The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.

Backports e9e51b7154404efc9af8735ab87c658a9c434cfd
 2021-03-04 16:38:25 -05:00
Richard Henderson 5e6196ea6b target/riscv: Set instance_align on RISCVCPU TypeInfo 
Fix alignment of CPURISCVState.vreg.

Backports 5de5b99b3101a1648ed583193db8d92eea0c4545
 2021-03-01 19:00:27 -05:00
LIU Zhiwei 9b7f4b72fc target/riscv: vector single-width integer multiply instructions 2021-02-26 10:46:26 -05:00
LIU Zhiwei ab81642440 target/riscv: vector integer min/max instructions 
558fa7797c919c4f21ac10980f3ed28160d6d3cb
 2021-02-26 10:43:13 -05:00
LIU Zhiwei 965af9986a target/riscv: vector integer comparison instructions 
1366fc79be04fa56a0e3f078ba4f26c27ac67e89
 2021-02-26 10:40:33 -05:00
LIU Zhiwei 244793c4e8 target/riscv: vector single-width bit shift instructions 
Backports 3277d955d21d8943d80062b4cfd8547f831dbd51
 2021-02-26 10:37:09 -05:00
LIU Zhiwei 56c0e253c2 target/riscv: vector bitwise logical instructions 
Backports d3842924cf93d104f691c5ea9090d6700ccef281
 2021-02-26 10:30:33 -05:00
LIU Zhiwei 05153c6d7c target/riscv: vector integer add-with-carry / subtract-with-borrow instructions 
3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448
 2021-02-26 10:19:48 -05:00
LIU Zhiwei b9814de4c3 target/riscv: vector widening integer add and subtract 
Backports 8fcdf77630290591a6068c2d82ca2935338c3b0c
 2021-02-26 10:05:43 -05:00
LIU Zhiwei f564388e89 target/riscv: vector single-width integer add and subtract 
Backports 43740e3a3b3bb66456103684e622ba4e9baae297
 2021-02-26 09:58:31 -05:00
LIU Zhiwei 7d0d7338c2 target/riscv: add vector amo operations 
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction

Backports 268fcca66bde62257960ec8d859de374315a5e3d
 2021-02-26 09:47:32 -05:00
LIU Zhiwei 152934bade target/riscv: add fault-only-first unit stride load 
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.

Backports commit 022b4ecf775ffeff522eaea4f0d94edcfe00a0a9 from qemu
 2021-02-26 09:28:19 -05:00
LIU Zhiwei 887c29bc79 target/riscv: add vector index load and store instructions 
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.

Backports f732560e3551c0823cee52efba993fbb8f689a36
 2021-02-26 03:00:45 -05:00
LIU Zhiwei c7a17d04a2 target/riscv: add vector stride load and store instructions 
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.

Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.

Backports 751538d5da557e5c10e5045c2d27639580ea54a7
 2021-02-26 02:55:14 -05:00
LIU Zhiwei e4bc5056cd target/riscv: add an internals.h header 
The internals.h keeps things that are not relevant to the actual architecture,
only to the implementation, separate.

Backports f476f17740ad42288d42dd8fedcdae8ca7007a16
 2021-02-26 02:39:29 -05:00
LIU Zhiwei 9db3b70869 target/riscv: add vector configure instruction 
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.

Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu
 2021-02-26 02:37:59 -05:00
LIU Zhiwei 0554e79ad1 target/riscv: support vector extension csr 
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.

Backports 8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a from qemu
 2021-02-26 02:25:58 -05:00
LIU Zhiwei bff31d8822 target/riscv: implementation-defined constant parameters 
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.

Backports 32931383270e2ca8209267ca99f23f3c5f780982 from qemu
 2021-02-26 02:23:28 -05:00
LIU Zhiwei 0968caa249 target/riscv: add vector extension field in CPURISCVState 
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.

Backports ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 from qemu
 2021-02-26 02:17:49 -05:00
Zong Li 001d2e6a29 target/riscv: Fix the range of pmpcfg of CSR funcion table 
Backports commit 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d from qemu
 2021-02-25 23:35:21 -05:00
Alistair Francis e1f49dc888 target/riscv: Implement checks for hfence 
Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.

Backports commit 2761db5fc20943bbd606b6fd49640ac000398de6 from qemu
 2021-02-25 12:03:57 -05:00
Alistair Francis 8eb8bc290f target/riscv: Move the hfence instructions to the rvh decode 
Also correct the name of the VVMA instruction.

Backports commit b8429ded723ec52568e05f6a24ed78c93224687c from qemu
 2021-02-25 11:59:49 -05:00
Alistair Francis 39ff690eff target/riscv: Report errors validating 2nd-stage PTEs 
Backports commit 88914473e748db20d8e18b9735f647a683319fa6 from qemu
 2021-02-25 11:55:53 -05:00
Alistair Francis a6c323c912 target/riscv: Set access as data_load when validating stage-2 PTEs 
Backports commit efe9f9c820d1322729957a60ff785c9527a79ddf from qemu
 2021-02-25 11:54:31 -05:00
Ian Jiang 5c3a2f391c riscv: Add helper to make NaN-boxing for FP register 
The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.

Backports commit 354908cee1f7ff761b5fedbdb6376c378c10f941 from qemu
 2021-02-25 11:53:27 -05:00
Alistair Francis 2b2f91f82c target/riscv: Add the lowRISC Ibex CPU 
The reset vector is set in the init function don't set it again in
realize.

Backports commit 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 from qemu
 2020-06-14 22:28:55 -04:00
Alistair Francis 2584ab8ee5 target/riscv: Drop support for ISA spec version 1.09.1 
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Backports commit 1a9540d1f1a9c5022d9273d0244e5809679dd33b from qemu
 2020-06-14 22:23:26 -04:00
Alistair Francis e35d56a146 target/riscv: Remove the deprecated CPUs 2020-06-14 22:15:16 -04:00
Corey Wharton bc097bd2ae target/riscv: Add a sifive-e34 cpu type 
The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.

Backports commit d784733bf1875c1ba355c69739518f24d56f1260 from qemu
 2020-04-30 21:08:10 -04:00