Alistair Francis
416b2a0077
target/riscv: Split the Hypervisor execute load helpers
...
Split the hypervisor execute load functions into two seperate functions.
This avoids us having to pass the memop to the C helper functions.
Backports 7687537ab0c16e0b1e69e7707456573a64b8e13b
2021-03-08 15:14:47 -05:00
Alistair Francis
4762dcda3c
target/riscv: Remove the hyp load and store functions
...
Remove the special Virtulisation load and store functions and just use
the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions
instead.
As part of this change we ensure we still run an access check to make
sure we can perform the operations.
Backports 743077b35b1ed88ed243daefafe9403d88a958f6
2021-03-08 15:11:11 -05:00
Alistair Francis
0e14547c7d
target/riscv: Support the Virtual Instruction fault
...
Backports e39a8320b088dd5efc9ebaafe387e52b3d962665
2021-03-08 13:55:02 -05:00
Alistair Francis
4972437f93
target/riscv: Allow generating hlv/hlvx/hsv instructions
...
Backports 8c5362acb573b8b1913238a5ddefdeef12f513a8
2021-03-08 13:13:32 -05:00
LIU Zhiwei
cde007ccb6
target/riscv: check before allocating TCG temps
...
Backports ec80f8745931f0c8f8f2251e16bcc69170cf6f27
2021-03-08 12:41:19 -05:00
LIU Zhiwei
8fe29be764
target/riscv: Clean up fmv.w.x
...
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Backports 6e0229e63868b8b5bfcc54959cea227ed19f7bd3
2021-03-08 12:39:38 -05:00
Richard Henderson
3af34d3df4
target/riscv: Check nanboxed inputs in trans_rvf.inc.c
...
If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan. The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.
Backports ffe70e4dfc9cf2a6934e674b81b69c847b403c4b
2021-03-08 12:38:15 -05:00
Richard Henderson
f0bb9a7f39
target/riscv: Generate nanboxed results from trans_rvf.inc.c
...
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.
Backports 40eaa473611936445ae9c63841445cfa6e36840b
2021-03-08 12:26:49 -05:00
Richard Henderson
52f2d5cbee
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
...
Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno. Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.
Backports d36a86d01e67792c51dd2a82360cda012bde9442
2021-03-08 12:24:20 -05:00
LIU Zhiwei
0f95c05ca4
target/riscv: fix vector index load/store constraints
...
Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.
And this constraint has been added to the v0.8 spec.
Backports 3e09396e36dff4234afd6f6fd51861949be383e1
2021-03-08 12:16:45 -05:00
LIU Zhiwei
fdfa52f424
target/riscv: Quiet Coverity complains about vamo*
...
Backports eabfeb0cb9e054108b3e29a3a85363b3d80d9c38
2021-03-08 12:15:56 -05:00
Frank Chang
61d69c8175
target/riscv: fix return value of do_opivx_widen()
...
do_opivx_widen() should return false if check function returns false.
Backports a69f97c1110205bc173657c77ce2d16877cad683
2021-03-08 12:13:16 -05:00
Frank Chang
98982dbe49
target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
...
Backports 1989205c4e973bc7f9fac0ce0700993f30582538
2021-03-08 12:12:36 -05:00
Frank Chang
d75c8e7fcf
target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
...
gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
Backports 7acafcfa844fd93f5ff073077007627338bd6739
2021-03-08 12:11:38 -05:00
LIU Zhiwei
dba0d32708
target/riscv: vector compress instruction
...
Backports 31bf42a26cf8b1e02f27acd302ee0ef14e877682
2021-03-07 12:47:46 -05:00
LIU Zhiwei
a68f111390
target/riscv: vector register gather instruction
...
Backports e4b83d5c0928507cc27a0f613675b117db9993e4
2021-03-07 12:45:36 -05:00
LIU Zhiwei
162ae6efd7
target/riscv: vector slide instructions
...
Backports ec17e03688ce4d0ae188db6d90b185b92a9a2087
2021-03-07 12:43:14 -05:00
LIU Zhiwei
0e0ac052cd
target/riscv: floating-point scalar move instructions
...
Backports 2843420a562c107801bae20f74579e4fe540316f
2021-03-07 12:41:23 -05:00
LIU Zhiwei
b75de9504c
target/riscv: integer scalar move instruction
...
Backports 9fc08be626a96ae1ac0cffb22f30ae652c1c645a
2021-03-07 12:38:41 -05:00
LIU Zhiwei
d61c1e91a8
target/riscv: integer extract instruction
...
Backports 90355f391d979ccd95d09ab42f647f103a3dbe69
2021-03-07 12:36:01 -05:00
LIU Zhiwei
5ff1871e32
target/riscv: vector element index instruction
...
Backports 126bec3f6ff3379e1a49f4a7d36922bfd079a3cc
2021-03-07 12:29:13 -05:00
LIU Zhiwei
2f7cdaee7b
target/riscv: vector iota instruction
...
Backports 78d90cfe859c8f5bd7baa0d41a4b5126e08eac24
2021-03-07 12:27:10 -05:00
LIU Zhiwei
ec24e09ce7
target/riscv: set-X-first mask bit
...
Backports 81fbf7daf2eccadd6480b90db95a2e8c410d4414
2021-03-07 12:25:09 -05:00
LIU Zhiwei
92d5ce9b66
target/riscv: vmfirst find-first-set mask bit
...
Backports 0db67e1c0c49011eb09c4f5b790eef15a2b4c351
2021-03-07 12:22:13 -05:00
LIU Zhiwei
782835889c
target/riscv: vector mask population count vmpopc
...
Backports 2e88f551df8fe6af81c0f920b7341ae2c75d00f2
2021-03-07 12:20:01 -05:00
LIU Zhiwei
68765e92c0
target/riscv: vector mask-register logical instructions
...
c21f34aebfb15c112131e36f425986170a3fcae9
2021-03-07 12:16:44 -05:00
LIU Zhiwei
4cbb4ae73d
target/riscv: vector widening floating-point reduction instructions
...
Backports 696b0c260a0312c865cd0e4a8f09d0b9f13b07c9
2021-03-07 12:12:49 -05:00
LIU Zhiwei
ebe125af76
target/riscv: vector single-width floating-point reduction instructions
...
Backports 523547f19e3914f11543e2da03907c724f15cd5e
2021-03-07 12:11:01 -05:00
LIU Zhiwei
798c1682f8
target/riscv: vector wideing integer reduction instructions
...
Backports bba718200b2d2aac6ab5031817f7125571c983a1
2021-03-07 12:09:15 -05:00
LIU Zhiwei
4b1e548fd0
target/riscv: vector single-width integer reduction instructions
...
Backports fe5c9ab1fc185e96bf7e034954127429ca74d386
2021-03-07 12:07:51 -05:00
LIU Zhiwei
e925927e23
target/riscv: narrowing floating-point/integer type-convert instructions
...
Backports 878d406ec28f945d262af4ffbea50b825d7a0825
2021-03-07 12:05:59 -05:00
LIU Zhiwei
0c80c49b1b
target/riscv: widening floating-point/integer type-convert instructions
...
Backports 4514b7b12390525e59e335e7ca58fd44f6e69272
2021-03-07 12:02:56 -05:00
LIU Zhiwei
8b06759ba4
target/riscv: vector floating-point/integer type-convert instructions
...
Backports 921009732614fd620c75f05496597796719544cf
2021-03-07 12:00:36 -05:00
LIU Zhiwei
fabc8bab77
target/riscv: vector floating-point merge instructions
...
Backports 64ab5846974140118c64e4d94ff2696932a0a58b
2021-03-07 11:58:41 -05:00
LIU Zhiwei
f9c9716534
target/riscv: vector floating-point classify instructions
...
Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c
2021-03-07 11:55:45 -05:00
LIU Zhiwei
b859be12b9
target/riscv: vector floating-point compare instructions
...
Backports 2a68e9e568faddf4d689a37fa6895bcb8404a677
2021-03-07 11:47:51 -05:00
LIU Zhiwei
31978f270b
target/riscv: vector floating-point sign-injection instructions
...
Backports 1d426b81f71eeeb1cbfec76c2f27ed0495719fb0
2021-03-07 11:43:47 -05:00
LIU Zhiwei
f7f0425a4d
target/riscv: vector floating-point min/max instructions
...
Backports 230b53ddd706c8b18a6d9beed1a0153b276d7037
2021-03-07 11:42:05 -05:00
LIU Zhiwei
69c73cfc4e
target/riscv: vector floating-point square-root instruction
...
Backports d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36
2021-03-07 11:40:04 -05:00
LIU Zhiwei
95a6d78121
target/riscv: vector widening floating-point fused multiply-add instructions
...
Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87
2021-03-07 11:37:23 -05:00
LIU Zhiwei
42116609f0
target/riscv: vector single-width floating-point fused multiply-add instructions
...
Backports 4aa5a8fed4a21fe2e132a9a21b251aa95e19de80
2021-03-07 11:34:56 -05:00
LIU Zhiwei
14cbabde4f
target/riscv: vector widening floating-point multiply
...
Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
2021-03-07 11:32:19 -05:00
LIU Zhiwei
5e4b142c31
target/riscv: vector single-width floating-point multiply/divide instructions
...
Backports 0e0057cbe2169195a08ae8247504e69f9b80542b
2021-03-07 11:30:14 -05:00
LIU Zhiwei
0de56731ae
target/riscv: vector widening floating-point add/subtract instructions
...
eeffab2ec1b332a5eb2d2dcd2732cdb57179c6eb
2021-03-07 11:27:33 -05:00
LIU Zhiwei
06092b88b9
target/riscv: vector single-width floating-point add/subtract instructions
...
Backports ce2a0343f441f0ee949690eabae5ab600397e2eb
2021-03-05 09:50:56 -05:00
LIU Zhiwei
5fb589cdd7
target/riscv: vector narrowing fixed-point clip instructions
...
Backports 9ff3d28739b760970f5e542c74a033470dca3f9b
2021-03-05 09:34:11 -05:00
LIU Zhiwei
241deddb50
target/riscv: vector single-width scaling shift instructions
...
Backports 04a614062dd5fb43f00bd955f44f7a2c3def016d
2021-03-05 09:32:15 -05:00
LIU Zhiwei
e7582a5d74
target/riscv: vector widening saturating scaled multiply-add
...
Backports 0a1eaf0036442b2bfa69df7fad9a5f1d6a4984f2
2021-03-05 09:29:42 -05:00
LIU Zhiwei
e27aadfa4f
target/riscv: vector single-width fractional multiply with rounding and saturation
...
Backports 9f0ff9e51480f8f1d2d7a62b11aa156fcdb4ef95
2021-03-05 09:26:56 -05:00
LIU Zhiwei
2343892c2e
target/riscv: vector single-width averaging add and subtract
...
Backports b7aee4819206cbb7adfdb624d4f2fa9918c25d43
2021-03-05 09:25:09 -05:00
