Commit graph

146 commits

Author SHA1 Message Date
Fabian Aggeler f120ad5308
target-arm: implement IRQ/FIQ routing to Monitor mode
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.

Backports commit de38d23b542efca54108ef28bcc0efe96f378d2e from qemu
2018-02-11 18:51:21 -05:00
Fabian Aggeler 4d9c9f893e
target-arm: move AArch32 SCR into security reglist
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.

Backports commit 0f1a3b2470d798ad5335eb9d6236f02ff64e31a8 from qemu
2018-02-11 18:48:33 -05:00
Fabian Aggeler 3494160ea6
target-arm: insert AArch32 cpregs twice into hashtable
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.

Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 18:41:25 -05:00
Peter Maydell fb78e79d72
target-arm: add secure state bit to CPREG hash
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.

Backports commit 51a79b039728277e35fd19f7a7b4bc6cb323697f from qemu
2018-02-11 18:35:52 -05:00
Fabian Aggeler 4f5106b56d
target-arm: add CPREG secure state support
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).

Also added secure state tracking field and flags. This allows for
identification of the register info secure state.

Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 18:29:35 -05:00
Sergey Fedorov acdd665668
target-arm: add non-secure Translation Block flag
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter <johannes.winter@iaik.tugraz.at>.

The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system register accesses.

Backports commit 3f342b9e0e64ad681cd39840bfa75ef12d2807c1 from qemu
2018-02-11 17:50:46 -05:00
Fabian Aggeler 90c47cb40f
target-arm: add banked register accessors
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.

- A32_BANKED macros are used for choosing the banked register based on provided
input security argument. This macro is used to choose the bank during
translation of MRC/MCR instructions that are dependent on something other
than the current secure state.
- A32_BANKED_CURRENT macros are used for choosing the banked register based on
current secure state. This is NOT to be used for choosing the bank used
during translation as it breaks monitor mode.

If EL3 is operating in AArch64 state coprocessor registers are not
banked anymore. The macros use the non-secure instance (_ns) in this
case, which is architecturally mapped to the AArch64 EL register.

Backports commit ea30a4b824ecc3c829b70eb9999ac5457dc5790f from qemu
2018-02-11 17:46:52 -05:00
Greg Bellows 67d68df401
target-arm: add async excp target_el function
Adds a dedicated function and a lookup table for determining the target
exception level of IRQ and FIQ exceptions. The lookup table is taken from the
ARMv7 and ARMv8 specification exception routing tables.

Backports commit 0eeb17d618361a0f4faddc160e33598b23da6dd5 from qemu
2018-02-11 17:45:09 -05:00
Lioncash 2d8f0be9f8
target-arm: extend async excp masking
This patch extends arm_excp_unmasked() to use lookup tables for determining
whether IRQ and FIQ exceptions are masked. The lookup tables are based on the
ARMv8 and ARMv7 specification physical interrupt masking tables.

If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels
other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3).

Backports commit 57e3a0c7cb0ac2f0288890482e0a463adce2080a from qemu
2018-02-11 17:38:59 -05:00
Richard Henderson 2c091e5fb8
target-arm: Add condexec state to insn_start
Backports commit 52e971d9ff67e340ac2a86bd67e14bd31c7991e0 from qemu
2018-02-11 15:13:40 -05:00
Richard Henderson dd1ec408e5
target-*: Increment num_insns immediately after tcg_gen_insn_start
This does tidy the icount test common to all targets.

Backports commit 959082fc4a93a016a6b697e1e0c2b373d8a3a373 from qemu
2018-02-11 12:46:30 -05:00
Richard Henderson a64d0ff657
target-*: Unconditionally emit tcg_gen_insn_start
While we're at it, emit the opcode adjacent to where we currently
record data for search_pc. This puts gen_io_start et al on the
"correct" side of the marker.

Backports commit 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 from qemu
2018-02-11 12:41:20 -05:00
Lioncash b3f9ff667b
tcg: Rename debug_insn_start to insn_start
With an eye toward making it mandatory.

Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu
2018-02-11 12:34:01 -05:00
Lioncash 3791fc69fd
target-arm: Use new revbit functions
Backports commit 42fedbca8f5b54324ed89be3484d4a3dc9946387 from qemu
2018-02-11 02:57:55 -05:00
Richard Henderson eb5ed2a844
target-arm: Use tcg_gen_extrh_i64_i32
Usually, eliminate an operation from the translator by combining
a shift with an extract.

In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF,
merely a non-zero value. Given that we can extract both halves of a
64-bit input in one call, this simplifies the code.

Backports commit 7cb36e18b2f1c1f971ebdc2121de22a8c2e94fd6 from qemu
2018-02-11 02:57:54 -05:00
Richard Henderson b94da3fc13
target-arm: Recognize ROR
Backports commit 8fb0ad8e16ab3d03433244a1a03e1df757342ad8 from qemu
2018-02-11 02:57:33 -05:00
Richard Henderson 3173269986
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
For !SF, this initial ext32u can't be optimized away by the
current TCG code generator. (It would require backward bit
liveness propagation.)

Backports commit d3a77b42decd0cbfa62a5526e67d1d6d380c83a9 from qemu
2018-02-11 01:35:58 -05:00
Richard Henderson c637a97270
target-arm: Recognize UXTB, UXTH, LSR, LSL
These are all special case aliases of UBFM.

Backports commit 9924e85829fe21b5f38a5d267c9aea44c5d478ac from qemu
2018-02-11 01:34:11 -05:00
Richard Henderson d9e4e70636
target-arm: Recognize SXTB, SXTH, SXTW, ASR
These are all special case aliases of SBFM.

Backports commit ef60151bee9a95e3a5cc98b345a19ed7eb435ddb from qemu
2018-02-11 01:31:54 -05:00
Richard Henderson 5ee72ff9f5
target-arm: Implement fcsel with movcond
Backports commit 6e061029d74455d83f6fa070ac33de7a356cf60d from qemu
2018-02-11 01:29:14 -05:00
Richard Henderson 53bd2b1d5c
target-arm: Implement ccmp branchless
This can allow much of a ccmp to be elided when particular
flags are subsequently dead.

Backports commit 7dd03d773e0dafae9271318fc8d6b2b14de74403 from qemu
2018-02-11 01:25:51 -05:00
Richard Henderson 2c71ddefb1
target-arm: Use setcond and movcond for csel
Backports commit 259cb68491ab36427e7e5d820fe543d53b006ec6 from qemu
2018-02-10 23:57:11 -05:00
Richard Henderson 70dd48b855
target-arm: Handle always condition codes within arm_test_cc
Handling this with TCG_COND_ALWAYS will allow these unlikely
cases to be handled without special cases in the rest of the
translator. The TCG optimizer ought to be able to reduce
these ALWAYS conditions completely.

Backports commit 9305eac09e61d857c9cc11e20db754dfc25a82db from qemu
2018-02-10 23:48:10 -05:00
Lioncash 94f1227f7a
target-arm: Introduce DisasCompare
Split arm_gen_test_cc into 3 functions, so that it can be reused
for non-branch TCG comparisons.

Backports commit 6c2c63d3a02c79e9035ca0370cc549d0f938a4dd from qemu
2018-02-10 23:45:47 -05:00
Richard Henderson a3aaf5a864
tcg: Remove tcg_gen_trunc_i64_i32
Replacing it with tcg_gen_extrl_i64_i32.

Backports commit ecc7b3aa71f5fdcf9ee87e74ca811d988282641d from qemu
2018-02-10 23:11:02 -05:00
Richard Henderson ac713c7034
tcg: Push merged memop+mmu_idx parameter to softmmu routines
The extra information is not yet used but it is now available.
This requires minor changes through all of the tcg backends.

Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu
2018-02-10 20:03:22 -05:00
Richard Henderson 232632e76c
tcg: Change translator-side labels to a pointer
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.

Note that the code generating backends still manipulate labels as int.

With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.

Backports commit 42a268c241183877192c376d03bd9b6d527407c7 from qemu
2018-02-09 14:17:56 -05:00
Lioncash 0273e6ae18
tcg: Put opcodes in a linked list
The previous setup required ops and args to be completely sequential,
and was error prone when it came to both iteration and optimization.
2018-02-09 12:54:05 -05:00
Richard Henderson a41b9acc0c
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
The method by which we count the number of ops emitted
is going to change. Abstract that away into some inlines.

Backports commit fe700adb3db5b028b504423b946d4ee5200a8f2f from qemu.
2018-02-09 09:31:17 -05:00
Richard Henderson 78378289e3
tcg: Move emit of INDEX_op_end into gen_tb_end
Backports commit 0a7df5da986bd7ee0789f2d7b8611f2e8eee5046 from qemu
2018-02-09 08:51:01 -05:00
Richard Henderson 6b4b493dae
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Thus, use cpu_env as the parameter, not TCG_AREG0 directly.
Update all uses in the translators.

Backports commit e1ccc05444676b92c63708096e36582be27fbee1 from qemu
2018-02-08 12:33:33 -05:00
Richard Henderson afb67fc002
target/arm: Fix aa64 ldp register writeback
Backports commit 3e4d91b94ce400326fae0850578d9e9f30a71adb from qemu
2018-02-08 08:29:51 -05:00
Eric Blake 37cdcbf771
maint: Fix macros with broken 'do/while(0); ' usage 2018-02-07 20:27:37 -05:00
Lioncash 0f453b0595
target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
Backports commit 9a2b5256ea1f68c89d5da4b54f180f576c2c82d6 from qemu
2018-02-07 10:09:26 -05:00
Lioncash dd577f5ea5
target/arm: Change the type of vfp.regs
Backports commit 3f68b8a5a6862f856524bb347bf348ae364dd43c from qemu
2018-02-07 09:57:43 -05:00
Lioncash ef07c136b6
target/arm: Add fp16 support to vfp_expand_imm
Backports commit 8081796a75414f9ed5ec3d97158e543ed45908ec from qemu.
2018-02-07 09:47:04 -05:00
Lioncash b55f35ba92
target/arm: Split out vfp_expand_imm
Backports commit e90a99fe6bde9b85bff8c052ade51520f20d9bce from qemu.
2018-02-07 09:44:52 -05:00
Lioncash 4c165ed788
translate-a64: Silence unused variable warning 2018-02-06 08:38:01 -05:00
Merry 29d38d7c22
Merge pull request #10 from lioncash/el-busto-ldst-exclusive
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks
2018-02-05 20:59:25 +00:00
Merry 82c4212ce3
Merge pull request #8 from lioncash/optimize
Backport REV16 optimizations from qemu
2018-02-05 20:58:58 +00:00
Lioncash 1e451b386a
translate-a64: Backport fix for incorrect load/store exclusive unallocated checks
Backports commit e14f0eb12f920fd96b9f79d15cedd437648e8667 from qemu
2018-02-04 23:17:45 -05:00
Lioncash 5a37b8c28e
Backport optimizations to AArch32's REV16 handling
Backports commit 68cedf733ae32363ccf54f0b52c8a424d5ec98ed from qemu
2018-02-04 14:53:28 -05:00
Lioncash 4a8a92bad2
Backport optimizations to AArch64's REV16 handling
Backports commits abb1066df313602ef0ca631126bd342d399d5359 and e4256c3cbf7eefebc0bc6e1f472c47c6dd20b996 from qemu.
2018-02-04 14:45:39 -05:00
Lioncash 122d54e23e
Backport the SVE feature flag
Backports commit 0d0a16c647650d476219a5e1313dec434f9fbebb in qemu to unicorn
2018-02-02 08:52:15 -05:00
Lioncash 4fb2fbfacf
Backport the JAZELLE feature flag
Backports commit c99a55d38dd5b5131f3fcbbaf41828a09ee62544 in qemu to unicorn
2018-02-02 08:50:18 -05:00
Lioncash 84319130cd
Backport the M_SECURITY feature flag
Backports relevant parts from commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f in qemu to unicorn
2018-02-02 08:44:46 -05:00
Lioncash 20038fb801
Backport the PMU feature flag
Backports the applicable code from commit 929e754d5a621cd53f30e69b766ccf381b58d124 to unicorn
2018-02-02 08:28:27 -05:00
Lioncash 35100ce4e0
Backport the VBAR feature flag
Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn
2018-02-02 08:24:12 -05:00
Lioncash 291b5753eb
Backport the THUMB_DSP feature flag
Backports commit 62b44f059a84d1ac580a653fc4110dfabaef6b83 in qemu to unicorn.
2018-02-02 07:59:26 -05:00
Lioncash 438e2836e0
helper_a64: Fix CRC32's implementation 2018-01-29 09:24:36 -05:00