Commit graph

162 commits

Author SHA1 Message Date
Fredrik Noring baf2fe0fc1
target/mips: Introduce 32 R5900 multimedia registers
The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Backports commit a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd from qemu
2019-01-22 20:14:56 -05:00
Aleksandar Markovic 3bf320249e
target/mips: Rename 'rn' to 'register_name'
Rename 'rn' to 'register_name' in CP0-related handlers.

Backports commit 294fc2ea7f8af913523bf004433704377d9ee7a8 from qemu
2019-01-22 19:57:42 -05:00
Aleksandar Markovic 3a276522ac
target/mips: Amend preprocessor constants for CP0 registers
Correct existing CP0-related preprocessor constants (replace
"CPO" with "CP0" (form letter "O" to digit "0", when needed).
Besides, add preprocessor constants for CP0 subregisters.
The names of the subregisters were chosen to be in sync with
the table of corresponding assembler mnemonics found in the
documentation for I6500 and I6400 (release 1.0).

Backports commit 04992c8cd1c43ecdba39dd8c916db092db6ebae0 from qemu
2019-01-22 19:55:04 -05:00
Yongbok Kim 33e9ea3f10
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
Provide R/W access to SAARI and SAAR CP0 registers.

Backports commit 5fb2dcd17921be71b55fb62d59a12992707d2d3e from qemu
2019-01-22 19:51:38 -05:00
Aleksandar Markovic c0125e41a1
target/mips: Use preprocessor constants for 32 major CP0 registers
Use preprocessor constants for 32 major CP0 registers.

Backports commit 46d7642fcc97ac108c8080fbe41bc5d00bb537f2 from qemu
2019-01-22 19:38:43 -05:00
Fredrik Noring ee4b59e981
target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions
The three-operand MADD and MADDU are specific to R5900 cores.

Backports commit a95c4c26f1dc233987350e7cb1cf62d46ade5ce5 from qemu
2019-01-05 08:07:56 -05:00
Philippe Mathieu-Daudé 76bc93690f
target/mips: Support R5900 three-operand MADD and MADDU instructions
The three-operand MADD and MADDU are specific to Sony R5900 core,
and Toshiba TX19/TX39/TX79 cores as well.

The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf

Backports commit 3b948f053fc588154d95228da8a6561c61c66104 from qemu
2019-01-05 08:03:43 -05:00
Aleksandar Markovic 5729c803a7
target/mips: MXU: Add handler for an align instruction
Add translation handler for S32ALNI MXU instruction.

Backports commit 79f5fee7a3c53494c7ca4bc18c72944f5e2d5c2f from qemu
2019-01-05 08:00:09 -05:00
Aleksandar Markovic 94956d81f6
target/mips: MXU: Add handlers for max/min instructions
Add translation handlers for six max/min MXU instructions.

Backports commit bb84cbf38505bd1d800fdddcd81407a99e5c2142 from qemu
2019-01-05 07:55:39 -05:00
Aleksandar Markovic bf7da7bf57
target/mips: MXU: Add handlers for logic instructions
Add translation handlers for four logic MXU instructions.

It should be noted that there is an error in MXU documentation (dated
June 2017) regarding opcodes for this group of instructions. This was
confirmed by running tests on hardware, and also by looking up other
related public source trees (binutils, Android NDK). In initial MXU
patches to QEMU, opcodes for MXU logic instructions were created to
be in accordance with the MXU documentation, therefore the error from
was propagated. This patch corrects that, changing the involved code.
Besides that, as MXU was designed and implemented only for 32-bit
CPUs, corresponding preprosessor conditions were added around MXU
code, which allows more flexible implementation of MXU handlers.

Backports commit b621f0187ef789aeef733cf79e5ac83984752394 from qemu
2019-01-05 07:48:08 -05:00
Aleksandar Markovic ba253dd0d3
target/mips: MXU: Improve the comment containing MXU overview
Improve textual description of MXU extension. These are mostly
comment formatting changes.

Backports commit 84e2c895b12fb7056daeb7e5094656eae7b50d3d from qemu
2019-01-05 07:39:47 -05:00
Aleksandar Markovic 57bb979ce8
target/mips: MXU: Add generic naming for optn2 constants
Add generic naming involving generig suffixes OPTN0, OPTN1, OPTN2,
OPTN3 for four optn2 constants. Existing suffixes WW, LW, HW, XW
are not quite appropriate for some instructions using optn2.
2019-01-05 07:35:49 -05:00
Aleksandar Markovic b5e1ea2e08
target/mips: MXU: Add missing opcodes/decoding for LX* instructions
Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,
and LXHU instructions. They were for some reason forgotten in
previous commits. The MXU opcode list and decoding engine should
be now complete.

Backports commit c233bf07af7cf2358b69c38150dbd2e3e4a399b6 from qemu
2019-01-05 07:34:07 -05:00
Aleksandar Markovic 3b89ca7188
target/mips: Rename MMI-related functions
Rename MMI-related functions.

Backports commit 874b28797045f574adb10b69c28006ca143f9280 from qemu
2018-11-23 18:54:02 -05:00
Aleksandar Markovic f51b980772
target/mips: Rename MMI-related opcodes
Rename MMI-related opcodes.

Backports commit baa609db75057b6a84c1867049e85d553b990090 from qemu
2018-11-23 18:49:13 -05:00
Aleksandar Markovic 8f8c6e3bb5
target/mips: Rename MMI-related masks
Rename MMI-related masks.

Backports commit c8341e00007f51e777b8b00b3fc3f475b3684001 from qemu
2018-11-23 18:41:55 -05:00
Fredrik Noring ed586cfa46
target/mips: Guard check_insn with INSN_R5900 check
Explicitely mark handling of PREF instruction for R5900 as
treating the same as NOP.

Backports commit 992e8176d36882983bb04f0259f7151a36d003a1 from qemu
2018-11-23 18:39:37 -05:00
Fredrik Noring a79d4b6fe7
target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
Avoid using check_opc_user_only() as a decision making code wrt
various architectures. Use ctx->insn_flags checks instead.

Backports commit 55fc7a69aa38f5ec726e862caf4e4394caca04a8 from qemu
2018-11-23 18:38:08 -05:00
Fredrik Noring b671293fe0
target/mips: Fix decoding mechanism of special R5900 opcodes
MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
instead of the generic decode_opc_special_legacy.

Backports commit 9dc324ce66807cc231fe890d4031de595ad1cf72 from qemu
2018-11-23 18:35:55 -05:00
Fredrik Noring f23c6fd006
target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.

Backports commit c42171c3bfe6fdc94c183f664c4d6548f8c5488b from qemu
2018-11-23 18:33:35 -05:00
Fredrik Noring 3d637206bd
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.

Backports commit 86efbfb619a42061ac6439c074cfbf52df2ef2c2 from qemu
2018-11-23 18:29:01 -05:00
Aleksandar Markovic 9137e4c201
target/mips: Amend MXU ASE overview note
Add prefix, suffix, operation descriptions, and other corrections
and amendments to the comment that describes MXU ASE.

Backports commit 093ade12179b6a3f679c100c0fe2a0a7d72068ba from qemu
2018-11-11 07:30:31 -05:00
Aleksandar Markovic 702abac53f
target/mips: Move MXU_EN check one level higher
Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.

Backports commit e5bf8a08293a1c576f8b6094f4deae7bdafceade from qemu
2018-11-11 07:29:11 -05:00
Craig Janeczek f2c3e173ad
target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Backports commit 4ca837218c92139cb85d214a25d1d1bc3f7e044c from qemu
2018-11-11 07:24:27 -05:00
Craig Janeczek bd75529f43
target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
Backports commit a9a4181bdbf9eea81d718894bda607bd01b00f5b from qemu
2018-11-11 07:21:44 -05:00
Craig Janeczek 97b7155db1
target/mips: Add emulation of MXU instruction D16MAC
Backports commit e67915b4277932def37b15cf8434323d096edeaa from qemu
2018-11-11 07:18:12 -05:00
Craig Janeczek db2e8c1761
target/mips: Add emulation of MXU instruction D16MUL
Backports commit 72c9bcf89c59ee1a8e4545069de3efcbeb4d4833 from qemu
2018-11-11 07:00:00 -05:00
Craig Janeczek cad0283888
target/mips: Add emulation of MXU instruction S8LDD
Backports commit be57bcdb2ed8a4b41be05c8dc42bdec5174f43d6 from qemu
2018-11-11 06:15:57 -05:00
Aleksandar Markovic 914c0cea7c
target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Backports commit 87860df5511b972f0234a6b2cfaad5227c79b6b4 from qemu
2018-11-11 06:12:44 -05:00
Craig Janeczek 3862cd205d
target/mips: Add emulation of MXU instructions S32I2M and S32M2I
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.

Backports commit 96992d1aa1b250c0fffc1ff2dad5e6e4f0b9815b from qemu
2018-11-11 06:11:09 -05:00
Craig Janeczek 8a03757fb0
target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Backports commit 11d56f61036091206f085e58cff72b6872911d3a from qemu
2018-11-11 06:05:45 -05:00
Craig Janeczek 839f5babde
target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
Backports commit 53f1131fde02ae49e1f794f811a60fda32c72dca from qemu
2018-11-11 06:04:47 -05:00
Craig Janeczek bc98daa7c5
target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
Backports commit a35723f4ce026ebad0c34f18ea874813799058f0 from qemu
2018-11-11 06:04:18 -05:00
Aleksandar Markovic 9cf4a32b0d
target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
Backports commit 5bb29992397217ae7d09d2192c5b56aefaf6cd11 from qemu
2018-11-11 06:03:47 -05:00
Craig Janeczek bbb2a1e62b
target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
Backports commit b70bb918e2f5063975ba845fb9456ada25e3db91 from qemu
2018-11-11 06:03:08 -05:00
Aleksandar Markovic 5e92fd655f
target/mips: Add MXU decoding engine
Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.

Backports commit 03f400883a1dd92fac5b0d9127b38e34c9a722d7 from qemu
2018-11-11 06:01:58 -05:00
Aleksandar Markovic 1029b4151d
target/mips: Add and integrate MXU decoding engine placeholder
Provide the placeholder and add the invocation logic for MXU
decoding engine.

Backports commit 0a348b9a4e115deb28856e650b8fe5277e291c23 from qemu
2018-11-11 05:59:20 -05:00
Aleksandar Markovic ed037799c7
target/mips: Amend MXU instruction opcodes
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.

Backports commit eab0bdb07cbed1131be2d1f541059c7b96b05e32 from qemu
2018-11-11 05:58:35 -05:00
Craig Janeczek 58dc377890
target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Backports commit eb5559f67dc8dc12335dd996877bb6daaea32eb2 from qemu.
2018-11-11 05:50:52 -05:00
Aleksandar Markovic a1ba04ae44
target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
Coverity found two fallthroughs that miss break statement. Fix them.

Backports commit 2431a422d325c1832d77dd64fa3135ec303b00de from qemu
2018-11-11 05:44:23 -05:00
Dimitrije Nikolic 948d49db81
target/mips: Implement emulation of nanoMIPS EVA instructions
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.

Backports commit d046a9ea1b8877a570a8b12a2d0125ec59fe5b22 from qemu
2018-11-10 12:18:11 -05:00
Aleksandar Markovic 006f0a5873
target/mips: Add nanoMIPS CRC32 instruction pool
Backports commit ba1e81171fb761aea9a9a4ccadedf808e34eaae2 from qemu
2018-11-10 12:15:01 -05:00
Aleksandar Markovic 9f728678ec
target/mips: Fix decoding of ALIGN and DALIGN instructions
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.

Backports commit 373ecd3823f949fd550ec49685299e287af5753e from qemu
2018-11-10 12:14:01 -05:00
Aleksandar Markovic caa67a9d17
target/mips: Fix the title of translate.c
Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.

Backports commit ab99e0e44bc7b0e2e52d9083a673866b18470536 from qemu
2018-11-10 12:12:27 -05:00
Fredrik Noring e9a4475a35
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU plays the role of the
kernel in user mode, so those traps are emulated by accepting the
instructions.

This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception for flagged CPUs in QEMU system mode.

The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.

Backports commit 96631327be14c4f54cc31f873c278d9ffedd1e00 from qemu
2018-11-10 12:10:01 -05:00
Fredrik Noring cb7b097204
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.

Backports commit 5601e6217d90ed322b4b9a6d68e8db607db91842 from qemu
2018-11-10 12:08:14 -05:00
Fredrik Noring 296d8bd729
target/mips: Support R5900 DIV1 and DIVU1 instructions
Backports commit be9c42c90d162100a63111ddeb8bfe50be897873 from qemu
2018-11-10 12:07:24 -05:00
Fredrik Noring b42c8e80b8
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
Backports commit 8d927f7cb4b3ec06d6a7cf71221fd6a48e9a8fb5 from qemu
2018-11-10 12:06:20 -05:00
Fredrik Noring 3914d65fb9
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
Add support for MULT1 and MULTU1 instructions.

Backports commit 06de726b2d4da185dfec9d06b5f1032059ad3554 from qemu
2018-11-10 12:04:28 -05:00
Fredrik Noring 91cd7c20e5
target/mips: Support R5900 three-operand MULT and MULTU instructions
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.

Likewise, the R5900-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.

Backports commit 21e8e8b230af38b6bd8c953fa5f31e4a5a128e1c from qemu
2018-11-10 11:57:54 -05:00