Commit graph

86 commits

Author SHA1 Message Date
Catena cyber 2c9b6df879
Mips undefined shift fix
Backports commit 46999575fb9e82ccd925e835d0d7db47200e010d from unicorn
2018-10-06 05:00:27 -04:00
Lioncash b62e892b20
mips: Use DisasContext for parameters in place of TCGContext where applicable
This is more future-friendly with qemu's main repo, as it's more
generic.
2018-10-06 04:37:28 -04:00
Dimitrije Nikolic 7e0342c9f6
target/mips: Add availability control via bit NMS
A set of nanoMIPS instructions is not available if Config5 bit NMS
is set.

Backports commit fb32f8c8560be7ca4e323cee1b839701126401d1 from qemu
2018-08-27 14:59:15 -04:00
Stefan Markovic 38f2640a34
target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
Add emulation of DSP ASE instructions for nanoMIPS - part 6.

Backports commit 0b591184a2d0686b8f2c5fb27cc9fe2f60752d57 from qemu
2018-08-27 06:47:59 -04:00
Stefan Markovic ba7d8bc0ab
target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
Add emulation of DSP ASE instructions for nanoMIPS - part 5.

Backports commit 4c75c985d9b4d2ac7e0183083e31c243b06a3f2b from qemu
2018-08-27 06:45:25 -04:00
Stefan Markovic 73a5efd599
target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
Add emulation of DSP ASE instructions for nanoMIPS - part 4.

Backports commit 8b3698b2947610e0645a65ace4822164d55dd76b from qemu
2018-08-27 06:43:34 -04:00
Stefan Markovic b6602fff1f
target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
Add emulation of DSP ASE instructions for nanoMIPS - part 3.

Backports commit 2ed42efaae9516b71b7edf669b120cad718ba37b from qemu
2018-08-27 06:34:14 -04:00
Stefan Markovic 33dee2e5f3
target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
Add emulation of DSP ASE instructions for nanoMIPS - part 2.

Backports commit 6d033ca7513d85562f1b6bbb002a38b1c2541e5d from qemu
2018-08-27 05:53:17 -04:00
Stefan Markovic 49f448af3c
target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
Add emulation of DSP ASE instructions for nanoMIPS - part 1.

Backports commit 3285a3e4445be70d5f2dbdd29249e1e2627a5216 from qemu
2018-08-27 05:52:12 -04:00
Stefan Markovic 795d903f1c
target/mips: Implement MT ASE support for nanoMIPS
Add emulation of MT ASE instructions for nanoMIPS.

Backports commit 0a1a6ed78ae13a87f23810899a838f8d0c0fa2a5 from qemu
2018-08-27 05:39:15 -04:00
Aleksandar Rikalo 8c0248696a
target/mips: Fix pre-nanoMIPS MT ASE instructions availability control
Use bits from configuration registers for availability control
of MT ASE instructions, rather than only ISA_MT bit in insn_flags.
This is done by adding a field in hflags for MT bit, and adding
functions check_mt() and check_cp0_mt().

Backports commit 9affc1c59279f482ff145e0371926f79b6448e3e from qemu
2018-08-27 05:36:38 -04:00
Stefan Markovic 93f7cd2307
target/mips: Add emulation of nanoMIPS 32-bit branch instructions
Add emulation of various flavors of nanoMIPS 32-bit branch
instructions.

Backports commit 11d0fc10b7efe3d0404a71e855c0d9f521ce3d66 from qemu
2018-08-27 05:34:52 -04:00
Aleksandar Rikalo 371bb5a134
target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside
adding core functionality of these instructions, this patch adds
support for availability control via configuration bit XNP.

Backports commit 0b16dcd180bdbe3add9edea42c2374d427882661 from qemu
2018-08-27 05:25:14 -04:00
Dimitrije Nikolic 128bfa00d2
target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.

Backports commit ab77fc611bf004dfd25ecad5b2c11261e32012e9 from qemu
2018-08-27 05:20:26 -04:00
Yongbok Kim e18c921501
target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
Add emulation of various nanoMIPS load and store instructions.

Backports commit 8f1d9b6d63978b80971b15fef16636f454241879 from qemu
2018-08-27 05:18:55 -04:00
James Hogan bcdee16199
target/mips: Implement emulation of nanoMIPS EXTW instruction
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).

Backports commit 821f2008c3c708e0e33158039ab55673a0f04519 from qemu
2018-08-27 05:14:54 -04:00
Matthew Fortune 06e5835cc7
target/mips: Implement emulation of nanoMIPS ROTX instruction
Added a helper for ROTX based on the pseudocode from the
architecture spec. This instraction was not present in previous
MIPS instruction sets.

Backports commit e222f5067269392af489731221750976d0cf3c05 from qemu
2018-08-27 05:11:14 -04:00
Yongbok Kim e9442a5ca9
target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.

Backports commit eac5266459fb83e70fbf33f95c7c846f89df5c6a from qemu
2018-08-27 05:07:40 -04:00
Yongbok Kim db0ca1924e
target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)
Add emulation of misc nanoMIPS instructions situated in pool32axf.

Backports commit 642241870a029da1525ad1641e1c99d434580817 from qemu
2018-08-27 05:02:08 -04:00
Yongbok Kim a2ff65acec
target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)
Add emulation of nanoMIPS instructions that are situated in pool32a0.

Backports commit e0cf0e6586d6a2c7e56b58bdfb5a67cec04c2999 from qemu
2018-08-27 04:59:06 -04:00
Yongbok Kim aee648c5ee
target/mips: Add emulation of nanoMIPS FP instructions
Add emulation of basic floating point arithmetic for nanoMIPS.

Backports commit 579b8ea97a0a4b8e4b9e18d282ab0dc7138d41d1 from qemu
2018-08-27 04:55:19 -04:00
Yongbok Kim d77363e1ae
target/mips: Add emulation of nanoMIPS 48-bit instructions
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.

Backports commit 7ef009b2dd72852505c7348c0bd1f8eb1e62a064 from qemu
2018-08-27 04:53:02 -04:00
Yongbok Kim 6c31da99e3
target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV
Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV.

Backports commit 4d18232ca0f903df099d243ccfe28b0e545dc92d from qemu
2018-08-27 04:50:32 -04:00
Yongbok Kim 48d61aee0b
target/mips: Add emulation of some common nanoMIPS 32-bit instructions
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,
ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.

Backports commit c0280983034627a336248409711e969eb2ea8325 from qemu
2018-08-27 04:48:39 -04:00
Stefan Markovic 6b5dbbf6a3
target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions
Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines
gen_save(), gen_restore(), and gen_adjust_sp() are provided to support
this feature.

This patch at the same time provides function gen_op_addr_addi(). This
function will be used in emulation of some other nanoMIPS instructions.

Backports commit bf0718c59a4b27dd01346a7b5b9a183ed1b18fb7 from qemu
2018-08-27 04:43:27 -04:00
Yongbok Kim b4fa0bfbba
target/mips: Add emulation of nanoMIPS 16-bit logic instructions
Add emulation of NOT16, AND16, XOR16, OR16 instructions.

Backports commit 80845edf37bac0c1e8d378046bd2b741e4deefc8 from qemu
2018-08-27 04:35:58 -04:00
Yongbok Kim 038cc8df4d
target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16,
LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions.

Backports commit 8bdb7029c3b73327ba39a59fdc2c6ee3d64b2b24 from qemu
2018-08-27 04:34:18 -04:00
Yongbok Kim 9e82494344
target/mips: Add emulation of nanoMIPS 16-bit misc instructions
Add emulation of misc nanoMIPS 16-bit instructions.

Backports commit 8869ad02bfd9737f6a8fceab5ca286eaa899b790 from qemu
2018-08-27 04:31:35 -04:00
Yongbok Kim 25d95b6971
target/mips: Add emulation of nanoMIPS 16-bit shift instructions
Add emulation of nanoMIPS 16-bit shift instructions.

Backports commit c46562fb2fd41429c7acbf10dedfd5cbe0aa34fa from qemu
2018-08-27 04:29:59 -04:00
Stefan Markovic 2bf4a1b0a8
target/mips: Add emulation of nanoMIPS 16-bit branch instructions
Add emulation of nanoMIPS 16-bit branch instructions.

Backports commit 764371d24c51336c7713eb6f350218683871d05e from qemu
2018-08-27 04:28:22 -04:00
Yongbok Kim bd803a32e5
target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions
Add emulation of nanoMIPS 16-bit arithmetic instructions.

Backports commit ea4ca3c22646f5826e4adbfa006b564a5d38da8f from qemu
2018-08-27 04:20:02 -04:00
Aleksandar Markovic bfc5637339
target/mips: Add nanoMIPS decoding and extraction utilities
Add some basic utility functions and macros for nanoMIPS decoding
engine.

Backports commit 6bfa9f4c9cf24d6cfaaa227722e9cdcca1ad6fe9 from qemu
2018-08-27 04:17:19 -04:00
Aleksandar Markovic 5decf2e0ed
target/mips: Add placeholder and invocation of decode_nanomips_opc()
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.

Backports commit c533c0f4741be62501ef6c7f6ce77ffbfc2e4964 from qemu
2018-08-27 04:16:29 -04:00
Stefan Markovic 2389a5468c
target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS
Only if Config3.ISA is 3 (microMIPS), the mode should be switched in
cpu_state_reset(). Config3.ISA is 1 for nanoMIPS processors, and no mode
change should happen.

Backports commit 0bbc0396809f6caaaf96863dafe738e94f9b73ea from qemu
2018-08-27 04:15:31 -04:00
Stefan Markovic b3f59dae30
target/mips: Add nanoMIPS DSP ASE opcodes
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.

Backports commit b3979b6fc3faf286968a239d09c7adf36d0fade6 from qemu
2018-08-27 04:14:35 -04:00
Yongbok Kim 89cc42c8e2
target/mips: Add nanoMIPS base instruction set opcodes
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called
instruction pools. Each pool contains a set of opcodes, that in turn
can be instruction opcodes or instruction pool opcodes.

Backports commit 261c95a0e98e5e9b13c9c005a991b7e7dc27f38a from qemu
2018-08-27 04:12:53 -04:00
Yongbok Kim eb775926fd
target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.

Backports commit 59488dda1f16c0259bc2610d8d71686ef436c649 from qemu
2018-08-17 14:25:22 -04:00
Stefan Markovic dbebd7f27f
target/mips: Implement CP0 Config1.WR bit functionality
Add testing Config1.WR bit into watch exception handling logic.

Backports commit fa192d4974de3ace960d03803ab9d2f09abd9282 from qemu
2018-08-17 14:23:35 -04:00
Aleksandar Markovic af31bc3982
target/mips: Fix two instances of shadow variables
Fix two instances of shadow variables. This cleans up entire file
translate.c from shadow variables.

Backports commit e1555d7ddf2c86fb92165e47eb092f1f5fa9e8bd from qemu
2018-08-17 14:18:38 -04:00
Aleksandar Markovic 0fd3ae0efb
target/mips: Mark switch fallthroughs with interpretable comments
Mark switch fallthroughs with comments, in cases fallthroughs
are intentional.

The comments "/* fall through */" are interpreted by compilers and
other tools, and they will not issue warnings in such cases. For gcc,
the warning is turnend on by -Wimplicit-fallthrough. With this patch,
there will be no such warnings in target/mips directory. If such
warning appears in future, it should be checked if it is intentional,
and, if yes, marked with a comment similar to those from this patch.

The comment must be just before next "case", otherwise gcc won't
understand it.

Backports commit 146dd620db815558938433eb9f57a571d424d2c6 from qemu
2018-08-17 14:17:45 -04:00
Aleksandar Rikalo 0f118a005b
target/mips: Avoid case statements formulated by ranges - part 2
Remove "range style" case statements to make code analysis easier.
This patch handles cases when the values in the range in question
were not properly defined.

Backports commit c38a1d52233c85976eeed99c9015e881de8cd68e from qemu
2018-08-17 14:16:40 -04:00
Aleksandar Markovic 0259ce5b6d
target/mips: Avoid case statements formulated by ranges - part 1
Remove "range style" case statements to make code analysis easier.

This is needed also for some upcoming nanoMIPS-related refactorings.

Backports commit c2e19f3c2b1a1bb5f4fc3c55ee8cfa28dde9b810 from qemu
2018-08-17 14:14:11 -04:00
Yongbok Kim a63e549673
target/mips: Fix data type for offset
Offset can be larger than 16 bit from nanoMIPS,
and immediate field can be larger than 16 bits as well.

Backports commit 72e1f16f18fe62504f8f25d7a3f6813b24b221be from qemu
2018-07-03 01:01:09 -04:00
Yongbok Kim f2d68a4079
target/mips: Update gen_flt_ldst()
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS

Backports commit b52d3bfa2d54d99ef25f6d008815eecc53b67bfe from qemu
2018-07-03 00:59:47 -04:00
Yongbok Kim a246bdb5b3
target/mips: Fix microMIPS on reset
Fix to activate microMIPS on reset when Config3.ISA == {1, 3}

Backports commit 0305d194be1dbda09fa7a7c883894030d07c355f from qemu
2018-07-03 00:57:50 -04:00
Richard Henderson 10e2b13650
tcg: Pass tb and index to tcg_gen_exit_tb separately
Do the cast to uintptr_t within the helper, so that the compiler
can type check the pointer argument. We can also do some more
sanity checking of the index argument.

Backports commit 07ea28b41830f946de3841b0ac61a3413679feb9 from qemu
2018-06-07 11:56:32 -04:00
Emilio G. Cota bb95f85569
target/mips: convert to TranslatorOps
Notes:

- DISAS_TOO_MANY replaces the former "break" in the translation loop.
However, care must be taken not to overwrite a previous condition
in is_jmp; that's why in translate_insn we first check is_jmp and
return if it's != DISAS_NEXT.

- Added an assert in translate_insn, before exiting due to an exception,
to make sure that is_jmp is set to DISAS_NORETURN (the exception
generation function always sets it.)

- Added an assert for the default case in is_jmp's switch.

Backports commit 18f440edfb974feaff8490d4861844b5a2b7a3b5 from qemu
2018-05-12 16:42:21 -04:00
Emilio G. Cota 2c93423acd
target/mips: use *ctx for DisasContext
No changes to the logic here; this is just to make the diff
that follows easier to read.

While at it, remove the unnecessary 'struct' in
'struct TranslationBlock'.

Note that checkpatch complains with a false positive:
ERROR: space prohibited after that '&' (ctx:WxW)
\#75: FILE: target/mips/translate.c:20220:
+ ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
^

Backports commit 12be92588cf26a192f1b62846906983fc1e102a7 from qemu
2018-05-12 16:26:06 -04:00
Emilio G. Cota dae6b84c14
target/mips: convert to DisasContextBase
Backports commit eeb3bba8477cebc46c482ef37d565d54e771c2d3 from qemu
2018-05-12 16:18:00 -04:00
Emilio G. Cota de5d90f9a4
target/mips: convert to DisasJumpType
Notes:

- BS_EXCP in generate_exception_err and after hen_helper_wait
becomes DISAS_NORETURN, because we do not return after
raising an exception.

- Some uses of BS_EXCP are misleading in that they're used
only as a "not BS_STOP" exit condition, i.e. they have nothing
to do with an actual exception. For those cases, define
and use DISAS_EXIT, which is clearer. With this and the
above change, BS_EXCP goes away completely.

- fix a comment typo (s/intetrupt/interrupt/).

Backports commit b28425babc2ad4b90cd87d07a1809d3322b9c065 from qemu
2018-05-11 16:17:02 -04:00