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unicorn/qemu/target/arm/translate-vfp.inc.c

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target/arm: Add stubs for AArch32 VFP decodetree Add the infrastructure for building and invoking a decodetree decoder for the AArch32 VFP encodings. At the moment the new decoder covers nothing, so we always fall back to the existing hand-written decode. We need to have one decoder for the unconditional insns and one for the conditional insns, as otherwise the patterns for conditional insns would incorrectly match against the unconditional ones too. Since translate.c is over 14,000 lines long and we're going to be touching pretty much every line of the VFP code as part of the decodetree conversion, we create a new translate-vfp.inc.c to hold the code which deals with VFP in the new scheme. It should be possible to convert this into a standalone translation unit eventually, but the conversion process will be much simpler if we simply #include it midway through translate.c to start with. Backports commit 78e138bc1f672c145ef6ace74617db00eebaa2ba from qemu
2019-06-13 20:24:24 +00:00
/*
* ARM translation: AArch32 VFP instructions
*
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2005-2007 CodeSourcery
* Copyright (c) 2007 OpenedHand, Ltd.
* Copyright (c) 2019 Linaro, Ltd.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file is intended to be included from translate.c; it uses
* some macros and definitions provided by that file.
* It might be possible to convert it to a standalone .c file eventually.
*/
/* Include the generated VFP decoder */
#include "decode-vfp.inc.c"
#include "decode-vfp-uncond.inc.c"
target/arm: Factor out VFP access checking code Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Backports commit 06db8196bba34776829020192ed623a0b22e6557 from qemu
2019-06-13 20:30:12 +00:00
target/arm: Move vfp_expand_imm() to translate.[ch] We want to use vfp_expand_imm() in the AArch32 VFP decode; move it from the a64-only header/source file to the AArch32 one (which is always compiled even for AArch64). Backports commit d6a092d479333b5f20a647a912a31b0102d37335 from qemu
2019-06-25 23:17:37 +00:00
/*
* The imm8 encodes the sign bit, enough bits to represent an exponent in
* the range 01....1xx to 10....0xx, and the most significant 4 bits of
* the mantissa; see VFPExpandImm() in the v8 ARM ARM.
*/
uint64_t vfp_expand_imm(int size, uint8_t imm8)
{
uint64_t imm;
switch (size) {
case MO_64:
imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
(extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
extract32(imm8, 0, 6);
imm <<= 48;
break;
case MO_32:
imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
(extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
(extract32(imm8, 0, 6) << 3);
imm <<= 16;
break;
case MO_16:
imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
(extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
(extract32(imm8, 0, 6) << 6);
break;
default:
g_assert_not_reached();
}
return imm;
}
target/arm: Convert the VCVT-from-f16 insns to decodetree Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Backports commit b623d803dda805f07aadcbf098961fde27315c19 from qemu
2019-06-13 22:59:06 +00:00
/*
* Return the offset of a 16-bit half of the specified VFP single-precision
* register. If top is true, returns the top 16 bits; otherwise the bottom
* 16 bits.
*/
static inline long vfp_f16_offset(unsigned reg, bool top)
{
long offs = vfp_reg_offset(false, reg);
#ifdef HOST_WORDS_BIGENDIAN
if (!top) {
offs += 2;
}
#else
if (top) {
offs += 2;
}
#endif
return offs;
}
target/arm: Factor out VFP access checking code Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Backports commit 06db8196bba34776829020192ed623a0b22e6557 from qemu
2019-06-13 20:30:12 +00:00
/*
* Check that VFP access is enabled. If it is, do the necessary
* M-profile lazy-FP handling and then return true.
* If not, emit code to generate an appropriate exception and
* return false.
* The ignore_vfp_enabled argument specifies that we should ignore
* whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
* accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
*/
static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (s->fp_excp_el) {
if (arm_dc_feature(s, ARM_FEATURE_M)) {
gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
s->fp_excp_el);
} else {
gen_exception_insn(s, 4, EXCP_UDEF,
syn_fp_access_trap(1, 0xe, false),
s->fp_excp_el);
}
return false;
}
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
target/arm: Factor out unallocated_encoding for aarch32 Make this a static function private to translate.c. Thus we can use the same idiom between aarch64 and aarch32 without actually sharing function implementations. Backports commit 1ce21ba1eaf08b22da5925f3e37fc0b4322da858 from qemu
2019-11-19 04:51:43 +00:00
unallocated_encoding(s);
target/arm: Factor out VFP access checking code Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Backports commit 06db8196bba34776829020192ed623a0b22e6557 from qemu
2019-06-13 20:30:12 +00:00
return false;
}
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/* Handle M-profile lazy FP state mechanics */
/* Trigger lazy-state preservation if necessary */
if (s->v7m_lspact) {
/*
* Lazy state saving affects external memory and also the NVIC,
* so we must mark it as an IO operation for icount.
*/
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_start(tcg_ctx);
}
gen_helper_v7m_preserve_fp_state(tcg_ctx, tcg_ctx->cpu_env);
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
gen_io_end(tcg_ctx);
}
/*
* If the preserve_fp_state helper doesn't throw an exception
* then it will clear LSPACT; we don't need to repeat this for
* any further FP insns in this TB.
*/
s->v7m_lspact = false;
}
/* Update ownership of FP context: set FPCCR.S to match current state */
if (s->v8m_fpccr_s_wrong) {
TCGv_i32 tmp;
target/arm: Make load_cpu_offset() take a DisasContext* instead of uc_struct* Keeps it consistent with store_cpu_offset
2019-06-13 20:35:30 +00:00
tmp = load_cpu_field(s, v7m.fpccr[M_REG_S]);
target/arm: Factor out VFP access checking code Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Backports commit 06db8196bba34776829020192ed623a0b22e6557 from qemu
2019-06-13 20:30:12 +00:00
if (s->v8m_secure) {
tcg_gen_ori_i32(tcg_ctx, tmp, tmp, R_V7M_FPCCR_S_MASK);
} else {
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, ~R_V7M_FPCCR_S_MASK);
}
store_cpu_field(s, tmp, v7m.fpccr[M_REG_S]);
/* Don't need to do this for any further FP insns in this TB */
s->v8m_fpccr_s_wrong = false;
}
if (s->v7m_new_fp_ctxt_needed) {
/*
* Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
* and the FPSCR.
*/
TCGv_i32 control, fpscr;
uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
target/arm: Make load_cpu_offset() take a DisasContext* instead of uc_struct* Keeps it consistent with store_cpu_offset
2019-06-13 20:35:30 +00:00
fpscr = load_cpu_field(s, v7m.fpdscr[s->v8m_secure]);
target/arm: Factor out VFP access checking code Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Backports commit 06db8196bba34776829020192ed623a0b22e6557 from qemu
2019-06-13 20:30:12 +00:00
gen_helper_vfp_set_fpscr(tcg_ctx, tcg_ctx->cpu_env, fpscr);
tcg_temp_free_i32(tcg_ctx, fpscr);
/*
* We don't need to arrange to end the TB, because the only
* parts of FPSCR which we cache in the TB flags are the VECLEN
* and VECSTRIDE, and those don't exist for M-profile.
*/
if (s->v8m_secure) {
bits |= R_V7M_CONTROL_SFPA_MASK;
}
target/arm: Make load_cpu_offset() take a DisasContext* instead of uc_struct* Keeps it consistent with store_cpu_offset
2019-06-13 20:35:30 +00:00
control = load_cpu_field(s, v7m.control[M_REG_S]);
target/arm: Factor out VFP access checking code Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Backports commit 06db8196bba34776829020192ed623a0b22e6557 from qemu
2019-06-13 20:30:12 +00:00
tcg_gen_ori_i32(tcg_ctx, control, control, bits);
store_cpu_field(s, control, v7m.control[M_REG_S]);
/* Don't need to do this for any further FP insns in this TB */
s->v7m_new_fp_ctxt_needed = false;
}
}
return true;
}
target/arm: Convert the VSEL instructions to decodetree Convert the VSEL instructions to decodetree. We leave trans_VSEL() in translate.c for now as this allows the patch to show just the changes from the old handle_vsel(). In the old code the check for "do D16-D31 exist" was hidden in the VFP_DREG macro, and assumed that VFPv3 always implied that D16-D31 exist. In the new code we do the correct ID register test. This gives identical behaviour for most of our CPUs, and fixes previously incorrect handling for Cortex-R5F, Cortex-M4 and Cortex-M33, which all implement VFPv3 or better with only 16 double-precision registers. Backports commit b3ff4b87b4ae08120a51fe12592725e1dca8a085 from qemu
2019-06-13 20:41:19 +00:00
/*
* The most usual kind of VFP access check, for everything except
* FMXR/FMRX to the always-available special registers.
*/
static bool vfp_access_check(DisasContext *s)
{
return full_vfp_access_check(s, false);
}
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rd, rn, rm;
bool dp = a->dp;
if (!dc_isar_feature(aa32_vsel, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
return false;
}
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
rd = a->vd;
rn = a->vn;
rm = a->vm;
if (!vfp_access_check(s)) {
return true;
}
if (dp) {
TCGv_i64 frn, frm, dest;
TCGv_i64 tmp, zero, zf, nf, vf;
zero = tcg_const_i64(tcg_ctx, 0);
frn = tcg_temp_new_i64(tcg_ctx);
frm = tcg_temp_new_i64(tcg_ctx);
dest = tcg_temp_new_i64(tcg_ctx);
zf = tcg_temp_new_i64(tcg_ctx);
nf = tcg_temp_new_i64(tcg_ctx);
vf = tcg_temp_new_i64(tcg_ctx);
tcg_gen_extu_i32_i64(tcg_ctx, zf, tcg_ctx->cpu_ZF);
tcg_gen_ext_i32_i64(tcg_ctx, nf, tcg_ctx->cpu_NF);
tcg_gen_ext_i32_i64(tcg_ctx, vf, tcg_ctx->cpu_VF);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg64(s, frn, rn);
neon_load_reg64(s, frm, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
switch (a->cc) {
case 0: /* eq: Z */
tcg_gen_movcond_i64(tcg_ctx, TCG_COND_EQ, dest, zf, zero,
frn, frm);
break;
case 1: /* vs: V */
tcg_gen_movcond_i64(tcg_ctx, TCG_COND_LT, dest, vf, zero,
frn, frm);
break;
case 2: /* ge: N == V -> N ^ V == 0 */
tmp = tcg_temp_new_i64(tcg_ctx);
tcg_gen_xor_i64(tcg_ctx, tmp, vf, nf);
tcg_gen_movcond_i64(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
frn, frm);
tcg_temp_free_i64(tcg_ctx, tmp);
break;
case 3: /* gt: !Z && N == V */
tcg_gen_movcond_i64(tcg_ctx, TCG_COND_NE, dest, zf, zero,
frn, frm);
tmp = tcg_temp_new_i64(tcg_ctx);
tcg_gen_xor_i64(tcg_ctx, tmp, vf, nf);
tcg_gen_movcond_i64(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
dest, frm);
tcg_temp_free_i64(tcg_ctx, tmp);
break;
}
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg64(s, dest, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i64(tcg_ctx, frn);
tcg_temp_free_i64(tcg_ctx, frm);
tcg_temp_free_i64(tcg_ctx, dest);
tcg_temp_free_i64(tcg_ctx, zf);
tcg_temp_free_i64(tcg_ctx, nf);
tcg_temp_free_i64(tcg_ctx, vf);
tcg_temp_free_i64(tcg_ctx, zero);
} else {
TCGv_i32 frn, frm, dest;
TCGv_i32 tmp, zero;
zero = tcg_const_i32(tcg_ctx, 0);
frn = tcg_temp_new_i32(tcg_ctx);
frm = tcg_temp_new_i32(tcg_ctx);
dest = tcg_temp_new_i32(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg32(s, frn, rn);
neon_load_reg32(s, frm, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
switch (a->cc) {
case 0: /* eq: Z */
tcg_gen_movcond_i32(tcg_ctx, TCG_COND_EQ, dest, tcg_ctx->cpu_ZF, zero,
frn, frm);
break;
case 1: /* vs: V */
tcg_gen_movcond_i32(tcg_ctx, TCG_COND_LT, dest, tcg_ctx->cpu_VF, zero,
frn, frm);
break;
case 2: /* ge: N == V -> N ^ V == 0 */
tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_xor_i32(tcg_ctx, tmp, tcg_ctx->cpu_VF, tcg_ctx->cpu_NF);
tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
frn, frm);
tcg_temp_free_i32(tcg_ctx, tmp);
break;
case 3: /* gt: !Z && N == V */
tcg_gen_movcond_i32(tcg_ctx, TCG_COND_NE, dest, tcg_ctx->cpu_ZF, zero,
frn, frm);
tmp = tcg_temp_new_i32(tcg_ctx);
tcg_gen_xor_i32(tcg_ctx, tmp, tcg_ctx->cpu_VF, tcg_ctx->cpu_NF);
tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
dest, frm);
tcg_temp_free_i32(tcg_ctx, tmp);
break;
}
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg32(s, dest, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i32(tcg_ctx, frn);
tcg_temp_free_i32(tcg_ctx, frm);
tcg_temp_free_i32(tcg_ctx, dest);
tcg_temp_free_i32(tcg_ctx, zero);
}
return true;
}
static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rd, rn, rm;
bool dp = a->dp;
bool vmin = a->op;
TCGv_ptr fpst;
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
return false;
}
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
rd = a->vd;
rn = a->vn;
rm = a->vm;
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, 0);
if (dp) {
TCGv_i64 frn, frm, dest;
frn = tcg_temp_new_i64(tcg_ctx);
frm = tcg_temp_new_i64(tcg_ctx);
dest = tcg_temp_new_i64(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg64(s, frn, rn);
neon_load_reg64(s, frm, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
if (vmin) {
gen_helper_vfp_minnumd(tcg_ctx, dest, frn, frm, fpst);
} else {
gen_helper_vfp_maxnumd(tcg_ctx, dest, frn, frm, fpst);
}
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg64(s, dest, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i64(tcg_ctx, frn);
tcg_temp_free_i64(tcg_ctx, frm);
tcg_temp_free_i64(tcg_ctx, dest);
} else {
TCGv_i32 frn, frm, dest;
frn = tcg_temp_new_i32(tcg_ctx);
frm = tcg_temp_new_i32(tcg_ctx);
dest = tcg_temp_new_i32(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg32(s, frn, rn);
neon_load_reg32(s, frm, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
if (vmin) {
gen_helper_vfp_minnums(tcg_ctx, dest, frn, frm, fpst);
} else {
gen_helper_vfp_maxnums(tcg_ctx, dest, frn, frm, fpst);
}
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg32(s, dest, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i32(tcg_ctx, frn);
tcg_temp_free_i32(tcg_ctx, frm);
tcg_temp_free_i32(tcg_ctx, dest);
}
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
/*
* Table for converting the most common AArch32 encoding of
* rounding mode to arm_fprounding order (which matches the
* common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
*/
static const uint8_t fp_decode_rm[] = {
FPROUNDING_TIEAWAY,
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
FPROUNDING_NEGINF,
};
static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rd, rm;
bool dp = a->dp;
TCGv_ptr fpst;
TCGv_i32 tcg_rmode;
int rounding = fp_decode_rm[a->rm];
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
return false;
}
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vd) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
rd = a->vd;
rm = a->vm;
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, 0);
tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
if (dp) {
TCGv_i64 tcg_op;
TCGv_i64 tcg_res;
tcg_op = tcg_temp_new_i64(tcg_ctx);
tcg_res = tcg_temp_new_i64(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg64(s, tcg_op, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
gen_helper_rintd(tcg_ctx, tcg_res, tcg_op, fpst);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg64(s, tcg_res, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i64(tcg_ctx, tcg_op);
tcg_temp_free_i64(tcg_ctx, tcg_res);
} else {
TCGv_i32 tcg_op;
TCGv_i32 tcg_res;
tcg_op = tcg_temp_new_i32(tcg_ctx);
tcg_res = tcg_temp_new_i32(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg32(s, tcg_op, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
gen_helper_rints(tcg_ctx, tcg_res, tcg_op, fpst);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg32(s, tcg_res, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i32(tcg_ctx, tcg_op);
tcg_temp_free_i32(tcg_ctx, tcg_res);
}
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
tcg_temp_free_i32(tcg_ctx, tcg_rmode);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rd, rm;
bool dp = a->dp;
TCGv_ptr fpst;
TCGv_i32 tcg_rmode, tcg_shift;
int rounding = fp_decode_rm[a->rm];
bool is_signed = a->op;
if (!dc_isar_feature(aa32_vcvt_dr, s)) {
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
return false;
}
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
rd = a->vd;
rm = a->vm;
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, 0);
tcg_shift = tcg_const_i32(tcg_ctx, 0);
tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
if (dp) {
TCGv_i64 tcg_double, tcg_res;
TCGv_i32 tcg_tmp;
tcg_double = tcg_temp_new_i64(tcg_ctx);
tcg_res = tcg_temp_new_i64(tcg_ctx);
tcg_tmp = tcg_temp_new_i32(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg64(s, tcg_double, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
if (is_signed) {
gen_helper_vfp_tosld(tcg_ctx, tcg_res, tcg_double, tcg_shift, fpst);
} else {
gen_helper_vfp_tould(tcg_ctx, tcg_res, tcg_double, tcg_shift, fpst);
}
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_tmp, tcg_res);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg32(s, tcg_tmp, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i32(tcg_ctx, tcg_tmp);
tcg_temp_free_i64(tcg_ctx, tcg_res);
tcg_temp_free_i64(tcg_ctx, tcg_double);
} else {
TCGv_i32 tcg_single, tcg_res;
tcg_single = tcg_temp_new_i32(tcg_ctx);
tcg_res = tcg_temp_new_i32(tcg_ctx);
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_load_reg32(s, tcg_single, rm);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
if (is_signed) {
gen_helper_vfp_tosls(tcg_ctx, tcg_res, tcg_single, tcg_shift, fpst);
} else {
gen_helper_vfp_touls(tcg_ctx, tcg_res, tcg_single, tcg_shift, fpst);
}
target/arm: Add helpers for VFP register loads and stores The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
neon_store_reg32(s, tcg_res, rd);
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Backports commit f7bbb8f31f0761edbf0c64b7ab3c3f49c13612ea from qemu
2019-06-13 20:56:21 +00:00
tcg_temp_free_i32(tcg_ctx, tcg_res);
tcg_temp_free_i32(tcg_ctx, tcg_single);
}
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
tcg_temp_free_i32(tcg_ctx, tcg_rmode);
tcg_temp_free_i32(tcg_ctx, tcg_shift);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
target/arm: Convert double-precision register moves to decodetree Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 21:09:09 +00:00
static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
{
/* VMOV scalar to general purpose register */
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp;
int pass;
uint32_t offset;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
/* SIZE == 2 is a VFP instruction; otherwise NEON. */
if (a->size == 2
? !dc_isar_feature(aa32_fpsp_v2, s)
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
target/arm: Convert double-precision register moves to decodetree Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 21:09:09 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
target/arm: Convert double-precision register moves to decodetree Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 21:09:09 +00:00
return false;
}
offset = a->index << a->size;
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
if (!vfp_access_check(s)) {
return true;
}
tmp = neon_load_reg(s, a->vn, pass);
switch (a->size) {
case 0:
if (offset) {
tcg_gen_shri_i32(tcg_ctx, tmp, tmp, offset);
}
if (a->u) {
gen_uxtb(tmp);
} else {
gen_sxtb(tmp);
}
break;
case 1:
if (a->u) {
if (offset) {
tcg_gen_shri_i32(tcg_ctx, tmp, tmp, 16);
} else {
gen_uxth(tmp);
}
} else {
if (offset) {
tcg_gen_sari_i32(tcg_ctx, tmp, tmp, 16);
} else {
gen_sxth(tmp);
}
}
break;
case 2:
break;
}
store_reg(s, a->rt, tmp);
return true;
}
static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
{
/* VMOV general purpose register to scalar */
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp, tmp2;
int pass;
uint32_t offset;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
/* SIZE == 2 is a VFP instruction; otherwise NEON. */
if (a->size == 2
? !dc_isar_feature(aa32_fpsp_v2, s)
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
target/arm: Convert double-precision register moves to decodetree Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 21:09:09 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
target/arm: Convert double-precision register moves to decodetree Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 21:09:09 +00:00
return false;
}
offset = a->index << a->size;
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
if (!vfp_access_check(s)) {
return true;
}
tmp = load_reg(s, a->rt);
switch (a->size) {
case 0:
tmp2 = neon_load_reg(s, a->vn, pass);
tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, offset, 8);
tcg_temp_free_i32(tcg_ctx, tmp2);
break;
case 1:
tmp2 = neon_load_reg(s, a->vn, pass);
tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, offset, 16);
tcg_temp_free_i32(tcg_ctx, tmp2);
break;
case 2:
break;
}
neon_store_reg(s, a->vn, pass, tmp);
return true;
}
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
{
/* VDUP (general purpose register) */
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp;
int size, vec_size;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
target/arm: Convert double-precision register moves to decodetree Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 21:09:09 +00:00
return false;
}
if (a->b && a->e) {
return false;
}
if (a->q && (a->vn & 1)) {
return false;
}
vec_size = a->q ? 16 : 8;
if (a->b) {
size = 0;
} else if (a->e) {
size = 1;
} else {
size = 2;
}
if (!vfp_access_check(s)) {
return true;
}
tmp = load_reg(s, a->rt);
tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(a->vn, 0),
vec_size, vec_size, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp;
bool ignore_vfp_enabled = false;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/*
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
target/arm: Allow reading flags from FPSCR for M-profile rt==15 is a special case when reading the flags: it means the destination is APSR. This patch avoids rejecting vmrs apsr_nzcv, fpscr as illegal instruction. Backports commit cdc6896659b85f7ed8f7552850312e55170de0c5 from qemu
2019-11-18 21:31:51 +00:00
* Accesses to R15 are UNPREDICTABLE; we choose to undef.
* (FPSCR -> r15 is a special case which writes to the PSR flags.)
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
*/
target/arm: Allow reading flags from FPSCR for M-profile rt==15 is a special case when reading the flags: it means the destination is APSR. This patch avoids rejecting vmrs apsr_nzcv, fpscr as illegal instruction. Backports commit cdc6896659b85f7ed8f7552850312e55170de0c5 from qemu
2019-11-18 21:31:51 +00:00
if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
return false;
}
}
switch (a->reg) {
case ARM_VFP_FPSID:
/*
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
* all ID registers to privileged access only.
*/
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_MVFR2:
if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_FPSCR:
break;
case ARM_VFP_FPEXC:
if (IS_USER(s)) {
return false;
}
ignore_vfp_enabled = true;
break;
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
/* Not present in VFPv3 */
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
return false;
}
break;
default:
return false;
}
if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
return true;
}
if (a->l) {
/* VMRS, move VFP special register to gp register */
switch (a->reg) {
target/arm: Handle trapping to EL2 of AArch32 VMRS instructions HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to EL2, and HCR_EL2.TID0 does the same for reads of FPSID. In order to handle this, introduce a new TCG helper function that checks for these control bits before executing the VMRC instruction. Tested with a hacked-up version of KVM/arm64 that sets the control bits for 32bit guests. Backports commit 9ca1d776cb49c09b09579d9edd0447542970c834 from qemu
2020-01-07 23:04:09 +00:00
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
if (s->current_el == 1) {
TCGv_i32 tcg_reg, tcg_rt;
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
tcg_reg = tcg_const_i32(tcg_ctx, a->reg);
tcg_rt = tcg_const_i32(tcg_ctx, a->rt);
gen_helper_check_hcr_el2_trap(tcg_ctx, tcg_ctx->cpu_env, tcg_rt, tcg_reg);
tcg_temp_free_i32(tcg_ctx, tcg_reg);
tcg_temp_free_i32(tcg_ctx, tcg_rt);
}
/* fall through */
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
case ARM_VFP_FPSID:
case ARM_VFP_FPEXC:
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
tmp = load_cpu_field(s, vfp.xregs[a->reg]);
break;
case ARM_VFP_FPSCR:
if (a->rt == 15) {
tmp = load_cpu_field(s, vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xf0000000);
} else {
tmp = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_get_fpscr(tcg_ctx, tmp, tcg_ctx->cpu_env);
}
break;
default:
g_assert_not_reached();
}
if (a->rt == 15) {
/* Set the 4 flag bits in the CPSR. */
gen_set_nzcv(s, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
} else {
store_reg(s, a->rt, tmp);
}
} else {
/* VMSR, move gp register to VFP special register */
switch (a->reg) {
case ARM_VFP_FPSID:
case ARM_VFP_MVFR0:
case ARM_VFP_MVFR1:
case ARM_VFP_MVFR2:
/* Writes are ignored. */
break;
case ARM_VFP_FPSCR:
tmp = load_reg(s, a->rt);
gen_helper_vfp_set_fpscr(tcg_ctx, tcg_ctx->cpu_env, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPEXC:
/*
* TODO: VFP subarchitecture support.
* For now, keep the EN bit only
*/
tmp = load_reg(s, a->rt);
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 1 << 30);
store_cpu_field(s, tmp, vfp.xregs[a->reg]);
gen_lookup_tb(s);
break;
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
tmp = load_reg(s, a->rt);
store_cpu_field(s, tmp, vfp.xregs[a->reg]);
break;
default:
g_assert_not_reached();
}
}
return true;
}
static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert single-precision register moves to decodetree Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Backports commit a9ab50011aeda2dd012da99069e078379315ea18 from qemu
2019-06-13 21:16:35 +00:00
if (!vfp_access_check(s)) {
return true;
}
if (a->l) {
/* VFP to general purpose register */
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vn);
if (a->rt == 15) {
/* Set the 4 flag bits in the CPSR. */
gen_set_nzcv(s, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
} else {
store_reg(s, a->rt, tmp);
}
} else {
/* general purpose register to VFP */
tmp = load_reg(s, a->rt);
neon_store_reg32(s, tmp, a->vn);
tcg_temp_free_i32(tcg_ctx, tmp);
}
return true;
}
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
/*
* VMOV between two general-purpose registers and two single precision
* floating point registers
*/
if (!vfp_access_check(s)) {
return true;
}
if (a->op) {
/* fpreg to gpreg */
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm);
store_reg(s, a->rt, tmp);
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm + 1);
store_reg(s, a->rt2, tmp);
} else {
/* gpreg to fpreg */
tmp = load_reg(s, a->rt);
neon_store_reg32(s, tmp, a->vm);
target/arm: Free TCG temps in trans_VMOV_64_sp() The function neon_store_reg32() doesn't free the TCG temp that it is passed, so the caller must do that. We got this right in most places but forgot to free the TCG temps in trans_VMOV_64_sp(). Backports commit 38fb634853ac6547326d9f88b9a068d9fc6b4ad4 from qemu
2019-11-18 21:27:12 +00:00
tcg_temp_free_i32(tcg_ctx, tmp);
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
tmp = load_reg(s, a->rt2);
neon_store_reg32(s, tmp, a->vm + 1);
target/arm: Free TCG temps in trans_VMOV_64_sp() The function neon_store_reg32() doesn't free the TCG temp that it is passed, so the caller must do that. We got this right in most places but forgot to free the TCG temps in trans_VMOV_64_sp(). Backports commit 38fb634853ac6547326d9f88b9a068d9fc6b4ad4 from qemu
2019-11-18 21:27:12 +00:00
tcg_temp_free_i32(tcg_ctx, tmp);
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
}
return true;
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 tmp;
/*
* VMOV between two general-purpose registers and one double precision
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
* floating point register. Note that this does not require support
* for double precision arithmetic.
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
*/
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
target/arm: Convert VFP two-register transfer insns to decodetree Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Backports commit 81f681106eabe21c55118a5a41999fb7387fb714 from qemu
2019-06-13 21:19:58 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (a->op) {
/* fpreg to gpreg */
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm * 2);
store_reg(s, a->rt, tmp);
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm * 2 + 1);
store_reg(s, a->rt2, tmp);
} else {
/* gpreg to fpreg */
tmp = load_reg(s, a->rt);
neon_store_reg32(s, tmp, a->vm * 2);
tcg_temp_free_i32(tcg_ctx, tmp);
tmp = load_reg(s, a->rt2);
neon_store_reg32(s, tmp, a->vm * 2 + 1);
tcg_temp_free_i32(tcg_ctx, tmp);
}
return true;
}
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t offset;
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
TCGv_i32 addr, tmp;
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
if (!vfp_access_check(s)) {
return true;
}
offset = a->imm << 2;
if (!a->u) {
offset = -offset;
}
target/arm: Introduce add_reg_for_lit Provide a common routine for the places that require ALIGN(PC, 4) as the base address as opposed to plain PC. The two are always the same for A32, but the difference is meaningful for thumb mode. Backports commit 16e0d8234ef9291747332d2c431e46808a060472 from qemu
2019-11-18 22:07:18 +00:00
/* For thumb, use of PC is UNPREDICTABLE. */
addr = add_reg_for_lit(s, a->rn, offset);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tmp = tcg_temp_new_i32(tcg_ctx);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
if (a->l) {
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
neon_store_reg32(s, tmp, a->vd);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
} else {
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
neon_load_reg32(s, tmp, a->vd);
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
}
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tcg_temp_free_i32(tcg_ctx, tmp);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
tcg_temp_free_i32(tcg_ctx, addr);
return true;
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t offset;
TCGv_i32 addr;
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
TCGv_i64 tmp;
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
/* Note that this does not require support for double arithmetic. */
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
offset = a->imm << 2;
if (!a->u) {
offset = -offset;
}
target/arm: Introduce add_reg_for_lit Provide a common routine for the places that require ALIGN(PC, 4) as the base address as opposed to plain PC. The two are always the same for A32, but the difference is meaningful for thumb mode. Backports commit 16e0d8234ef9291747332d2c431e46808a060472 from qemu
2019-11-18 22:07:18 +00:00
/* For thumb, use of PC is UNPREDICTABLE. */
addr = add_reg_for_lit(s, a->rn, offset);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tmp = tcg_temp_new_i64(tcg_ctx);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
if (a->l) {
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
neon_store_reg64(s, tmp, a->vd);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
} else {
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
neon_load_reg64(s, tmp, a->vd);
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
}
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tcg_temp_free_i64(tcg_ctx, tmp);
target/arm: Convert VFP VLDR and VSTR to decodetree Convert the VFP single load/store insns VLDR and VSTR to decodetree. Backports commit 79b02a3b5231c5b8cd31e50cd549968dd0a05c49 from qemu
2019-06-13 21:22:47 +00:00
tcg_temp_free_i32(tcg_ctx, addr);
return true;
}
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t offset;
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
TCGv_i32 addr, tmp;
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
int i, n;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
n = a->imm;
if (n == 0 || (a->vd + n) > 32) {
/*
* UNPREDICTABLE cases for bad immediates: we choose to
* UNDEF to avoid generating huge numbers of TCG ops
*/
return false;
}
if (a->rn == 15 && a->w) {
/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
return false;
}
if (!vfp_access_check(s)) {
return true;
}
target/arm: Introduce add_reg_for_lit Provide a common routine for the places that require ALIGN(PC, 4) as the base address as opposed to plain PC. The two are always the same for A32, but the difference is meaningful for thumb mode. Backports commit 16e0d8234ef9291747332d2c431e46808a060472 from qemu
2019-11-18 22:07:18 +00:00
/* For thumb, use of PC is UNPREDICTABLE. */
addr = add_reg_for_lit(s, a->rn, 0);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
if (a->p) {
/* pre-decrement */
tcg_gen_addi_i32(tcg_ctx, addr, addr, -(a->imm << 2));
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
/*
* Here 'addr' is the lowest address we will store to,
* and is either the old SP (if post-increment) or
* the new SP (if pre-decrement). For post-increment
* where the old value is below the limit and the new
* value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger.
*/
gen_helper_v8m_stackcheck(tcg_ctx, tcg_ctx->cpu_env, addr);
}
offset = 4;
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tmp = tcg_temp_new_i32(tcg_ctx);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
neon_store_reg32(s, tmp, a->vd + i);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
} else {
/* store */
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
neon_load_reg32(s, tmp, a->vd + i);
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
}
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
}
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tcg_temp_free_i32(tcg_ctx, tmp);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
if (a->w) {
/* writeback */
if (a->p) {
offset = -offset * n;
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
}
store_reg(s, a->rn, addr);
} else {
tcg_temp_free_i32(tcg_ctx, addr);
}
return true;
}
static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t offset;
TCGv_i32 addr;
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
TCGv_i64 tmp;
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
int i, n;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
/* Note that this does not require support for double arithmetic. */
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
n = a->imm >> 1;
if (n == 0 || (a->vd + n) > 32 || n > 16) {
/*
* UNPREDICTABLE cases for bad immediates: we choose to
* UNDEF to avoid generating huge numbers of TCG ops
*/
return false;
}
if (a->rn == 15 && a->w) {
/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) {
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
target/arm: Introduce add_reg_for_lit Provide a common routine for the places that require ALIGN(PC, 4) as the base address as opposed to plain PC. The two are always the same for A32, but the difference is meaningful for thumb mode. Backports commit 16e0d8234ef9291747332d2c431e46808a060472 from qemu
2019-11-18 22:07:18 +00:00
/* For thumb, use of PC is UNPREDICTABLE. */
addr = add_reg_for_lit(s, a->rn, 0);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
if (a->p) {
/* pre-decrement */
tcg_gen_addi_i32(tcg_ctx, addr, addr, -(a->imm << 2));
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
/*
* Here 'addr' is the lowest address we will store to,
* and is either the old SP (if post-increment) or
* the new SP (if pre-decrement). For post-increment
* where the old value is below the limit and the new
* value is above, it is UNKNOWN whether the limit check
* triggers; we choose to trigger.
*/
gen_helper_v8m_stackcheck(tcg_ctx, tcg_ctx->cpu_env, addr);
}
offset = 8;
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tmp = tcg_temp_new_i64(tcg_ctx);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
neon_store_reg64(s, tmp, a->vd + i);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
} else {
/* store */
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
neon_load_reg64(s, tmp, a->vd + i);
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
}
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
}
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d Expand out the sequences in the new decoder VLDR/VSTR/VLDM/VSTM trans functions which perform the memory accesses by going via the TCG globals cpu_F0s and cpu_F0d, to use local TCG temps instead. Backports commit 3993d0407dff7233e42f2251db971e126a0497e9 from qemu
2019-06-13 21:31:25 +00:00
tcg_temp_free_i64(tcg_ctx, tmp);
target/arm: Convert the VFP load/store multiple insns to decodetree Convert the VFP load/store multiple insns to decodetree. This includes tightening up the UNDEF checking for pre-VFPv3 CPUs which only have D0-D15 : they now UNDEF for any access to D16-D31, not merely when the smallest register in the transfer list is in D16-D31. This conversion does not try to share code between the single precision and the double precision versions; this looks a bit duplicative of code, but it leaves the door open for a future refactoring which gets rid of the use of the "F0" registers by inlining the various functions like gen_vfp_ld() and gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }" conditionalisation. Backports commit fa288de272c5c8a66d5eb683b123706a52bc7ad6 from qemu
2019-06-13 21:25:34 +00:00
if (a->w) {
/* writeback */
if (a->p) {
offset = -offset * n;
} else if (a->imm & 1) {
offset = 4;
} else {
offset = 0;
}
if (offset != 0) {
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
}
store_reg(s, a->rn, addr);
} else {
tcg_temp_free_i32(tcg_ctx, addr);
}
return true;
}
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
/*
* Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
* The callback should emit code to write a value to vd. If
* do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
* will contain the old value of the relevant VFP register;
* otherwise it must be written to only.
*/
typedef void VFPGen3OpSPFn(TCGContext *, TCGv_i32 vd,
TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst);
typedef void VFPGen3OpDPFn(TCGContext *, TCGv_i64 vd,
TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst);
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
/*
* Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
* The callback should emit code to write a value to vd (which
* should be written to only).
*/
typedef void VFPGen2OpSPFn(TCGContext *, TCGv_i32 vd, TCGv_i32 vm);
typedef void VFPGen2OpDPFn(TCGContext *, TCGv_i64 vd, TCGv_i64 vm);
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
/*
* Return true if the specified S reg is in a scalar bank
* (ie if it is s0..s7)
*/
static inline bool vfp_sreg_is_scalar(int reg)
{
return (reg & 0x18) == 0;
}
/*
* Return true if the specified D reg is in a scalar bank
* (ie if it is d0..d3 or d16..d19)
*/
static inline bool vfp_dreg_is_scalar(int reg)
{
return (reg & 0xc) == 0;
}
/*
* Advance the S reg number forwards by delta within its bank
* (ie increment the low 3 bits but leave the rest the same)
*/
static inline int vfp_advance_sreg(int reg, int delta)
{
return ((reg + delta) & 0x7) | (reg & ~0x7);
}
/*
* Advance the D reg number forwards by delta within its bank
* (ie increment the low 2 bits but leave the rest the same)
*/
static inline int vfp_advance_dreg(int reg, int delta)
{
return ((reg + delta) & 0x3) | (reg & ~0x3);
}
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
/*
* Perform a 3-operand VFP data processing instruction. fn is the
* callback to do the actual operation; this function deals with the
* code to handle looping around for VFP vector processing.
*/
static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
int vd, int vn, int vm, bool reads_vd)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t delta_m = 0;
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i32 f0, f1, fd;
TCGv_ptr fpst;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (veclen > 0) {
/* Figure out what type of vector operation this is. */
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_sreg_is_scalar(vd)) {
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
/* scalar */
veclen = 0;
} else {
delta_d = s->vec_stride + 1;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_sreg_is_scalar(vm)) {
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
/* mixed scalar/vector */
delta_m = 0;
} else {
/* vector */
delta_m = delta_d;
}
}
}
f0 = tcg_temp_new_i32(tcg_ctx);
f1 = tcg_temp_new_i32(tcg_ctx);
fd = tcg_temp_new_i32(tcg_ctx);
fpst = get_fpstatus_ptr(s, 0);
neon_load_reg32(s, f0, vn);
neon_load_reg32(s, f1, vm);
for (;;) {
if (reads_vd) {
neon_load_reg32(s, fd, vd);
}
fn(tcg_ctx, fd, f0, f1, fpst);
neon_store_reg32(s, fd, vd);
if (veclen == 0) {
break;
}
/* Set up the operands for the next iteration */
veclen--;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_sreg(vd, delta_d);
vn = vfp_advance_sreg(vn, delta_d);
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
neon_load_reg32(s, f0, vn);
if (delta_m) {
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vm = vfp_advance_sreg(vm, delta_m);
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
neon_load_reg32(s, f1, vm);
}
}
tcg_temp_free_i32(tcg_ctx, f0);
tcg_temp_free_i32(tcg_ctx, f1);
tcg_temp_free_i32(tcg_ctx, fd);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
int vd, int vn, int vm, bool reads_vd)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t delta_m = 0;
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i64 f0, f1, fd;
TCGv_ptr fpst;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (veclen > 0) {
/* Figure out what type of vector operation this is. */
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_dreg_is_scalar(vd)) {
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
/* scalar */
veclen = 0;
} else {
delta_d = (s->vec_stride >> 1) + 1;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_dreg_is_scalar(vm)) {
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
/* mixed scalar/vector */
delta_m = 0;
} else {
/* vector */
delta_m = delta_d;
}
}
}
f0 = tcg_temp_new_i64(tcg_ctx);
f1 = tcg_temp_new_i64(tcg_ctx);
fd = tcg_temp_new_i64(tcg_ctx);
fpst = get_fpstatus_ptr(s, 0);
neon_load_reg64(s, f0, vn);
neon_load_reg64(s, f1, vm);
for (;;) {
if (reads_vd) {
neon_load_reg64(s, fd, vd);
}
fn(tcg_ctx, fd, f0, f1, fpst);
neon_store_reg64(s, fd, vd);
if (veclen == 0) {
break;
}
/* Set up the operands for the next iteration */
veclen--;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_dreg(vd, delta_d);
vn = vfp_advance_dreg(vn, delta_d);
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
neon_load_reg64(s, f0, vn);
if (delta_m) {
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vm = vfp_advance_dreg(vm, delta_m);
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
neon_load_reg64(s, f1, vm);
}
}
tcg_temp_free_i64(tcg_ctx, f0);
tcg_temp_free_i64(tcg_ctx, f1);
tcg_temp_free_i64(tcg_ctx, fd);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t delta_m = 0;
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i32 f0, fd;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (veclen > 0) {
/* Figure out what type of vector operation this is. */
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_sreg_is_scalar(vd)) {
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
/* scalar */
veclen = 0;
} else {
delta_d = s->vec_stride + 1;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_sreg_is_scalar(vm)) {
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
/* mixed scalar/vector */
delta_m = 0;
} else {
/* vector */
delta_m = delta_d;
}
}
}
f0 = tcg_temp_new_i32(tcg_ctx);
fd = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, f0, vm);
for (;;) {
fn(tcg_ctx, fd, f0);
neon_store_reg32(s, fd, vd);
if (veclen == 0) {
break;
}
if (delta_m == 0) {
/* single source one-many */
while (veclen--) {
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_sreg(vd, delta_d);
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
neon_store_reg32(s, fd, vd);
}
break;
}
/* Set up the operands for the next iteration */
veclen--;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_sreg(vd, delta_d);
vm = vfp_advance_sreg(vm, delta_m);
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
neon_load_reg32(s, f0, vm);
}
tcg_temp_free_i32(tcg_ctx, f0);
tcg_temp_free_i32(tcg_ctx, fd);
return true;
}
static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t delta_m = 0;
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i64 f0, fd;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
/* UNDEF accesses to D16-D31 if they don't exist */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
return false;
}
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (veclen > 0) {
/* Figure out what type of vector operation this is. */
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_dreg_is_scalar(vd)) {
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
/* scalar */
veclen = 0;
} else {
delta_d = (s->vec_stride >> 1) + 1;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_dreg_is_scalar(vm)) {
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
/* mixed scalar/vector */
delta_m = 0;
} else {
/* vector */
delta_m = delta_d;
}
}
}
f0 = tcg_temp_new_i64(tcg_ctx);
fd = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, f0, vm);
for (;;) {
fn(tcg_ctx, fd, f0);
neon_store_reg64(s, fd, vd);
if (veclen == 0) {
break;
}
if (delta_m == 0) {
/* single source one-many */
while (veclen--) {
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_dreg(vd, delta_d);
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
neon_store_reg64(s, fd, vd);
}
break;
}
/* Set up the operands for the next iteration */
veclen--;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_dreg(vd, delta_d);
vd = vfp_advance_dreg(vm, delta_m);
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
neon_load_reg64(s, f0, vm);
}
tcg_temp_free_i64(tcg_ctx, f0);
tcg_temp_free_i64(tcg_ctx, fd);
return true;
}
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
static void gen_VMLA_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
{
/* Note that order of inputs to the add matters for NaNs */
TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_muls(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_adds(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
}
static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a)
{
return do_vfp_3op_sp(s, gen_VMLA_sp, a->vd, a->vn, a->vm, true);
}
static void gen_VMLA_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
{
/* Note that order of inputs to the add matters for NaNs */
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
gen_helper_vfp_muld(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_addd(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a)
target/arm: Convert VFP VMLA to decodetree Convert the VFP VMLA instruction to decodetree. This is the first of the VFP 3-operand data processing instructions, so we include in this patch the code which loops over the elements for an old-style VFP vector operation. The existing code to do this looping uses the deprecated cpu_F0s/F0d/F1s/F1d TCG globals; since we are going to be converting instructions one at a time anyway we can take the opportunity to make the new loop use TCG temporaries, which means we can do that conversion one operation at a time rather than needing to do it all in one go. We include an UNDEF check which was missing in the old code: short-vector operations (with stride or length non-zero) were deprecated in v7A and must UNDEF in v8A, so if the MVFR0 FPShVec field does not indicate that support for short vectors is present we UNDEF the operations that would use them. (This is a change of behaviour for Cortex-A7, Cortex-A15 and the v8 CPUs, which previously were all incorrectly allowing short-vector operations.) Note that the conversion fixes a bug in the old code for the case of VFP short-vector "mixed scalar/vector operations". These happen where the destination register is in a vector bank but but the second operand is in a scalar bank. For example vmla.f64 d10, d1, d16 with length 2 stride 2 is equivalent to the pair of scalar operations vmla.f64 d10, d1, d16 vmla.f64 d8, d3, d16 where the destination and first input register cycle through their vector but the second input is scalar (d16). In the old decoder the gen_vfp_F1_mul() operation uses cpu_F1{s,d} as a temporary output for the multiply, which trashes the second input operand. For the fully-scalar case (where we never do a second iteration) and the fully-vector case (where the loop loads the new second input operand) this doesn't matter, but for the mixed scalar/vector case we will end up using the wrong value for later loop iterations. In the new code we use TCG temporaries and so avoid the bug. This bug is present for all the multiply-accumulate insns that operate on short vectors: VMLA, VMLS, VNMLA, VNMLS. Note 2: the expression used to calculate the next register number in the vector bank is not in fact correct; we leave this behaviour unchanged from the old decoder and will fix this bug later in the series. Backports commit 266bd25c485597c94209bfdb3891c1d0c573c164 from qemu
2019-06-13 21:59:10 +00:00
{
return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true);
}
target/arm: Convert VFP VMLS to decodetree Convert the VFP VMLS instruction to decodetree. Backports commit e7258280d46af4ab6a0cc93ccfe8f6614defb4b7 from qemu
2019-06-13 22:02:34 +00:00
static void gen_VMLS_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
{
/*
* VMLS: vd = vd + -(vn * vm)
* Note that order of inputs to the add matters for NaNs.
*/
TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_muls(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_negs(tcg_ctx, tmp, tmp);
gen_helper_vfp_adds(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
}
static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a)
{
return do_vfp_3op_sp(s, gen_VMLS_sp, a->vd, a->vn, a->vm, true);
}
static void gen_VMLS_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
{
/*
* VMLS: vd = vd + -(vn * vm)
* Note that order of inputs to the add matters for NaNs.
*/
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
gen_helper_vfp_muld(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_negd(tcg_ctx, tmp, tmp);
gen_helper_vfp_addd(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a)
target/arm: Convert VFP VMLS to decodetree Convert the VFP VMLS instruction to decodetree. Backports commit e7258280d46af4ab6a0cc93ccfe8f6614defb4b7 from qemu
2019-06-13 22:02:34 +00:00
{
return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true);
}
target/arm: Convert VFP VNMLS to decodetree Convert the VFP VNMLS instruction to decodetree. Backports commit c54a416cc6d60efbc79dd37aaf0c8918c05b5815 from qemu
2019-06-13 22:04:30 +00:00
static void gen_VNMLS_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
{
/*
* VNMLS: -fd + (fn * fm)
* Note that it isn't valid to replace (-A + B) with (B - A) or similar
* plausible looking simplifications because this will give wrong results
* for NaNs.
*/
TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_muls(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_negs(tcg_ctx, vd, vd);
gen_helper_vfp_adds(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
}
static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a)
{
return do_vfp_3op_sp(s, gen_VNMLS_sp, a->vd, a->vn, a->vm, true);
}
static void gen_VNMLS_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
{
/*
* VNMLS: -fd + (fn * fm)
* Note that it isn't valid to replace (-A + B) with (B - A) or similar
* plausible looking simplifications because this will give wrong results
* for NaNs.
*/
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
gen_helper_vfp_muld(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_negd(tcg_ctx, vd, vd);
gen_helper_vfp_addd(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a)
target/arm: Convert VFP VNMLS to decodetree Convert the VFP VNMLS instruction to decodetree. Backports commit c54a416cc6d60efbc79dd37aaf0c8918c05b5815 from qemu
2019-06-13 22:04:30 +00:00
{
return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true);
}
target/arm: Convert VFP VNMLA to decodetree Convert the VFP VNMLA instruction to decodetree. Backports commit 8a483533adc1bdc2decb8f456dbe930a2d245a8b from qemu
2019-06-13 22:09:53 +00:00
static void gen_VNMLA_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
{
/* VNMLA: -fd + -(fn * fm) */
TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_muls(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_negs(tcg_ctx, tmp, tmp);
gen_helper_vfp_negs(tcg_ctx, vd, vd);
gen_helper_vfp_adds(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
}
static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a)
{
return do_vfp_3op_sp(s, gen_VNMLA_sp, a->vd, a->vn, a->vm, true);
}
static void gen_VNMLA_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
{
/* VNMLA: -fd + (fn * fm) */
TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
gen_helper_vfp_muld(tcg_ctx, tmp, vn, vm, fpst);
gen_helper_vfp_negd(tcg_ctx, tmp, tmp);
gen_helper_vfp_negd(tcg_ctx, vd, vd);
gen_helper_vfp_addd(tcg_ctx, vd, vd, tmp, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a)
target/arm: Convert VFP VNMLA to decodetree Convert the VFP VNMLA instruction to decodetree. Backports commit 8a483533adc1bdc2decb8f456dbe930a2d245a8b from qemu
2019-06-13 22:09:53 +00:00
{
return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true);
}
target/arm: Convert VMUL to decodetree Convert the VMUL instruction to decodetree. Backports commit 88c5188ced60e9f2b8cc3af3b9bc4a8031c8c996 from qemu
2019-06-13 22:12:01 +00:00
static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a)
{
return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a)
target/arm: Convert VMUL to decodetree Convert the VMUL instruction to decodetree. Backports commit 88c5188ced60e9f2b8cc3af3b9bc4a8031c8c996 from qemu
2019-06-13 22:12:01 +00:00
{
return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false);
}
target/arm: Convert VNMUL to decodetree Convert the VNMUL instruction to decodetree. Backports commit 43c4be1236c105090d134540da1036073d157cd4 from qemu
2019-06-13 22:14:15 +00:00
static void gen_VNMUL_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpst)
{
/* VNMUL: -(fn * fm) */
gen_helper_vfp_muls(tcg_ctx, vd, vn, vm, fpst);
gen_helper_vfp_negs(tcg_ctx, vd, vd);
}
static bool trans_VNMUL_sp(DisasContext *s, arg_VNMUL_sp *a)
{
return do_vfp_3op_sp(s, gen_VNMUL_sp, a->vd, a->vn, a->vm, false);
}
static void gen_VNMUL_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst)
{
/* VNMUL: -(fn * fm) */
gen_helper_vfp_muld(tcg_ctx, vd, vn, vm, fpst);
gen_helper_vfp_negd(tcg_ctx, vd, vd);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a)
target/arm: Convert VNMUL to decodetree Convert the VNMUL instruction to decodetree. Backports commit 43c4be1236c105090d134540da1036073d157cd4 from qemu
2019-06-13 22:14:15 +00:00
{
return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false);
}
target/arm: Convert VADD to decodetree Convert the VADD instruction to decodetree. Backports commit ce28b303716e7eca3f3765bf6776d722ebbe1122 from qemu
2019-06-13 22:15:50 +00:00
static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a)
{
return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a)
target/arm: Convert VADD to decodetree Convert the VADD instruction to decodetree. Backports commit ce28b303716e7eca3f3765bf6776d722ebbe1122 from qemu
2019-06-13 22:15:50 +00:00
{
return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false);
}
target/arm: Convert VSUB to decodetree Convert the VSUB instruction to decodetree. Backports commit 8fec9a119264b7936503abce3c106fad7e3ccb76 from qemu.
2019-06-13 22:17:26 +00:00
static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a)
{
return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a)
target/arm: Convert VSUB to decodetree Convert the VSUB instruction to decodetree. Backports commit 8fec9a119264b7936503abce3c106fad7e3ccb76 from qemu.
2019-06-13 22:17:26 +00:00
{
return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false);
}
target/arm: Convert VDIV to decodetree Convert the VDIV instruction to decodetree. Backports commit 519ee7ae31e050eb0ff9ad35c213f0bd7ab1c03e from qemu
2019-06-13 22:19:44 +00:00
static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a)
{
return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false);
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
target/arm: Convert VDIV to decodetree Convert the VDIV instruction to decodetree. Backports commit 519ee7ae31e050eb0ff9ad35c213f0bd7ab1c03e from qemu
2019-06-13 22:19:44 +00:00
{
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
* VFNMS : fd = muladd(-fd, -fn, fm)
* VFMA : fd = muladd( fd, fn, fm)
* VFMS : fd = muladd( fd, -fn, fm)
*
* These are fused multiply-add, and must be done as one floating
* point operation with no rounding between the multiplication and
* addition steps. NB that doing the negations here as separate
* steps is correct : an input NaN should come out with its sign
* bit flipped if it is a negated-input.
*/
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 vn, vm, vd;
/*
* Present in VFPv4 only.
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Backports commit c52881bbc22b50db99a6c37171ad3eea7d959ae6 from qemu
2020-03-22 03:48:11 +00:00
* Note that we can't rely on the SIMDFMAC check alone, because
* in a Neon-no-VFP core that ID register field will be non-zero.
*/
if (!dc_isar_feature(aa32_simdfmac, s) ||
!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
/*
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Backports commit c52881bbc22b50db99a6c37171ad3eea7d959ae6 from qemu
2020-03-22 03:48:11 +00:00
if (s->vec_len != 0 || s->vec_stride != 0) {
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
vn = tcg_temp_new_i32(tcg_ctx);
vm = tcg_temp_new_i32(tcg_ctx);
vd = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, vn, a->vn);
neon_load_reg32(s, vm, a->vm);
if (a->o2) {
/* VFNMS, VFMS */
gen_helper_vfp_negs(tcg_ctx, vn, vn);
}
neon_load_reg32(s, vd, a->vd);
if (a->o1 & 1) {
/* VFNMA, VFNMS */
gen_helper_vfp_negs(tcg_ctx, vd, vd);
}
fpst = get_fpstatus_ptr(s, 0);
gen_helper_vfp_muladds(tcg_ctx, vd, vn, vm, vd, fpst);
neon_store_reg32(s, vd, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, vn);
tcg_temp_free_i32(tcg_ctx, vm);
tcg_temp_free_i32(tcg_ctx, vd);
return true;
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
* VFNMS : fd = muladd(-fd, -fn, fm)
* VFMA : fd = muladd( fd, fn, fm)
* VFMS : fd = muladd( fd, -fn, fm)
*
* These are fused multiply-add, and must be done as one floating
* point operation with no rounding between the multiplication and
* addition steps. NB that doing the negations here as separate
* steps is correct : an input NaN should come out with its sign
* bit flipped if it is a negated-input.
*/
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i64 vn, vm, vd;
/*
* Present in VFPv4 only.
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Backports commit c52881bbc22b50db99a6c37171ad3eea7d959ae6 from qemu
2020-03-22 03:48:11 +00:00
* Note that we can't rely on the SIMDFMAC check alone, because
* in a Neon-no-VFP core that ID register field will be non-zero.
*/
if (!dc_isar_feature(aa32_simdfmac, s) ||
!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
/*
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Backports commit c52881bbc22b50db99a6c37171ad3eea7d959ae6 from qemu
2020-03-22 03:48:11 +00:00
if (s->vec_len != 0 || s->vec_stride != 0) {
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vn | a->vm) & 0x10)) {
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
target/arm: Check for dp support for dp VFM, not sp In commit 1120827fa182f0e7622 we accidentally put the "UNDEF unless FPU has double-precision support" check in the single-precision VFM function. Put it in the dp function where it belongs. Backports commit 34bea4edb9bbe8edf4b8606276482acdff5ca58b from qemu
2019-06-25 23:56:32 +00:00
return false;
}
target/arm: Convert VFP fused multiply-add insns to decodetree Convert the VFP fused multiply-add instructions (VFNMA, VFNMS, VFMA, VFMS) to decodetree. Note that in the old decode structure we were implementing these to honour the VFP vector stride/length. These instructions were introduced in VFPv4, and in the v7A architecture they are UNPREDICTABLE if the vector stride or length are non-zero. In v8A they must UNDEF if stride or length are non-zero, like all VFP instructions; we choose to UNDEF always. Backports commit d4893b01d23060845ee3855bc96626e16aad9ab5 from qemu
2019-06-13 22:22:48 +00:00
if (!vfp_access_check(s)) {
return true;
}
vn = tcg_temp_new_i64(tcg_ctx);
vm = tcg_temp_new_i64(tcg_ctx);
vd = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, vn, a->vn);
neon_load_reg64(s, vm, a->vm);
if (a->o2) {
/* VFNMS, VFMS */
gen_helper_vfp_negd(tcg_ctx, vn, vn);
}
neon_load_reg64(s, vd, a->vd);
if (a->o1 & 1) {
/* VFNMA, VFNMS */
gen_helper_vfp_negd(tcg_ctx, vd, vd);
}
fpst = get_fpstatus_ptr(s, 0);
gen_helper_vfp_muladdd(tcg_ctx, vd, vn, vm, vd, fpst);
neon_store_reg64(s, vd, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i64(tcg_ctx, vn);
tcg_temp_free_i64(tcg_ctx, vm);
tcg_temp_free_i64(tcg_ctx, vd);
return true;
}
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i32 fd;
target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm The AArch32 VMOV (immediate) instruction uses the same VFP encoded immediate format we already handle in vfp_expand_imm(). Use that function rather than hand-decoding it. Backports commit 9bee50b498410ed6466018b26464d7384c7879e9 from qemu
2019-06-25 23:19:43 +00:00
uint32_t vd;
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
vd = a->vd;
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (!dc_isar_feature(aa32_fpsp_v3, s)) {
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
return false;
}
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (veclen > 0) {
/* Figure out what type of vector operation this is. */
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_sreg_is_scalar(vd)) {
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
/* scalar */
veclen = 0;
} else {
delta_d = s->vec_stride + 1;
}
}
target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm The AArch32 VMOV (immediate) instruction uses the same VFP encoded immediate format we already handle in vfp_expand_imm(). Use that function rather than hand-decoding it. Backports commit 9bee50b498410ed6466018b26464d7384c7879e9 from qemu
2019-06-25 23:19:43 +00:00
fd = tcg_const_i32(tcg_ctx, vfp_expand_imm(MO_32, a->imm));
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
for (;;) {
neon_store_reg32(s, fd, vd);
if (veclen == 0) {
break;
}
/* Set up the operands for the next iteration */
veclen--;
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
vd = vfp_advance_sreg(vd, delta_d);
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
}
tcg_temp_free_i32(tcg_ctx, fd);
return true;
}
static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i64 fd;
target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm The AArch32 VMOV (immediate) instruction uses the same VFP encoded immediate format we already handle in vfp_expand_imm(). Use that function rather than hand-decoding it. Backports commit 9bee50b498410ed6466018b26464d7384c7879e9 from qemu
2019-06-25 23:19:43 +00:00
uint32_t vd;
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
vd = a->vd;
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (!dc_isar_feature(aa32_fpdp_v3, s)) {
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
if (veclen > 0) {
/* Figure out what type of vector operation this is. */
target/arm: Fix short-vector increment behaviour For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations Backports commit 18cf951af9a27ae573a6fa17f9d0c103f7b7679b from qemu
2019-06-13 23:44:25 +00:00
if (vfp_dreg_is_scalar(vd)) {
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
/* scalar */
veclen = 0;
} else {
delta_d = (s->vec_stride >> 1) + 1;
}
}
target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm The AArch32 VMOV (immediate) instruction uses the same VFP encoded immediate format we already handle in vfp_expand_imm(). Use that function rather than hand-decoding it. Backports commit 9bee50b498410ed6466018b26464d7384c7879e9 from qemu
2019-06-25 23:19:43 +00:00
fd = tcg_const_i64(tcg_ctx, vfp_expand_imm(MO_64, a->imm));
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
for (;;) {
neon_store_reg64(s, fd, vd);
if (veclen == 0) {
break;
}
/* Set up the operands for the next iteration */
veclen--;
target/arm: Correct VMOV_imm_dp handling of short vectors Coverity points out (CID 1402195) that the loop in trans_VMOV_imm_dp() that iterates over the destination registers in a short-vector VMOV accidentally throws away the returned updated register number from vfp_advance_dreg(). Add the missing assignment. (We got this correct in trans_VMOV_imm_sp().) Backports commit 89a11ff756410aecb87d2c774df6e45dbf4105c1 from qemu
2019-08-08 22:08:53 +00:00
vd = vfp_advance_dreg(vd, delta_d);
target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu
2019-06-13 22:37:51 +00:00
}
tcg_temp_free_i64(tcg_ctx, fd);
return true;
}
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
target/arm: Convert VMOV (register) to decodetree Backports commit 17552b979ebb9848a534c25ebed18a1072710058 from qemu
2019-06-13 22:49:45 +00:00
static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a)
{
return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm);
}
static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a)
{
return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm);
}
target/arm: Convert VABS to decodetree Convert the VFP VABS instruction to decodetree. Unlike the 3-op versions, we don't pass fpst to the VFPGen2OpSPFn or VFPGen2OpDPFn because none of the operations which use this format and support short vectors will need it. Backports commit 90287e22c987e9840704345ed33d237cbe759dd9 from qemu
2019-06-13 22:41:41 +00:00
static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
{
return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
}
static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a)
{
return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
}
target/arm: Convert VNEG to decodetree Convert the VNEG instruction to decodetree. Backports commit 1882651afdb0ca44f0631192fbe65a71c660d809 from qemu
2019-06-13 22:43:49 +00:00
static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a)
{
return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm);
}
static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
{
return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
}
target/arm: Convert VSQRT to decodetree Convert the VSQRT instruction to decodetree. Backports commit b8474540cbce4e2fa45010416375d1bcbe86dc15 from qemu
2019-06-13 22:45:42 +00:00
static void gen_VSQRT_sp(TCGContext *tcg_ctx, TCGv_i32 vd, TCGv_i32 vm)
{
gen_helper_vfp_sqrts(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
}
static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a)
{
return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm);
}
static void gen_VSQRT_dp(TCGContext *tcg_ctx, TCGv_i64 vd, TCGv_i64 vm)
{
gen_helper_vfp_sqrtd(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
}
static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a)
{
return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm);
}
target/arm: Convert VFP comparison insns to decodetree Convert the VFP comparison instructions to decodetree. Note that comparison instructions should not honour the VFP short-vector length and stride information: they are scalar-only operations. This applies to all the 2-operand instructions except for VMOV, VABS, VNEG and VSQRT. (In the old decoder this is implemented via the "if (op == 15 && rn > 3) { veclen = 0; }" check.) Backports commit 386bba2368842fc74388a3c1651c6c0c0c70adbd from qemu
2019-06-13 22:54:16 +00:00
static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vd, vm;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert VFP comparison insns to decodetree Convert the VFP comparison instructions to decodetree. Note that comparison instructions should not honour the VFP short-vector length and stride information: they are scalar-only operations. This applies to all the 2-operand instructions except for VMOV, VABS, VNEG and VSQRT. (In the old decoder this is implemented via the "if (op == 15 && rn > 3) { veclen = 0; }" check.) Backports commit 386bba2368842fc74388a3c1651c6c0c0c70adbd from qemu
2019-06-13 22:54:16 +00:00
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
vd = tcg_temp_new_i32(tcg_ctx);
vm = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, vd, a->vd);
if (a->z) {
tcg_gen_movi_i32(tcg_ctx, vm, 0);
} else {
neon_load_reg32(s, vm, a->vm);
}
if (a->e) {
gen_helper_vfp_cmpes(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
} else {
gen_helper_vfp_cmps(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
}
tcg_temp_free_i32(tcg_ctx, vd);
tcg_temp_free_i32(tcg_ctx, vm);
return true;
}
static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 vd, vm;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
target/arm: Convert VFP comparison insns to decodetree Convert the VFP comparison instructions to decodetree. Note that comparison instructions should not honour the VFP short-vector length and stride information: they are scalar-only operations. This applies to all the 2-operand instructions except for VMOV, VABS, VNEG and VSQRT. (In the old decoder this is implemented via the "if (op == 15 && rn > 3) { veclen = 0; }" check.) Backports commit 386bba2368842fc74388a3c1651c6c0c0c70adbd from qemu
2019-06-13 22:54:16 +00:00
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
target/arm: Rename isar_feature_aa32_simd_r32 The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Backports commit 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba from qemu
2020-03-21 23:37:29 +00:00
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
target/arm: Convert VFP comparison insns to decodetree Convert the VFP comparison instructions to decodetree. Note that comparison instructions should not honour the VFP short-vector length and stride information: they are scalar-only operations. This applies to all the 2-operand instructions except for VMOV, VABS, VNEG and VSQRT. (In the old decoder this is implemented via the "if (op == 15 && rn > 3) { veclen = 0; }" check.) Backports commit 386bba2368842fc74388a3c1651c6c0c0c70adbd from qemu
2019-06-13 22:54:16 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
vd = tcg_temp_new_i64(tcg_ctx);
vm = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, vd, a->vd);
if (a->z) {
tcg_gen_movi_i64(tcg_ctx, vm, 0);
} else {
neon_load_reg64(s, vm, a->vm);
}
if (a->e) {
gen_helper_vfp_cmped(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
} else {
gen_helper_vfp_cmpd(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
}
tcg_temp_free_i64(tcg_ctx, vd);
tcg_temp_free_i64(tcg_ctx, vm);
return true;
}
target/arm: Convert the VCVT-from-f16 insns to decodetree Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Backports commit b623d803dda805f07aadcbf098961fde27315c19 from qemu
2019-06-13 22:59:06 +00:00
static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 ahp_mode;
TCGv_i32 tmp;
if (!dc_isar_feature(aa32_fp16_spconv, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, false);
ahp_mode = get_ahp_flag(s);
tmp = tcg_temp_new_i32(tcg_ctx);
/* The T bit tells us if we want the low or high 16 bits of Vm */
tcg_gen_ld16u_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, vfp_f16_offset(a->vm, a->t));
gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tmp, tmp, fpst, ahp_mode);
neon_store_reg32(s, tmp, a->vd);
tcg_temp_free_i32(tcg_ctx, ahp_mode);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 ahp_mode;
TCGv_i32 tmp;
TCGv_i64 vd;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert the VCVT-from-f16 insns to decodetree Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Backports commit b623d803dda805f07aadcbf098961fde27315c19 from qemu
2019-06-13 22:59:06 +00:00
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
target/arm: Convert the VCVT-from-f16 insns to decodetree Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Backports commit b623d803dda805f07aadcbf098961fde27315c19 from qemu
2019-06-13 22:59:06 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert the VCVT-from-f16 insns to decodetree Convert the VCVTT, VCVTB instructions that deal with conversion from half-precision floats to f32 or 64 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit load of the right half of the input single-precision register rather than loading the full 32 bits and then doing a separate shift or sign-extension. Backports commit b623d803dda805f07aadcbf098961fde27315c19 from qemu
2019-06-13 22:59:06 +00:00
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, false);
ahp_mode = get_ahp_flag(s);
tmp = tcg_temp_new_i32(tcg_ctx);
/* The T bit tells us if we want the low or high 16 bits of Vm */
tcg_gen_ld16u_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, vfp_f16_offset(a->vm, a->t));
vd = tcg_temp_new_i64(tcg_ctx);
gen_helper_vfp_fcvt_f16_to_f64(tcg_ctx, vd, tmp, fpst, ahp_mode);
neon_store_reg64(s, vd, a->vd);
tcg_temp_free_i32(tcg_ctx, ahp_mode);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
tcg_temp_free_i64(tcg_ctx, vd);
return true;
}
target/arm: Convert the VCVT-to-f16 insns to decodetree Convert the VCVTT and VCVTB instructions which convert from f32 and f64 to f16 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit store of the right half of the input single-precision register rather than doing a load/modify/store sequence on the full 32 bits. Backports commit cdfd14e86ab0b1ca29a702d13a8e4af2e902a9bf from qemu
2019-06-13 23:03:54 +00:00
static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 ahp_mode;
TCGv_i32 tmp;
if (!dc_isar_feature(aa32_fp16_spconv, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, false);
ahp_mode = get_ahp_flag(s);
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm);
gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp, tmp, fpst, ahp_mode);
tcg_gen_st16_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, vfp_f16_offset(a->vd, a->t));
tcg_temp_free_i32(tcg_ctx, ahp_mode);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 ahp_mode;
TCGv_i32 tmp;
TCGv_i64 vm;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert the VCVT-to-f16 insns to decodetree Convert the VCVTT and VCVTB instructions which convert from f32 and f64 to f16 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit store of the right half of the input single-precision register rather than doing a load/modify/store sequence on the full 32 bits. Backports commit cdfd14e86ab0b1ca29a702d13a8e4af2e902a9bf from qemu
2019-06-13 23:03:54 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
target/arm: Convert the VCVT-to-f16 insns to decodetree Convert the VCVTT and VCVTB instructions which convert from f32 and f64 to f16 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit store of the right half of the input single-precision register rather than doing a load/modify/store sequence on the full 32 bits. Backports commit cdfd14e86ab0b1ca29a702d13a8e4af2e902a9bf from qemu
2019-06-13 23:03:54 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert the VCVT-to-f16 insns to decodetree Convert the VCVTT and VCVTB instructions which convert from f32 and f64 to f16 to decodetree. Since we're no longer constrained to the old decoder's style using cpu_F0s and cpu_F0d we can perform a direct 16 bit store of the right half of the input single-precision register rather than doing a load/modify/store sequence on the full 32 bits. Backports commit cdfd14e86ab0b1ca29a702d13a8e4af2e902a9bf from qemu
2019-06-13 23:03:54 +00:00
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, false);
ahp_mode = get_ahp_flag(s);
tmp = tcg_temp_new_i32(tcg_ctx);
vm = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, vm, a->vm);
gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tmp, vm, fpst, ahp_mode);
tcg_temp_free_i64(tcg_ctx, vm);
tcg_gen_st16_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, vfp_f16_offset(a->vd, a->t));
tcg_temp_free_i32(tcg_ctx, ahp_mode);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 tmp;
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm);
fpst = get_fpstatus_ptr(s, false);
gen_helper_rints(tcg_ctx, tmp, tmp, fpst);
neon_store_reg32(s, tmp, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i64 tmp;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_vrint, s)) {
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
if (!vfp_access_check(s)) {
return true;
}
tmp = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, tmp, a->vm);
fpst = get_fpstatus_ptr(s, false);
gen_helper_rintd(tcg_ctx, tmp, tmp, fpst);
neon_store_reg64(s, tmp, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
return true;
}
static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 tmp;
TCGv_i32 tcg_rmode;
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm);
fpst = get_fpstatus_ptr(s, false);
tcg_rmode = tcg_const_i32(tcg_ctx, float_round_to_zero);
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
gen_helper_rints(tcg_ctx, tmp, tmp, fpst);
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
neon_store_reg32(s, tmp, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tcg_rmode);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
target/arm: Fix typos in trans function prototypes In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Backports commit 83655223ac6143a563e981906ce13fd6f2cfbefd from qemu
2019-06-25 23:48:32 +00:00
static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i64 tmp;
TCGv_i32 tcg_rmode;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_vrint, s)) {
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
if (!vfp_access_check(s)) {
return true;
}
tmp = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, tmp, a->vm);
fpst = get_fpstatus_ptr(s, false);
tcg_rmode = tcg_const_i32(tcg_ctx, float_round_to_zero);
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
gen_helper_rintd(tcg_ctx, tmp, tmp, fpst);
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
neon_store_reg64(s, tmp, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
tcg_temp_free_i32(tcg_ctx, tcg_rmode);
return true;
}
static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i32 tmp;
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
tmp = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, tmp, a->vm);
fpst = get_fpstatus_ptr(s, false);
gen_helper_rints_exact(tcg_ctx, tmp, tmp, fpst);
neon_store_reg32(s, tmp, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i32(tcg_ctx, tmp);
return true;
}
static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_ptr fpst;
TCGv_i64 tmp;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_vrint, s)) {
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VFP round insns to decodetree Convert the VFP round-to-integer instructions VRINTR, VRINTZ and VRINTX to decodetree. These instructions were only introduced as part of the "VFP misc" additions in v8A, so we check this. The old decoder's implementation was incorrectly providing them even for v7A CPUs. Backports commit e25155f55dc4abb427a88dfe58bbbc550fe7d643 from qemu
2019-06-13 23:14:59 +00:00
if (!vfp_access_check(s)) {
return true;
}
tmp = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, tmp, a->vm);
fpst = get_fpstatus_ptr(s, false);
gen_helper_rintd_exact(tcg_ctx, tmp, tmp, fpst);
neon_store_reg64(s, tmp, a->vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
tcg_temp_free_i64(tcg_ctx, tmp);
return true;
}
target/arm: Convert double-single precision conversion insns to decodetree Convert the VCVT double/single precision conversion insns to decodetree. Backports commit 6ed7e49c3693ed8411773c4880f42b2932beb12d from qemu
2019-06-13 23:18:00 +00:00
static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 vd;
TCGv_i32 vm;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert double-single precision conversion insns to decodetree Convert the VCVT double/single precision conversion insns to decodetree. Backports commit 6ed7e49c3693ed8411773c4880f42b2932beb12d from qemu
2019-06-13 23:18:00 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert double-single precision conversion insns to decodetree Convert the VCVT double/single precision conversion insns to decodetree. Backports commit 6ed7e49c3693ed8411773c4880f42b2932beb12d from qemu
2019-06-13 23:18:00 +00:00
if (!vfp_access_check(s)) {
return true;
}
vm = tcg_temp_new_i32(tcg_ctx);
vd = tcg_temp_new_i64(tcg_ctx);
neon_load_reg32(s, vm, a->vm);
gen_helper_vfp_fcvtds(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
neon_store_reg64(s, vd, a->vd);
tcg_temp_free_i32(tcg_ctx, vm);
tcg_temp_free_i64(tcg_ctx, vd);
return true;
}
static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 vm;
TCGv_i32 vd;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert double-single precision conversion insns to decodetree Convert the VCVT double/single precision conversion insns to decodetree. Backports commit 6ed7e49c3693ed8411773c4880f42b2932beb12d from qemu
2019-06-13 23:18:00 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert double-single precision conversion insns to decodetree Convert the VCVT double/single precision conversion insns to decodetree. Backports commit 6ed7e49c3693ed8411773c4880f42b2932beb12d from qemu
2019-06-13 23:18:00 +00:00
if (!vfp_access_check(s)) {
return true;
}
vd = tcg_temp_new_i32(tcg_ctx);
vm = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, vm, a->vm);
gen_helper_vfp_fcvtsd(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
neon_store_reg32(s, vd, a->vd);
tcg_temp_free_i32(tcg_ctx, vd);
tcg_temp_free_i64(tcg_ctx, vm);
return true;
}
target/arm: Convert integer-to-float insns to decodetree Convert the VCVT integer-to-float instructions to decodetree. Backports commit 8fc9d8918cde342c71923e361b9f2193e36ed18b from qemu
2019-06-13 23:20:39 +00:00
static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vm;
TCGv_ptr fpst;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert integer-to-float insns to decodetree Convert the VCVT integer-to-float instructions to decodetree. Backports commit 8fc9d8918cde342c71923e361b9f2193e36ed18b from qemu
2019-06-13 23:20:39 +00:00
if (!vfp_access_check(s)) {
return true;
}
vm = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, vm, a->vm);
fpst = get_fpstatus_ptr(s, false);
if (a->s) {
/* i32 -> f32 */
gen_helper_vfp_sitos(tcg_ctx, vm, vm, fpst);
} else {
/* u32 -> f32 */
gen_helper_vfp_uitos(tcg_ctx, vm, vm, fpst);
}
neon_store_reg32(s, vm, a->vd);
tcg_temp_free_i32(tcg_ctx, vm);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vm;
TCGv_i64 vd;
TCGv_ptr fpst;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert integer-to-float insns to decodetree Convert the VCVT integer-to-float instructions to decodetree. Backports commit 8fc9d8918cde342c71923e361b9f2193e36ed18b from qemu
2019-06-13 23:20:39 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert integer-to-float insns to decodetree Convert the VCVT integer-to-float instructions to decodetree. Backports commit 8fc9d8918cde342c71923e361b9f2193e36ed18b from qemu
2019-06-13 23:20:39 +00:00
if (!vfp_access_check(s)) {
return true;
}
vm = tcg_temp_new_i32(tcg_ctx);
vd = tcg_temp_new_i64(tcg_ctx);
neon_load_reg32(s, vm, a->vm);
fpst = get_fpstatus_ptr(s, false);
if (a->s) {
/* i32 -> f64 */
gen_helper_vfp_sitod(tcg_ctx, vd, vm, fpst);
} else {
/* u32 -> f64 */
gen_helper_vfp_uitod(tcg_ctx, vd, vm, fpst);
}
neon_store_reg64(s, vd, a->vd);
tcg_temp_free_i32(tcg_ctx, vm);
tcg_temp_free_i64(tcg_ctx, vd);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
target/arm: Convert VJCVT to decodetree Convert the VJCVT instruction to decodetree. Backports commit 92073e947487e2109f3dfebfeaa48d6323cbd981 from qemu
2019-06-13 23:30:20 +00:00
static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vd;
TCGv_i64 vm;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert VJCVT to decodetree Convert the VJCVT instruction to decodetree. Backports commit 92073e947487e2109f3dfebfeaa48d6323cbd981 from qemu
2019-06-13 23:30:20 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_jscvt, s)) {
target/arm: Convert VJCVT to decodetree Convert the VJCVT instruction to decodetree. Backports commit 92073e947487e2109f3dfebfeaa48d6323cbd981 from qemu
2019-06-13 23:30:20 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VJCVT to decodetree Convert the VJCVT instruction to decodetree. Backports commit 92073e947487e2109f3dfebfeaa48d6323cbd981 from qemu
2019-06-13 23:30:20 +00:00
if (!vfp_access_check(s)) {
return true;
}
vm = tcg_temp_new_i64(tcg_ctx);
vd = tcg_temp_new_i32(tcg_ctx);
neon_load_reg64(s, vm, a->vm);
gen_helper_vjcvt(tcg_ctx, vd, vm, tcg_ctx->cpu_env);
neon_store_reg32(s, vd, a->vd);
tcg_temp_free_i64(tcg_ctx, vm);
tcg_temp_free_i32(tcg_ctx, vd);
return true;
}
target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree Convert the VCVT (between floating-point and fixed-point) instructions to decodetree. Backports commit e3d6f4290c788e850c64815f0b3e331600a4bcc0 from qemu
2019-06-13 23:34:05 +00:00
static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vd, shift;
TCGv_ptr fpst;
int frac_bits;
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (!dc_isar_feature(aa32_fpsp_v3, s)) {
target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree Convert the VCVT (between floating-point and fixed-point) instructions to decodetree. Backports commit e3d6f4290c788e850c64815f0b3e331600a4bcc0 from qemu
2019-06-13 23:34:05 +00:00
return false;
}
if (!vfp_access_check(s)) {
return true;
}
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
vd = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, vd, a->vd);
fpst = get_fpstatus_ptr(s, false);
shift = tcg_const_i32(tcg_ctx, frac_bits);
/* Switch on op:U:sx bits */
switch (a->opc) {
case 0:
gen_helper_vfp_shtos(tcg_ctx, vd, vd, shift, fpst);
break;
case 1:
gen_helper_vfp_sltos(tcg_ctx, vd, vd, shift, fpst);
break;
case 2:
gen_helper_vfp_uhtos(tcg_ctx, vd, vd, shift, fpst);
break;
case 3:
gen_helper_vfp_ultos(tcg_ctx, vd, vd, shift, fpst);
break;
case 4:
gen_helper_vfp_toshs_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
case 5:
gen_helper_vfp_tosls_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
case 6:
gen_helper_vfp_touhs_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
case 7:
gen_helper_vfp_touls_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
default:
g_assert_not_reached();
}
neon_store_reg32(s, vd, a->vd);
tcg_temp_free_i32(tcg_ctx, vd);
tcg_temp_free_i32(tcg_ctx, shift);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i64 vd;
TCGv_i32 shift;
TCGv_ptr fpst;
int frac_bits;
target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Backports commit 84774cc37f2c17e48a4867a8e8e055deb23bea69 from qemu
2020-03-22 03:33:11 +00:00
if (!dc_isar_feature(aa32_fpdp_v3, s)) {
target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree Convert the VCVT (between floating-point and fixed-point) instructions to decodetree. Backports commit e3d6f4290c788e850c64815f0b3e331600a4bcc0 from qemu
2019-06-13 23:34:05 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree Convert the VCVT (between floating-point and fixed-point) instructions to decodetree. Backports commit e3d6f4290c788e850c64815f0b3e331600a4bcc0 from qemu
2019-06-13 23:34:05 +00:00
if (!vfp_access_check(s)) {
return true;
}
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
vd = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, vd, a->vd);
fpst = get_fpstatus_ptr(s, false);
shift = tcg_const_i32(tcg_ctx, frac_bits);
/* Switch on op:U:sx bits */
switch (a->opc) {
case 0:
gen_helper_vfp_shtod(tcg_ctx, vd, vd, shift, fpst);
break;
case 1:
gen_helper_vfp_sltod(tcg_ctx, vd, vd, shift, fpst);
break;
case 2:
gen_helper_vfp_uhtod(tcg_ctx, vd, vd, shift, fpst);
break;
case 3:
gen_helper_vfp_ultod(tcg_ctx, vd, vd, shift, fpst);
break;
case 4:
gen_helper_vfp_toshd_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
case 5:
gen_helper_vfp_tosld_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
case 6:
gen_helper_vfp_touhd_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
case 7:
gen_helper_vfp_tould_round_to_zero(tcg_ctx, vd, vd, shift, fpst);
break;
default:
g_assert_not_reached();
}
neon_store_reg64(s, vd, a->vd);
tcg_temp_free_i64(tcg_ctx, vd);
tcg_temp_free_i32(tcg_ctx, shift);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
target/arm: Convert float-to-integer VCVT insns to decodetree Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Backports commit 3111bfc2da6ba0c8396dc97ca479942d711c6146 from qemu
2019-06-13 23:39:58 +00:00
static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vm;
TCGv_ptr fpst;
target/arm: Add missing checks for fpsp_v2 We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Backports commit 82f6abe16b9b951180657c5fe15942d5214aa12e from qemu
2020-03-22 03:42:25 +00:00
if (!dc_isar_feature(aa32_fpsp_v2, s)) {
return false;
}
target/arm: Convert float-to-integer VCVT insns to decodetree Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Backports commit 3111bfc2da6ba0c8396dc97ca479942d711c6146 from qemu
2019-06-13 23:39:58 +00:00
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, false);
vm = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, vm, a->vm);
if (a->s) {
if (a->rz) {
gen_helper_vfp_tosizs(tcg_ctx, vm, vm, fpst);
} else {
gen_helper_vfp_tosis(tcg_ctx, vm, vm, fpst);
}
} else {
if (a->rz) {
gen_helper_vfp_touizs(tcg_ctx, vm, vm, fpst);
} else {
gen_helper_vfp_touis(tcg_ctx, vm, vm, fpst);
}
}
neon_store_reg32(s, vm, a->vd);
tcg_temp_free_i32(tcg_ctx, vm);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 vd;
TCGv_i64 vm;
TCGv_ptr fpst;
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
target/arm: Convert float-to-integer VCVT insns to decodetree Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Backports commit 3111bfc2da6ba0c8396dc97ca479942d711c6146 from qemu
2019-06-13 23:39:58 +00:00
return false;
}
target/arm: Perform fpdp_v2 check first Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Backports commit 799449abda137153a0e68b8788d8e1486f389490 from qemu
2020-03-22 03:29:05 +00:00
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
target/arm: Only implement doubles if the FPU supports them The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
2019-06-25 23:55:23 +00:00
return false;
}
target/arm: Convert float-to-integer VCVT insns to decodetree Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Backports commit 3111bfc2da6ba0c8396dc97ca479942d711c6146 from qemu
2019-06-13 23:39:58 +00:00
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, false);
vm = tcg_temp_new_i64(tcg_ctx);
vd = tcg_temp_new_i32(tcg_ctx);
neon_load_reg64(s, vm, a->vm);
if (a->s) {
if (a->rz) {
gen_helper_vfp_tosizd(tcg_ctx, vd, vm, fpst);
} else {
gen_helper_vfp_tosid(tcg_ctx, vd, vm, fpst);
}
} else {
if (a->rz) {
gen_helper_vfp_touizd(tcg_ctx, vd, vm, fpst);
} else {
gen_helper_vfp_touid(tcg_ctx, vd, vm, fpst);
}
}
neon_store_reg32(s, vd, a->vd);
tcg_temp_free_i32(tcg_ctx, vd);
tcg_temp_free_i64(tcg_ctx, vm);
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
target/arm: Move VLLDM and VLSTM to vfp.decode Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Backports commit dc778a6873f534817a13257be2acba3ca87ec015 from qemu
2020-03-22 03:51:57 +00:00
/*
* Decode VLLDM and VLSTM are nonstandard because:
* * if there is no FPU then these insns must NOP in
* Secure state and UNDEF in Nonsecure state
* * if there is an FPU then these insns do not have
* the usual behaviour that vfp_access_check() provides of
* being controlled by CPACR/NSACR enable bits or the
* lazy-stacking logic.
*/
static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv_i32 fptr;
if (!arm_dc_feature(s, ARM_FEATURE_M) ||
!arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
/* If not secure, UNDEF. */
if (!s->v8m_secure) {
return false;
}
/* If no fpu, NOP. */
if (!dc_isar_feature(aa32_vfp, s)) {
return true;
}
fptr = load_reg(s, a->rn);
if (a->l) {
gen_helper_v7m_vlldm(tcg_ctx, tcg_ctx->cpu_env, fptr);
} else {
gen_helper_v7m_vlstm(tcg_ctx, tcg_ctx->cpu_env, fptr);
}
tcg_temp_free_i32(tcg_ctx, fptr);
/* End the TB, because we have updated FP control bits */
s->base.is_jmp = DISAS_UPDATE;
return true;
}
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