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89 commits

Author SHA1 Message Date
Michael Clark b247ee234d
RISC-V: Update load reservation comment in do_interrupt
Backports commit d9360e96885dbd69ce4aa925d1701c7a10cf54ae from qemu
2019-03-19 23:58:31 -04:00
Michael Clark d3dbcb6dfc
RISC-V: Add support for vectored interrupts
If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu
2019-03-19 23:58:31 -04:00
Michael Clark 8ffa68e757
RISC-V: Change local interrupts from edge to level
This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.

Fixes WFI doesn't return when a IPI is issued:

- https://github.com/riscv/riscv-qemu/issues/132

To test:

1) Apply RISC-V Linux CPU hotplug patch:

- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html

2) Enable CONFIG_CPU_HOTPLUG in linux .config

3) Try to offline and online cpus:

echo 1 > /sys/devices/system/cpu/cpu2/online
echo 0 > /sys/devices/system/cpu/cpu2/online
echo 1 > /sys/devices/system/cpu/cpu2/online

Backports commit d26f5a423438e579d3ff0ca35e44edb966a36233 from qemu
2019-03-19 23:58:31 -04:00
Kito Cheng bd3e9ebaea
RISC-V: linux-user support for RVE ABI
This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Backports relevant parts of 5836c3eccedb6dfab16b8f606f2de24b8938b69c
from qemu
2019-03-19 23:58:31 -04:00
Michael Clark 2e0c040062
RISC-V: Allow interrupt controllers to claim interrupts
We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.

This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.

This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.

Backports commit e3e7039cc24ecf47d81c091e8bb04552d6564ad8 from qemu
2019-03-19 23:48:12 -04:00
Alistair Francis a4f2dcde28
riscv: pmp: Log pmp access errors as guest errors
Backports commit aad5ac2311f3ad2c0be12d0eaaf4ef4398438fc2 from qemu
2019-03-19 23:45:03 -04:00
Jim Wilson 65903cf9a4
RISC-V: Add debug support for accessing CSRs.
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.

Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
2019-03-19 23:42:48 -04:00
Jim Wilson 30ab335bb3
RISC-V: Fixes to CSR_* register macros.
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu
2019-03-19 23:39:49 -04:00
Bastian Koppelmann c0f036578c
target/riscv: Fix manually parsed 16 bit insn
during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.

Backports commit f330433b3633647b047cfa418c2ca4d18fda69c7 from qemu
2019-03-19 05:44:58 -04:00
Bastian Koppelmann e96282eb28
target/riscv: Remove decode_RV32_64G()
decodetree handles all instructions now so the fallback is not necessary
anymore.

Backports commit 25e6ca30c668783cd72ff97080ff44e141b99f9b from qemu
2019-03-19 05:37:42 -04:00
Bastian Koppelmann a371684da9
target/riscv: Remove gen_system()
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Backports commit 8f7bc273868939f0821e07fb23792db63d45bffb from qemu
2019-03-19 05:36:48 -04:00
Bastian Koppelmann 1765e6a090
target/riscv: Rename trans_arith to gen_arith
Backports commit 8dc9e8a8b04c4308cf275aa6480d289dcd3cf9b3 from qemu
2019-03-19 05:35:44 -04:00
Bastian Koppelmann 28daad082b
target/riscv: Remove manual decoding of RV32/64M insn
Backports commit 1288701682d81b93f62e01cd87001dc90b30b881 from qemu
2019-03-19 05:34:32 -04:00
Bastian Koppelmann b9eda7c464
target/riscv: Remove shift and slt insn manual decoding
Backports commit 34446e845829f55eaa9a07a915950af0b2710b47 from qemu
2019-03-19 05:23:47 -04:00
Bastian Koppelmann 177726afb8
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Backports commit f2ab1728675772cd475a33f4df3d2f68a22c188f from qemu
2019-03-19 05:17:54 -04:00
Bastian Koppelmann cb7c94fbc4
target/riscv: Move gen_arith_imm() decoding into trans_* functions
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.

Backports commit 7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130 from qemu
2019-03-19 05:14:21 -04:00
Bastian Koppelmann 6190837e2f
target/riscv: Remove manual decoding from gen_store()
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.

Backports commit bce8a342a1f0919479d18ec812b100136daa746b from qemu
2019-03-19 05:05:14 -04:00
Bastian Koppelmann f91f286ed2
target/riscv: Remove manual decoding from gen_load()
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.

Backports commit 98898b20e9cca462843c22ad952c216ffd57d654 from qemu
2019-03-19 05:02:25 -04:00
Bastian Koppelmann 6f89816f5d
target/riscv: Remove manual decoding from gen_branch()
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.

Backports commit 090cc2c898a04e42350eabf1bcf7d245471603f9 from qemu
2019-03-19 04:59:08 -04:00
Bastian Koppelmann 3fe4cf353c
target/riscv: Remove gen_jalr()
trans_jalr() is the only caller, so move the code into trans_jalr().

Backports commit 9e92c57d834cd50ab088d75510c3c720878eef13 from qemu
2019-03-19 04:55:52 -04:00
Bastian Koppelmann 580457a1d2
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
2019-03-19 04:53:07 -04:00
Bastian Koppelmann b4854e3340
target/riscv: Convert quadrant 1 of RVXC insns to decodetree
Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 04:50:08 -04:00
Lioncash 8d294a7897
target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-19 04:45:53 -04:00
Bastian Koppelmann 67164f2b29
target/riscv: Convert RV priv insns to decodetree
Backports commit 4ba79c47a205b3af4b62b9b1b6090dee678a1069 from qemu
2019-03-19 04:40:24 -04:00
Bastian Koppelmann 7475207aba
target/riscv: Convert RV64D insns to decodetree
Backports commit 31fe4d35f2608daecb2319c81e0bb4af81b398ae from qemu
2019-03-18 16:57:16 -04:00
Bastian Koppelmann 71f2ed2959
target/riscv: Convert RV32D insns to decodetree
Backports commit 97f8b49372d73aab4d172df4ea297d7f3ce4e02e from qemu
2019-03-18 16:51:20 -04:00
Bastian Koppelmann d8d107ec85
target/riscv: Convert RV64F insns to decodetree
Backports commit 95561ee3b41a536cc373e59da10605e2a8676ee2 from qemu
2019-03-18 16:43:17 -04:00
Bastian Koppelmann 9edaf2069e
target/riscv: Convert RV32F insns to decodetree
Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu
2019-03-18 16:40:04 -04:00
Bastian Koppelmann 3f9177f6e7
target/riscv: Convert RV64A insns to decodetree
Backports commit 40b9faecfe8000520958f50a77ea16f4b3dd6405 from qemu
2019-03-18 16:27:53 -04:00
Bastian Koppelmann 81013f9e2b
target/riscv: Convert RV32A insns to decodetree
Backports commit 3b77c289aef21b33517f2fd7639cce13bed50cc1 from qemu
2019-03-18 16:25:50 -04:00
Bastian Koppelmann 3a5da0b939
target/riscv: Convert RVXM insns to decodetree
Backports commit d2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1 from qemu
2019-03-18 16:20:29 -04:00
Bastian Koppelmann 4ea449a809
target/riscv: Convert RVXI csr insns to decodetree
Backports commit 771fbe156a2a2be964a4fbe6251339a5570a26c4 from qemu
2019-03-18 16:17:59 -04:00
Bastian Koppelmann de580ee378
target/riscv: Convert RVXI fence insns to decodetree
Backports commit 0c865e856a7e97d37c4dea4cf2ff875faa6e72ed from qemu
2019-03-18 16:09:21 -04:00
Bastian Koppelmann 11e2b9c410
target/riscv: Convert RVXI arithmetic insns to decodetree
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.

Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu
2019-03-18 16:04:49 -04:00
Bastian Koppelmann 1024ceb4df
target/riscv: Convert RV64I load/store insns to decodetree
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.

Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu
2019-03-18 16:02:16 -04:00
Bastian Koppelmann 65a415372b
target/riscv: Convert RV32I load/store insns to decodetree
Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu
2019-03-18 15:59:43 -04:00
Bastian Koppelmann 55dc0038e8
target/riscv: Convert RVXI branch insns to decodetree
Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu
2019-03-18 15:58:16 -04:00
Bastian Koppelmann 5e5b3e9ea9
target/riscv: Activate decodetree and implemnt LUI & AUIPC
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.

Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu
2019-03-18 15:54:17 -04:00
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
2019-03-08 21:46:10 -05:00