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138 commits

Author SHA1 Message Date
Corey Wharton bc097bd2ae target/riscv: Add a sifive-e34 cpu type 
The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.

Backports commit d784733bf1875c1ba355c69739518f24d56f1260 from qemu
 2020-04-30 21:08:10 -04:00
Alistair Francis dc7cbbe2c1 target/riscv: Remove user version information 
Remove the user version information. This was never used and never
publically exposed in a release of QEMU, so let's just remove it. In
future to manage versions we can extend the extension properties to
specify version.

Backports commit c9a73910c34a2147bcf6a3b5194d27abb19c2e54 from qemu
 2020-04-30 21:06:51 -04:00
Anup Patel 15e558e9cc riscv: Fix Stage2 SV32 page table walk 
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
is required to handle the 34bit intermediate physical address coming
from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2
SV32 level-0 page table will be 16KB in size with total 4096 enteries
where each entry maps 4MB of memory (same as Stage1 SV32 page table).

The get_physical_address() function is broken for Stage2 SV32 level-0
page table because it incorrectly computes output physical address for
Stage2 SV32 level-0 page table entry.

The root cause of the issue is that get_physical_address() uses the
"widened" variable to compute level-0 physical address mapping which
changes level-0 mapping size (instead of 4MB). We should use the
"widened" variable only for computing index of Stage2 SV32 level-0
page table.

Backports commit ee79e7cd47ef47074d7c20c221321c5d31d3683d from qemu
 2020-04-30 20:54:08 -04:00
Alistair Francis 434f9b057f riscv: AND stage-1 and stage-2 protection flags 
Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.

Backports commit 8f67cd6db7375f9133d900b13b300931fbc2e1d8 from qemu
 2020-04-30 20:53:11 -04:00
Alistair Francis b6e2cf33df riscv: Don't use stage-2 PTE lookup protection flags 
When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.

Backports commit 384728905441279e54fa3d714b11bf1b1bcbfd27 from qemu
 2020-04-30 20:52:06 -04:00
Rajnesh Kanwal cf08d74c26 target/riscv: Fix VS mode interrupts forwarding. 
Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.

Backports commit c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264 from qemu
 2020-04-30 06:21:03 -04:00
Alistair Francis 1001f0ba1f target/riscv: Correctly implement TSR trap 
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu
 2020-04-30 06:19:49 -04:00
Anup Patel d47390ade4 target/riscv: Emulate TIME CSRs for privileged mode 
Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.

For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.

We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.

Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu
 2020-03-22 02:22:17 -04:00
Alistair Francis 6c3338430a target/riscv: Add the MSTATUS_MPV_ISSET helper macro 
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.

Backports commit e44b50b5b2e508fdd24915ab0e44ac49685e1de3 from qemu
 2020-03-22 02:18:02 -04:00
Alistair Francis 835b025692 target/riscv: Add support for the 32-bit MSTATUSH CSR 
Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu
 2020-03-22 02:16:13 -04:00
Alistair Francis 63d5b37ebc target/riscv: Set htval and mtval2 on execptions 
Backports commit 3067553993ae986b76a92df8a978778134ecdc84 from qemu
 2020-03-22 02:13:07 -04:00
Alistair Francis 141c47a286 target/riscv: Raise the new execptions when 2nd stage translation fails 
Backports commit b2ef6ab9fee6948cf016f9e741feecdfb333fcbe from qemu
 2020-03-22 02:08:53 -04:00
Alistair Francis 773757a919 target/riscv: Implement second stage MMU 
Backports commit 36a18664bafcfafa5e997b47458387f6fe53d537 from qemu
 2020-03-22 02:07:49 -04:00
Alistair Francis e350bd6f85 target/riscv: Allow specifying MMU stage 
Backports commit 1448689c7b23690f49a4cce248c6e4ac973d37b8 from qemu
 2020-03-22 01:56:41 -04:00
Alistair Francis 74b8fd51f4 target/riscv: Respect MPRV and SPRV for floating point ops 
mark_fs_dirty() is the only place in translate.c that uses the
virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and
HSTATUS.SPRV when setting the bool as this is used for performing
floating point operations when V=0.

Backports commit ae84dd0ab7eaf7e98cd6ee05b2063cce8ff9bc02 from qemu
 2020-03-22 01:54:06 -04:00
Alistair Francis 270808e22e target/riscv: Mark both sstatus and msstatus_hs as dirty 
Mark both sstatus and vsstatus as dirty (3).

Backports commit 45b4dc8b403aa5473ec015336adf7d14d88e85c5 from qemu
 2020-03-22 01:51:41 -04:00
Alistair Francis 347ad87e98 target/riscv: Disable guest FP support based on virtual status 
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.

Backports commit 29409c1d921d607873268671bf11a088efb5558e from qemu
 2020-03-22 01:49:05 -04:00
Alistair Francis 0d488f3a76 target/riscv: Only set TB flags with FP status if enabled 
Backports commit e28eaed87902c5e852c3ed043b27204e879aa4e2 from qemu
 2020-03-22 01:45:32 -04:00
Alistair Francis 1e17cbc52c target/riscv: Remove the hret instruction 
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.

Backports commit 0736febb2d0e1bb503ca07091c16a16e78480366 from qemu
 2020-03-22 01:44:55 -04:00
Alistair Francis 13a7b74827 target/riscv: Add hfence instructions 
Backports commit 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a from qemu
 2020-03-22 01:43:53 -04:00
Alistair Francis fcc30eac4d target/riscv: Add Hypervisor trap return support 
Backports commit e3fba4bab668a41f7cec6405c5aeb21497bd7c83 from qemu
 2020-03-22 01:41:58 -04:00
Alistair Francis 3e3bdf836b target/riscv: Add hypvervisor trap support 
Backports commit 5eb9e782f523d2898e2dacd86c6e41365dae74b3 from qemu
 2020-03-22 01:40:06 -04:00
Alistair Francis f6b14e146e target/riscv: Generate illegal instruction on WFI when V=1 
Backports commit 9d0d11269671646be7475cc01142e9d3ed8ae59c from qemu
 2020-03-22 01:38:14 -04:00
Alistair Francis 4af0dc9a7e target/ricsv: Flush the TLB on virtulisation mode changes 
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.

Backports commit eccc5a12c2fd1c646c69a1e7de29183b7a559973 from qemu
 2020-03-22 01:37:19 -04:00
Alistair Francis 5adba06c29 target/riscv: Add support for virtual interrupt setting 
Backports commit 3ef10a098b0d3ebb02bf8e1325adc3b77af92f0b from qemu
 2020-03-22 01:36:28 -04:00
Alistair Francis 4e7aaee31a target/riscv: Extend the SIP CSR to support virtulisation 
Backports commit a2e9f57d06279220b1834eca2494e52adae121b8 from qemu
 2020-03-22 01:35:11 -04:00
Alistair Francis 1fd49ac6f0 target/riscv: Extend the MIE CSR to support virtulisation 
Backports commit d0e53ce33ec8f66ffa597c634d50be73264aeadb from qemu
 2020-03-22 01:33:17 -04:00
Alistair Francis 6aabd67ef8 target/riscv: Set VS bits in mideleg for Hyp extension 
Backports commit 713d8363deb3774db14fb88a9fcd99687dcef114 from qemu
 2020-03-22 01:32:12 -04:00
Alistair Francis ebc7b9371f target/riscv: Add virtual register swapping function 
Backports commit 66e594f2800ddc55f908830bf9e8dc4cda1304fe from qemu
 2020-03-22 01:30:22 -04:00
Alistair Francis 042e3df075 target/riscv: Add Hypervisor machine CSRs accesses 
Backports commit 34cfb5f61842d495c6f6fc3eeb4197b5b44fd570 from qemu
 2020-03-22 01:26:47 -04:00
Alistair Francis dd356201a6 target/riscv: Add Hypervisor virtual CSRs accesses 
Backports commit 8747c9eeb2aaec8441d0900b198725ab33af4951 from qemu
 2020-03-22 01:24:42 -04:00
Alistair Francis 221c427fc3 target/riscv: Add Hypervisor CSR access functions 
Backports commit ff2cc1294cd8179d87de299b8e7a16bdb1e69523 from qemu
 2020-03-22 01:22:58 -04:00
Alistair Francis e4e41d3d87 target/riscv: Fix CSR perm checking for HS mode 
Update the CSR permission checking to work correctly when we are in
HS-mode.

Backports commit 0a42f4c4408824dc7cb9ff60c9bdce6dcc0d24a5 from qemu
 2020-03-22 01:19:04 -04:00
Alistair Francis ab7c1570d8 target/riscv: Add the force HS exception mode 
Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit
specifies if an exeption should be taken to HS mode no matter the
current delegation status. This is used when an exeption must be taken
to HS mode, such as when handling interrupts.

Backports commit c7b1bbc80fc2af17395d3986c346fd2307e57829 from qemu
 2020-03-22 01:16:55 -04:00
Alistair Francis 95537388c5 target/riscv: Add the virtulisation mode 
Backports commit ef6bb7b62682badefdcb744831510aaa5971684f from qemu
 2020-03-22 01:15:06 -04:00
Alistair Francis fa04e7ea45 target/riscv: Rename the H irqs to VS irqs 
Backports commit 205377f8940898e4c53d1b44350a3d4934a2da72 from qemu
 2020-03-22 01:09:04 -04:00
Alistair Francis 0198a09698 target/riscv: Add support for the new execption numbers 
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.

Backports commit ab67a1d07a4f6f1b4d577c5c47013273b9804551 from qemu
 2020-03-22 01:07:23 -04:00
Alistair Francis 870603305d target/riscv: Add the Hypervisor CSRs to CPUState 
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.

Backports commit bd023ce33b85d73791b7bc78fd04a8115c60995e from qemu
 2020-03-22 01:05:23 -04:00
Alistair Francis 40afe12008 target/riscv: Add the Hypervisor extension 
Backports commit af1fa0039c799a350bcde07b3d8a71dfde07d11b from qemu
 2020-03-22 01:01:07 -04:00
Alistair Francis 83ac8747a5 target/riscv: Convert MIP CSR to target_ulong 
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.

Backports commit 028616130d5f0abc8a3b96f28963da51a875024b from qemu
 2020-03-22 00:59:47 -04:00
ShihPo Hung 7fffc5208c target/riscv: update mstatus.SD when FS is set dirty 
remove the check becuase SD bit should summarize FS and XS fields
unconditionally.

Backports commit 82f014671cf057de51c4a577c9e2ad637dcec6f9 from qemu
 2020-03-21 12:22:56 -04:00
ShihPo Hung 6bdd94bf26 target/riscv: fsd/fsw doesn't dirty FP state 
Backports commit a59796eb6d59bbd74ce28ddbddb1b83e60674e96 from qemu
 2020-03-21 12:20:52 -04:00
Yiting Wang 1c7f2083da riscv: Set xPIE to 1 after xRET 
When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.

Backports commit a37f21c27d3e2342c2080aafd4cfe7e949612428 from qemu
 2020-03-21 12:18:59 -04:00
Tony Nguyen f75368cd0f
tcg: TCGMemOp is now accelerator independent MemOp 
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Backports commit 14776ab5a12972ea439c7fb2203a4c15a09094b4 from qemu
 2019-11-28 03:01:12 -05:00
Richard Henderson 8767d64b66
target/riscv: Remove redundant declaration pragmas 
These are now generated by decodetree itself.

Backports commit 59a3a1c0c211640e18b058a1b0444154c4eb6f99 from qemu
 2019-11-18 21:22:09 -05:00
Alex Bennée 14b401f0bf
target/riscv: rationalise softfloat includes 
We should avoid including the whole of softfloat headers in cpu.h and
explicitly include it only where we will be calling softfloat
functions. We can use the -types.h and -helpers.h in cpu.h for the few
bits that are global.

Backports commit 135b03cb9defbd080b8834b30e3d45bed00c6137 from qemu
 2019-11-18 21:17:03 -05:00
Joel Sing 14c6ed2cca
RISC-V: Clear load reservations on context switch and SC 
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.

Backports commit c13b169f1a3dd158d6c75727cdc388f95988db39 from qemu
 2019-08-08 17:15:45 -04:00
Palmer Dabbelt 4a3d8417ca
RISC-V: Add support for the Zicsr extension 
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.

Backports commit 591bddea8d874e1500921de0353818e5586618f5 from qemu
 2019-08-08 17:10:34 -04:00
Palmer Dabbelt 5b59f956b3
RISC-V: Add support for the Zifencei extension 
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.

Backports commit 50fba816cd226001bec3e495c39879deb2fa5432 from qemu
 2019-08-08 17:09:09 -04:00
Alistair Francis e006204543
target/riscv: Set privledge spec 1.11.0 as default 
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.

Backports commit e3147506b02edcdd7c14ebb41a10fcc3027dcc5c from qemu
 2019-08-08 17:05:40 -04:00