Commit graph

6333 commits

Author SHA1 Message Date
Aleksandar Markovic 32457b2b37
target/mips: Fix emulation of ST.W in system mode
Order of arguments in helper_ret_stl_mmu() invocations was wrong,
apparently caused by a misplaced multiline copy-and-paste.

Fixes: 6decc57 ("target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host")

Backports commit abd4393d769d9fe2333b2e83e00f911a78475943 from qemu
2019-11-18 23:47:33 -05:00
Aleksandar Markovic 84ec43131c
target/mips: Clean up handling of CP0 register 31
Clean up handling of CP0 register 31.

Backports commit 14d92efd721755cc31df328261d301177980fa89 from qemu
2019-11-18 23:46:33 -05:00
Aleksandar Markovic d012faa9bf
target/mips: Clean up handling of CP0 register 30
Clean up handling of CP0 register 30.

Backports commit 4bcf121ebb009db8d135d8819b8d5837cfd6bb37 from qemu
2019-11-18 23:43:56 -05:00
Aleksandar Markovic 6fae1432ce
target/mips: Clean up handling of CP0 register 29
Clean up handling of CP0 register 29.

Backports commit af4bb6da80d3f6c733055bb4e2a1b99a30e81d24 from qemu
2019-11-18 23:43:11 -05:00
Aleksandar Markovic 7dc128c3ad
target/mips: Clean up handling of CP0 register 28
Clean up handling of CP0 register 28.

Backports commit a30e2f218034f6215757734c8107fd47f5385dfa from qemu
2019-11-18 23:40:48 -05:00
Aleksandar Markovic 9ed9ff06ab
target/mips: Clean up handling of CP0 register 27
Clean up handling of CP0 register 27.

Backports commit 5a10873d7ddd5d84c38c6f0dd69116b93219a7c1 from qemu
2019-11-18 23:38:00 -05:00
Aleksandar Markovic 9fe6520144
target/mips: Clean up handling of CP0 register 26
Clean up handling of CP0 register 26.

Backports commit dbbf08b2892a7cf93e47f84c512953234a452cec from qemu
2019-11-18 23:37:02 -05:00
Aleksandar Markovic 7f23faefa3
target/mips: Clean up handling of CP0 register 25
Clean up handling of CP0 register 25.

Backports commit 1176b328c310dbc71501f370fe128786edc7609c from qemu
2019-11-18 23:36:02 -05:00
Aleksandar Markovic d7b34101a0
target/mips: Clean up handling of CP0 register 24
Clean up handling of CP0 register 24.

Backports commit 8d7b4b6efbab8b5286aa9f5948d3e2ce9f98aea5 from qemu
2019-11-18 23:31:37 -05:00
Aleksandar Markovic 4626d0d314
target/mips: Clean up handling of CP0 register 23
Clean up handling of CP0 register 23.

Backports commit 4cbf4b6d00aa27176f1a19b3c739423875d702fe from qemu
2019-11-18 23:30:52 -05:00
Aleksandar Markovic 6d070f1346
target/mips: Clean up handling of CP0 register 20
Clean up handling of CP0 register 20.

Backports commit 14f92b0b9ca0abe48f9a23a73e8dc413d919eab9 from qemu
2019-11-18 23:22:56 -05:00
Aleksandar Markovic 462d062240
target/mips: Clean up handling of CP0 register 19
Clean up handling of CP0 register 19.

Backports commit be274dc18ee3682bb3a2ba7e5ccd3061b103cbec from qemu
2019-11-18 23:22:07 -05:00
Aleksandar Markovic e126751cdc
target/mips: Clean up handling of CP0 register 18
Clean up handling of CP0 register 18.

Backports commit e8dcfe825a51c5e963813343ec4112f06a0acf68 from qemu
2019-11-18 23:21:19 -05:00
Aleksandar Markovic 0424d7bd24
target/mips: Clean up handling of CP0 register 17
Clean up handling of CP0 register 17.

Backports commit 706ce142056b1304ea21db53b73d128295771a71 from qemu
2019-11-18 23:18:16 -05:00
Aleksandar Markovic 04de1c3a5e
target/mips: Clean up handling of CP0 register 16
Clean up handling of CP0 register 16.

Backports commit 433efb4cca1d942b6849be953ea166b492e9bb59 from qemu
2019-11-18 23:14:41 -05:00
Aleksandar Markovic e54d2617a1
target/mips: Clean up handling of CP0 register 15
Clean up handling of CP0 register 15.

Backports commit 4466cd49e53d3a4418a0f27ea9ff335fd9aed180 from qemu
2019-11-18 23:11:46 -05:00
Aleksandar Markovic 41133450de
target/mips: Clean up handling of CP0 register 14
Clean up handling of CP0 register 14.

Backports commit 35e4b54d90b07736d24d736c50f236231cde929f from qemu
2019-11-18 23:10:19 -05:00
Aleksandar Markovic dc1e7c4467
target/mips: Clean up handling of CP0 register 13
Clean up handling of CP0 register 13.

Backports commit e3c7559d8902fbb9857fb94fc5391f258cc3c4d1 from qemu
2019-11-18 23:08:20 -05:00
Aleksandar Markovic 3f76658fd8
target/mips: Clean up handling of CP0 register 12
Clean up handling of CP0 register 12.

Backports commit 2b0848674b4143bf5b2b6f7de6b8587dd52c31dd from qemu
2019-11-18 23:06:38 -05:00
Aleksandar Markovic 5812937c52
target/mips: Clean up handling of CP0 register 11
Clean up handling of CP0 register 11.

Backports commit f5f3834ff0f7d237fa9d5c67544ae5f5d49eaaf7 from qemu
2019-11-18 23:04:18 -05:00
Aleksandar Markovic 16e817b003
target/mips: Clean up handling of CP0 register 10
Clean up handling of CP0 register 10.

Backports commit 860ffef0477a92f1944f10528887fa5e74e6535d from qemu
2019-11-18 23:03:25 -05:00
Aleksandar Markovic 11d02fc0b7
target/mips: Clean up handling of CP0 register 9
Clean up handling of CP0 register 9.

Backports commit e5a98a7232e10632032be8f896ce0aaf171b6fd5 from qemu
2019-11-18 23:01:54 -05:00
Aleksandar Markovic f4015517ab
target/mips: Clean up handling of CP0 register 8
Clean up handling of CP0 register 8.

Backports commit 67d167d2d83d059932c99c077b402b94339c8cf0 from qemu
2019-11-18 22:59:32 -05:00
Aleksandar Markovic 38f0e31950
target/mips: Clean up handling of CP0 register 7
Clean up handling of CP0 register 7.

Backports commit 143a9875e51a358924154ffa76135ca29415dfb5 from qemu
2019-11-18 22:55:22 -05:00
Aleksandar Markovic 95fa7aae61
target/mips: Clean up handling of CP0 register 6
Clean up handling of CP0 register 6.

Backports commit 9023594b4081585518faf9b144bce62067381990 from qemu
2019-11-18 22:54:26 -05:00
Aleksandar Markovic 49eeba113e
target/mips: Clean up handling of CP0 register 5
Clean up handling of CP0 register 5.

Backports commit a1e76353e389f93e63bf1175c8422e5e7759662e from qemu
2019-11-18 22:51:19 -05:00
Aleksandar Markovic 11ac98331a
target/mips: Clean up handling of CP0 register 4
Clean up handling of CP0 register 4.

Backports commit 020fe379093deb116d72174268335d60133f0e26 from qemu
2019-11-18 22:46:46 -05:00
Aleksandar Markovic d96b3d06c4
target/mips: Clean up handling of CP0 register 3
Clean up handling of CP0 register 3.

Backports commit acd3731632c5737eaeb230d76fd55ce871a33439 from qemu
2019-11-18 22:42:17 -05:00
Aleksandar Markovic 8644845898
target/mips: Clean up handling of CP0 register 2
Clean up handling of CP0 register 2.

Backports commit 6d27d5bd73489a0560a6613e2b5633e221999db9 from qemu
2019-11-18 22:38:46 -05:00
Aleksandar Markovic 9450b71a13
target/mips: Clean up handling of CP0 register 1
Clean up handling of CP0 register 1

Backports commit 30deb4605bf0bb4cc0682216002dfed738bd5700 from qemu
2019-11-18 22:33:29 -05:00
Aleksandar Markovic 47adeabf87
target/mips: Clean up handling of CP0 register 0
Clean up handling of CP0 register 0.

Backports commit 1b142da5f82a8fcdc7783a418592de654d5c6052 from qemu
2019-11-18 22:25:31 -05:00
Marc-André Lureau effccae2d9
configure: remove AUTOCONF_HOST
This is a left-over from commit
c12b6d70e384c769ca372e15ffd19b3e9f563662 ("pixman: drop submodule")

Backports commit fbb04e760f4818a1ba9cfde0a2571a15cd4f49f7 from qemu
2019-11-18 22:19:47 -05:00
Carlo Marcelo Arenas Belón 467617cd8a
configure: remove obsoleted variable
9b9c37c364 ("tcg-sparc: Assume v9 cpu always, i.e. force v8plus in
32-bit mode.", 2012-09-21) removed the need for this variable and
most of the references to it, but this one.

Remove defunct code, no effect or functionality change expected.

Backports commit edd318b7a3c54321ead363ffc1e22ebac5785f1d from qemu
2019-11-18 22:08:27 -05:00
Jing Liu 61be812bfb
x86: Intel AVX512_BF16 feature enabling
Intel CooperLake cpu adds AVX512_BF16 instruction, defining as
CPUID.(EAX=7,ECX=1):EAX[bit 05].

The patch adds a property for setting the subleaf of CPUID leaf 7 in
case that people would like to specify it.

The release spec link as follows,
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Backports commit 80db491da4ce8b199e0e8d1e23943b20aab82f69 from qemu
2019-11-18 22:06:57 -05:00
Peter Maydell 5899803c3c
target/i386: Return 'indefinite integer value' for invalid SSE fp->int conversions
The x86 architecture requires that all conversions from floating
point to integer which raise the 'invalid' exception (infinities of
both signs, NaN, and all values which don't fit in the destination
integer) return what the x86 spec calls the "indefinite integer
value", which is 0x8000_0000 for 32-bits or 0x8000_0000_0000_0000 for
64-bits. The softfloat functions return the more usual behaviour of
positive overflows returning the maximum value that fits in the
destination integer format and negative overflows returning the
minimum value that fits.

Wrap the softfloat functions in x86-specific versions which
detect the 'invalid' condition and return the indefinite integer.

Note that we don't use these wrappers for the 3DNow! pf2id and pf2iw
instructions, which do return the minimum value that fits in
an int32 if the input float is a large negative number.

Fixes: https://bugs.launchpad.net/qemu/+bug/1815423

Backports commit 1e8a98b53867f61da9ca09f411288e2085d323c4 from qemu
2019-11-18 21:48:03 -05:00
tony.nguyen@bt.com b4c2c94602
configure: Define target access alignment in configure
This patch moves the define of target access alignment earlier from
target/foo/cpu.h to configure.

Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now
accelerator independent MemOp"

Backports commit 52bf9771fdfce98e98cea36a17a18915be6f6b7f from qemu
2019-11-18 21:41:35 -05:00
Wanpeng Li c041f5f2cc
target-i386: adds PV_SCHED_YIELD CPUID feature bit
Adds PV_SCHED_YIELD CPUID feature bit.

Backports commit b896c4b50da107bf0d40e6215d4ee20daf64723b from qemu
2019-11-18 21:38:26 -05:00
Aleksandar Markovic 551b3db088
target/mips: Style improvements in translate.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Backports commit 71375b59241a27b75d287b9216e5e82e43d763d8 from qemu
2019-11-18 21:36:30 -05:00
Aleksandar Markovic cf6adb51e0
target/mips: Style improvements in cpu.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Backports commit cf02a1164815ed6682c21070ddc95b88c31ff476 from qemu
2019-11-18 21:25:54 -05:00
Aleksandar Markovic 780b748780
target/mips: Style improvements in cp0_timer.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.

Backports commit 2f0d0196721d207297ce00a6cb39fc52005ccc7a from qemu
2019-11-18 21:24:37 -05:00
Richard Henderson 8767d64b66
target/riscv: Remove redundant declaration pragmas
These are now generated by decodetree itself.

Backports commit 59a3a1c0c211640e18b058a1b0444154c4eb6f99 from qemu
2019-11-18 21:22:09 -05:00
Richard Henderson b33a5bd513
decodetree: Suppress redundant declaration warnings
We can tell that a decodetree input file is "secondary" when it
uses an argument set marked "!extern". This indicates that at
least one of the insn translation functions will have already
been declared by the "primary" input file, but given only the
secondary we cannot tell which.

Avoid redundant declaration warnings by suppressing them with pragmas.

Backports commit c692079597d98337b6f25deff7599afe39b2a468 from qemu
2019-11-18 21:21:30 -05:00
Richard Henderson 6e2358ab60
decodetree: Allow !function with no input bits
Call this form a "parameter", returning a value extracted
from the DisasContext.

Backports commit 94597b6146f30f949f2c454f424082a2b0f55a0e from qemu
2019-11-18 21:21:25 -05:00
Alex Bennée 14b401f0bf
target/riscv: rationalise softfloat includes
We should avoid including the whole of softfloat headers in cpu.h and
explicitly include it only where we will be calling softfloat
functions. We can use the -types.h and -helpers.h in cpu.h for the few
bits that are global.

Backports commit 135b03cb9defbd080b8834b30e3d45bed00c6137 from qemu
2019-11-18 21:17:03 -05:00
Alex Bennée 3afb3723c7
target/mips: rationalise softfloat includes
We should avoid including the whole of softfloat headers in cpu.h and
explicitly include it only where we will be calling softfloat
functions. We can use the -types.h in cpu.h for the few bits that are
global. We also move the restore_snan_bit_mode into internal.h and
include -helpers.h there.

Backports commit 502700d0674919309a19bfd016ea0680c6b7747d from qemu
2019-11-18 21:15:19 -05:00
Alex Bennée 9d83300f3e
fpu: rename softfloat-specialize.h -> .inc.c
This is not a normal header and should only be included in the main
softfloat.c file to bring in the various target specific
specialisations. Indeed as it contains non-inlined C functions it is
not even a legal header. Rename it to match our included C convention.

Backports commit 00f43279a3e5e7ea3a0fa853157863663e838e2e from qemu
2019-11-18 21:12:30 -05:00
Alex Bennée 064f50cdf6
fpu: make softfloat-macros self-contained
The macros use the "flags" type and to be consistent if anyone just
needs the macros we should bring in the header we need. There is an
outstanding TODO to audit the use of "flags" and replace with bool at
which point this include could be dropped.

Backports commit 5937fb63a92d54cc4e5270256e4387c4d3a70091 from qemu
2019-11-18 21:10:39 -05:00
Alex Bennée 5ab2ac8dac
fpu: move inline helpers into a separate header
There are a bunch of users of the inline helpers who do not need
access to the entire softfloat API. Move those inline helpers into a
new header file which can be included without bringing in the rest of
the world.

Backports commit e34c47ea3fb5f324b58db117b3c010a494c8d6ca from qemu
2019-11-18 21:09:02 -05:00
Alex Bennée be878fb0e9
fpu: remove the LIT64 macro
Now the rest of the code has been cleaned up we can remove this.

Backports commit 472038ccf5d69ebcad44d835488a36ee640c219f from qemu
2019-11-18 21:06:55 -05:00
Alex Bennée affde8930a
target/m68k: replace LIT64 with UINT64_C macros
In our quest to eliminate the home rolled LIT64 macro we fixup usage
inside for m68k's many constants.

Backports commit e23263004d5fea809ad0f78c523f498e04ba788f from qemu
2019-11-18 21:05:59 -05:00