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unicorn/qemu/target-arm/helper.c

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import
2015-08-21 07:04:50 +00:00
#include "cpu.h"
#include "internals.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "sysemu/sysemu.h"
#include "qemu/bitops.h"
#include "qemu/crc32c.h"
#include "exec/cpu_ldst.h"
#include "arm_ldst.h"
#ifndef CONFIG_USER_ONLY
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
target_ulong *page_size, uint32_t *fsr);
import
2015-08-21 07:04:50 +00:00
/* Definitions for the PMCCNTR and PMCR registers */
#define PMCRD 0x8
#define PMCRC 0x4
#define PMCRE 0x1
#endif
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
target-arm: Add checks that cpreg raw accesses are handled Add assertion checking when cpreg structures are registered that they either forbid raw-access attempts or at least make an attempt at handling them. Also add an assert in the raw-accessor-of-last-resort, to avoid silently doing a read or write from offset zero, which is actually AArch32 CPU register r0. Backports commit 375421ccaeebae8212eb8f9a36835ad4d9dc60a8 from qemu
2018-02-12 16:01:36 +00:00
assert(ri->fieldoffset);
import
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if (cpreg_field_is_64bit(ri)) {
return CPREG_FIELD64(env, ri);
} else {
return CPREG_FIELD32(env, ri);
}
}
static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
target-arm: Add checks that cpreg raw accesses are handled Add assertion checking when cpreg structures are registered that they either forbid raw-access attempts or at least make an attempt at handling them. Also add an assert in the raw-accessor-of-last-resort, to avoid silently doing a read or write from offset zero, which is actually AArch32 CPU register r0. Backports commit 375421ccaeebae8212eb8f9a36835ad4d9dc60a8 from qemu
2018-02-12 16:01:36 +00:00
assert(ri->fieldoffset);
import
2015-08-21 07:04:50 +00:00
if (cpreg_field_is_64bit(ri)) {
CPREG_FIELD64(env, ri) = value;
} else {
CPREG_FIELD32(env, ri) = value;
}
}
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
{
return (char *)env + ri->fieldoffset;
}
import
2015-08-21 07:04:50 +00:00
static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Raw read of a coprocessor register (as needed for migration, etc). */
if (ri->type & ARM_CP_CONST) {
return ri->resetvalue;
} else if (ri->raw_readfn) {
return ri->raw_readfn(env, ri);
} else if (ri->readfn) {
return ri->readfn(env, ri);
} else {
return raw_read(env, ri);
}
}
static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t v)
{
/* Raw write of a coprocessor register (as needed for migration, etc).
* Note that constant registers are treated as write-ignored; the
* caller should check for success by whether a readback gives the
* value written.
*/
if (ri->type & ARM_CP_CONST) {
return;
} else if (ri->raw_writefn) {
ri->raw_writefn(env, ri, v);
} else if (ri->writefn) {
ri->writefn(env, ri, v);
} else {
raw_write(env, ri, v);
}
}
target-arm: Add checks that cpreg raw accesses are handled Add assertion checking when cpreg structures are registered that they either forbid raw-access attempts or at least make an attempt at handling them. Also add an assert in the raw-accessor-of-last-resort, to avoid silently doing a read or write from offset zero, which is actually AArch32 CPU register r0. Backports commit 375421ccaeebae8212eb8f9a36835ad4d9dc60a8 from qemu
2018-02-12 16:01:36 +00:00
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
{
/* Return true if the regdef would cause an assertion if you called
* read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
* program bug for it not to have the NO_RAW flag).
* NB that returning false here doesn't necessarily mean that calling
* read/write_raw_cp_reg() is safe, because we can't distinguish "has
* read/write access functions which are safe for raw use" from "has
* read/write access functions which have side effects but has forgotten
* to provide raw access functions".
* The tests here line up with the conditions in read/write_raw_cp_reg()
* and assertions in raw_read()/raw_write().
*/
if ((ri->type & ARM_CP_CONST) ||
ri->fieldoffset ||
((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
return false;
}
return true;
}
import
2015-08-21 07:04:50 +00:00
bool write_cpustate_to_list(ARMCPU *cpu)
{
/* Write the coprocessor state from cpu->env to the (index,value) list. */
int i;
bool ok = true;
for (i = 0; i < cpu->cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
const ARMCPRegInfo *ri;
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
if (!ri) {
ok = false;
continue;
}
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
if (ri->type & ARM_CP_NO_RAW) {
import
2015-08-21 07:04:50 +00:00
continue;
}
cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
}
return ok;
}
bool write_list_to_cpustate(ARMCPU *cpu)
{
int i;
bool ok = true;
for (i = 0; i < cpu->cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
uint64_t v = cpu->cpreg_values[i];
const ARMCPRegInfo *ri;
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
if (!ri) {
ok = false;
continue;
}
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
if (ri->type & ARM_CP_NO_RAW) {
import
2015-08-21 07:04:50 +00:00
continue;
}
/* Write value and confirm it reads back as written
* (to catch read-only registers and partially read-only
* registers where the incoming migration value doesn't match)
*/
write_raw_cp_reg(&cpu->env, ri, v);
if (read_raw_cp_reg(&cpu->env, ri) != v) {
ok = false;
}
}
return ok;
}
static void add_cpreg_to_list(gpointer key, gpointer opaque)
{
ARMCPU *cpu = opaque;
uint64_t regidx;
const ARMCPRegInfo *ri;
regidx = *(uint32_t *)key;
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
import
2015-08-21 07:04:50 +00:00
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
/* The value array need not be initialized at this point */
cpu->cpreg_array_len++;
}
}
static void count_cpreg(gpointer key, gpointer opaque)
{
ARMCPU *cpu = opaque;
uint64_t regidx;
const ARMCPRegInfo *ri;
regidx = *(uint32_t *)key;
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
import
2015-08-21 07:04:50 +00:00
cpu->cpreg_array_len++;
}
}
merge upstream/noglib and update some glib related types
2016-12-19 20:32:06 +00:00
static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
import
2015-08-21 07:04:50 +00:00
{
uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
if (aidx > bidx) {
return 1;
}
if (aidx < bidx) {
return -1;
}
return 0;
}
static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
{
GList **plist = udata;
*plist = g_list_prepend(*plist, key);
}
void init_cpreg_list(ARMCPU *cpu)
{
/* Initialise the cpreg_tuples[] array based on the cp_regs hash.
* Note that we require cpreg_tuples[] to be sorted by key ID.
*/
GList *keys = NULL;
int arraylen;
g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
keys = g_list_sort(keys, cpreg_key_compare);
cpu->cpreg_array_len = 0;
g_list_foreach(keys, count_cpreg, cpu);
arraylen = cpu->cpreg_array_len;
cpu->cpreg_indexes = g_new(uint64_t, arraylen);
cpu->cpreg_values = g_new(uint64_t, arraylen);
cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
cpu->cpreg_array_len = 0;
g_list_foreach(keys, add_cpreg_to_list, cpu);
assert(cpu->cpreg_array_len == arraylen);
g_list_free(keys);
}
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
raw_write(env, ri, value);
tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
}
static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (raw_read(env, ri) != value) {
/* Unlike real hardware the qemu TLB uses virtual addresses,
* not modified virtual addresses, so this causes a TLB flush.
*/
tlb_flush(CPU(cpu), 1);
raw_write(env, ri, value);
}
}
static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
&& !extended_addresses_enabled(env)) {
/* For VMSA (when not using the LPAE long descriptor page table
* format) this register includes the ASID, so do a TLB flush.
* For PMSA it is purely a process ID and no action is needed.
*/
tlb_flush(CPU(cpu), 1);
}
raw_write(env, ri, value);
}
static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate all (TLBIALL) */
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
}
static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (TLBIASID) */
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), value == 0);
}
static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
/* IS variants of TLB operations must affect all cores */
static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm: disable deadcode introduced by PR #643
2016-09-29 04:33:16 +00:00
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, 1);
import
2015-08-21 07:04:50 +00:00
}
static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm: disable deadcode introduced by PR #643
2016-09-29 04:33:16 +00:00
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, value == 0);
import
2015-08-21 07:04:50 +00:00
}
static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm: disable deadcode introduced by PR #643
2016-09-29 04:33:16 +00:00
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, value & TARGET_PAGE_MASK);
import
2015-08-21 07:04:50 +00:00
}
static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm: disable deadcode introduced by PR #643
2016-09-29 04:33:16 +00:00
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, value & TARGET_PAGE_MASK);
import
2015-08-21 07:04:50 +00:00
}
static const ARMCPRegInfo cp_reginfo[] = {
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
/* Define the secure and non-secure FCSE identifier CP registers
* separately because there is no secure bank in V8 (no _EL3). This allows
* the secure register to be properly reset and migrated. There is also no
* v8 EL1 version of the register so the non-secure instance stands alone.
*/
{ "FCSEIDR(NS)", 15,13,0, 0,0,0, 0,0,
PL1_RW, ARM_CP_SECSTATE_NS, NULL, 0,
offsetof(CPUARMState, cp15.fcseidr_ns), {0, 0},
NULL, NULL, fcse_write, NULL, raw_write, },
{ "FCSEIDR(S)", 15,13,0, 0,0,0, 0,0,
PL1_RW, ARM_CP_SECSTATE_S, NULL, 0,
offsetof(CPUARMState, cp15.fcseidr_s), {0, 0},
NULL, NULL, fcse_write, NULL, raw_write, },
/* Define the secure and non-secure context identifier CP registers
* separately because there is no secure bank in V8 (no _EL3). This allows
* the secure register to be properly reset and migrated. In the
* non-secure case, the 32-bit register will have reset and migration
* disabled during registration as it is handled by the 64-bit instance.
*/
{ "CONTEXTIDR_EL1", 0,13,0, 3,0,1, ARM_CP_STATE_BOTH,
0, PL1_RW, ARM_CP_SECSTATE_NS, NULL, 0, offsetof(CPUARMState, cp15.contextidr_el[1]), {0, 0},
NULL, NULL, contextidr_write, NULL, raw_write, NULL, },
{ "CONTEXTIDR(S)", 15,13,0, 0,0,1, ARM_CP_STATE_AA32,0,
PL1_RW, ARM_CP_SECSTATE_S, NULL, 0,
offsetof(CPUARMState, cp15.contextidr_s), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, contextidr_write, NULL, raw_write, NULL, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo not_v8_cp_reginfo[] = {
/* NB: Some of these registers exist in v8 but with more precise
* definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
*/
/* MMU Domain access control / MPU write buffer control */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DACR", 15,3,CP_ANY, 0,CP_ANY,CP_ANY, 0,
target-arm: make DACR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Backports commit 0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0 from qemu
2018-02-12 14:01:14 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, dacr_write, NULL, raw_write, NULL, },
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
/* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
* For v6 and v5, these mappings are overly broad.
import
2015-08-21 07:04:50 +00:00
*/
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
{ "TLB_LOCKDOWN", 15,10,0, 0,CP_ANY,CP_ANY, 0,
ARM_CP_NOP, PL1_RW, },
{ "TLB_LOCKDOWN", 15,10,1, 0,CP_ANY,CP_ANY, 0,
ARM_CP_NOP, PL1_RW, },
{ "TLB_LOCKDOWN", 15,10,4, 0,CP_ANY,CP_ANY, 0,
ARM_CP_NOP, PL1_RW, },
{ "TLB_LOCKDOWN", 15,10,8, 0,CP_ANY,CP_ANY, 0,
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
ARM_CP_NOP, PL1_RW, },
import
2015-08-21 07:04:50 +00:00
/* Cache maintenance ops; some of this space may be overridden later. */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CACHEMAINT", 15,7,CP_ANY, 0,0,CP_ANY, 0,
ARM_CP_NOP | ARM_CP_OVERRIDE, PL1_W, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
/* Not all pre-v6 cores implemented this WFI, so this is slightly
* over-broad.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "WFI_v5", 15,7,8, 0,0,2, 0,
ARM_CP_WFI, PL1_W, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
* is UNPREDICTABLE; we choose to NOP as most implementations do).
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "WFI_v6", 15,7,0, 0,0,4, 0,
ARM_CP_WFI, PL1_W, },
import
2015-08-21 07:04:50 +00:00
/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
* OMAPCP will override this space.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DLOCKDOWN", 15,9,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_data), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ILOCKDOWN", 15,9,0, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_insn), },
import
2015-08-21 07:04:50 +00:00
/* v6 doesn't have the cache ID registers but Linux reads them anyway */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DUMMY", 15,0,0, 0,1,CP_ANY, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_NO_RAW, PL1_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
* implementing it as RAZ means the "debug architecture version" bits
* will read as a reserved value, which should cause Linux to not try
* to use the debug hardware.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGDIDR", 14,0,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* MMU TLB control. Note that the wildcarding means we cover not just
* the unified TLB ops but also the dside/iside/inner-shareable variants.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TLBIALL", 15,8,CP_ANY, 0,CP_ANY,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_write, },
{ "TLBIMVA", 15,8,CP_ANY, 0,CP_ANY,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_write, },
{ "TLBIASID", 15,8,CP_ANY, 0,CP_ANY,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiasid_write, },
{ "TLBIMVAA", 15,8,CP_ANY, 0,CP_ANY,3, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimvaa_write, },
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
{ "PRRR", 15,10,2, 0,0,0, 0, ARM_CP_NOP,
PL1_RW },
{ "NMRR", 15,10,2, 0,0,1, 0, ARM_CP_NOP,
PL1_RW },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
uint32_t mask = 0;
/* In ARMv8 most bits of CPACR_EL1 are RES0. */
if (!arm_feature(env, ARM_FEATURE_V8)) {
/* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/
if (arm_feature(env, ARM_FEATURE_VFP)) {
/* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
if (!arm_feature(env, ARM_FEATURE_NEON)) {
/* ASEDIS [31] bit is RAO/WI */
value |= (1 << 31);
}
/* VFPv3 and upwards with NEON implement 32 double precision
* registers (D0-D31).
*/
if (!arm_feature(env, ARM_FEATURE_NEON) ||
!arm_feature(env, ARM_FEATURE_VFP3)) {
/* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
value |= (1 << 30);
}
}
value &= mask;
}
target-arm: rename c1_coproc to cpacr_el1 Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Backports commit 7ebd5f2e03a00889619bb97e83062d27066d4a26 from qemu
2018-02-13 01:44:07 +00:00
env->cp15.cpacr_el1 = value;
import
2015-08-21 07:04:50 +00:00
}
target-arm: Add AArch64 CPTR registers Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Backports commit c6f191642a4027909813b4e6e288411f8371e951 from qemu
2018-02-13 03:53:01 +00:00
static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (arm_feature(env, ARM_FEATURE_V8)) {
/* Check if CPACR accesses are to be trapped to EL2 */
if (arm_current_el(env) == 1 &&
(env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
return CP_ACCESS_TRAP_EL2;
/* Check if CPACR accesses are to be trapped to EL3 */
} else if (arm_current_el(env) < 3 &&
(env->cp15.cptr_el[3] & CPTR_TCPAC)) {
return CP_ACCESS_TRAP_EL3;
}
}
return CP_ACCESS_OK;
}
static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Check if CPTR accesses are set to trap to EL3 */
if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
}
import
2015-08-21 07:04:50 +00:00
static const ARMCPRegInfo v6_cp_reginfo[] = {
/* prefetch by MVA in v6, NOP in v7 */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MVA_prefetch", 15,7,13, 0,0,1, 0,
ARM_CP_NOP, PL1_W, },
{ "ISB", 15,7,5, 0,0,4, 0,
ARM_CP_NOP, PL0_W, },
{ "DSB", 15,7,10, 0,0,4, 0,
ARM_CP_NOP, PL0_W, },
{ "DMB", 15,7,10, 0,0,5, 0,
ARM_CP_NOP, PL0_W, },
{ "IFAR", 15,6,0, 0,0,2, 0,
target-arm: make IFAR/DFAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Backports commit b848ce2b9cbd38da3f2530fd93dba76dba0621c0 from qemu
2018-02-12 14:17:49 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) } },
import
2015-08-21 07:04:50 +00:00
/* Watchpoint Fault Address Register : should actually only be present
* for 1136, 1176, 11MPCore.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "WFAR", 15,6,0, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
target-arm: Add AArch64 CPTR registers Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Backports commit c6f191642a4027909813b4e6e288411f8371e951 from qemu
2018-02-13 03:53:01 +00:00
{ "CPACR", 0,1,0, 3,0,2, ARM_CP_STATE_BOTH,
target-arm: rename c1_coproc to cpacr_el1 Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Backports commit 7ebd5f2e03a00889619bb97e83062d27066d4a26 from qemu
2018-02-13 01:44:07 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cpacr_el1), {0, 0},
target-arm: Add AArch64 CPTR registers Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Backports commit c6f191642a4027909813b4e6e288411f8371e951 from qemu
2018-02-13 03:53:01 +00:00
cpacr_access, NULL, cpacr_write },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Performance monitor registers user accessibility is controlled
* by PMUSERENR.
*/
if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
#ifndef CONFIG_USER_ONLY
static inline bool arm_ccnt_enabled(CPUARMState *env)
{
/* This does not support checking PMCCFILTR_EL0 register */
if (!(env->cp15.c9_pmcr & PMCRE)) {
return false;
}
return true;
}
void pmccntr_sync(CPUARMState *env)
{
uint64_t temp_ticks;
temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
get_ticks_per_sec(), 1000000);
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
temp_ticks /= 64;
}
if (arm_ccnt_enabled(env)) {
env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
}
}
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
pmccntr_sync(env);
if (value & PMCRC) {
/* The counter has been reset */
env->cp15.c15_ccnt = 0;
}
/* only the DP, X, D and E bits are writable */
env->cp15.c9_pmcr &= ~0x39;
env->cp15.c9_pmcr |= (value & 0x39);
pmccntr_sync(env);
}
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
uint64_t total_ticks;
if (!arm_ccnt_enabled(env)) {
/* Counter is disabled, do not change value */
return env->cp15.c15_ccnt;
}
total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
get_ticks_per_sec(), 1000000);
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
total_ticks /= 64;
}
return total_ticks - env->cp15.c15_ccnt;
}
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
uint64_t total_ticks;
if (!arm_ccnt_enabled(env)) {
/* Counter is disabled, set the absolute value */
env->cp15.c15_ccnt = value;
return;
}
total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
get_ticks_per_sec(), 1000000);
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
total_ticks /= 64;
}
env->cp15.c15_ccnt = total_ticks - value;
}
static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
uint64_t cur_val = pmccntr_read(env, NULL);
pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
}
#else /* CONFIG_USER_ONLY */
void pmccntr_sync(CPUARMState *env)
{
}
#endif
static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
pmccntr_sync(env);
env->cp15.pmccfiltr_el0 = value & 0x7E000000;
pmccntr_sync(env);
}
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
value &= (1 << 31);
env->cp15.c9_pmcnten |= value;
}
static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
value &= (1 << 31);
env->cp15.c9_pmcnten &= ~value;
}
static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c9_pmovsr &= ~value;
}
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c9_pmxevtyper = value & 0xff;
}
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c9_pmuserenr = value & 1;
}
static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* We have no event counters so only the C bit can be changed */
value &= (1 << 31);
env->cp15.c9_pminten |= value;
}
static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
value &= (1 << 31);
env->cp15.c9_pminten &= ~value;
}
static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Note that even though the AArch64 view of this register has bits
* [10:0] all RES0 we can only mask the bottom 5, to comply with the
* architectural requirements for bits which are RES0 only in some
* contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
* requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
*/
raw_write(env, ri, value & ~0x1FULL);
}
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
/* We only mask off bits that are RES0 both for AArch64 and AArch32.
* For bits that vary between AArch32/64, code needs to check the
* current execution mode before directly using the feature bit.
*/
uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
if (!arm_feature(env, ARM_FEATURE_EL2)) {
valid_mask &= ~SCR_HCE;
/* On ARMv7, SMD (or SCD as it is called in v7) is only
* supported if EL2 exists. The bit is UNK/SBZP when
* EL2 is unavailable. In QEMU ARMv7, we force it to always zero
* when EL2 is unavailable.
Allow ARMv8 SCR.SMD updates Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8 regardless of whether virtualization (EL2) is enabled or not. Backports commit 4eb276408363aef5435a72a8e818f24220b5edd0 from qemu
2018-02-13 01:48:13 +00:00
* On ARMv8, this bit is always available.
import
2015-08-21 07:04:50 +00:00
*/
Allow ARMv8 SCR.SMD updates Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8 regardless of whether virtualization (EL2) is enabled or not. Backports commit 4eb276408363aef5435a72a8e818f24220b5edd0 from qemu
2018-02-13 01:48:13 +00:00
if (arm_feature(env, ARM_FEATURE_V7) &&
!arm_feature(env, ARM_FEATURE_V8)) {
import
2015-08-21 07:04:50 +00:00
valid_mask &= ~SCR_SMD;
}
}
/* Clear all-context RES0 bits. */
value &= valid_mask;
raw_write(env, ri, value);
}
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
target-arm: make CSSELR banked Rename CSSELR (cache size selection register) and add secure instance (AArch32). Backports commit b85a1fd61c4d72c7928cd9b70f9f59fb2895936d from qemu
2018-02-12 00:34:40 +00:00
/* Acquire the CSSELR index from the bank corresponding to the CCSIDR
* bank
*/
uint32_t index = A32_BANKED_REG_GET(env, csselr,
ri->secure & ARM_CP_SECSTATE_S);
return cpu->ccsidr[index];
import
2015-08-21 07:04:50 +00:00
}
static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
raw_write(env, ri, value & 0xf);
}
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
CPUState *cs = ENV_GET_CPU(env);
uint64_t ret = 0;
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
ret |= CPSR_I;
}
if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
ret |= CPSR_F;
}
/* External aborts are not possible in QEMU so A bit is always clear */
return ret;
}
static const ARMCPRegInfo v7_cp_reginfo[] = {
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "NOP", 15,7,0, 0,0,4, 0,
ARM_CP_NOP, PL1_W, },
import
2015-08-21 07:04:50 +00:00
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
* follow (although we don't actually implement any counters)
*
* Performance registers fall into three categories:
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
* (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
* (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
* For the cases controlled by PMUSERENR we must set .access to PL0_RW
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PMCNTENSET", 15,9,12, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL0_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcnten), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmcntenset_write, NULL, raw_write },
{ "PMCNTENSET_EL0", 0,9,12, 3,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmcnten), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmcntenset_write, NULL, raw_write },
{ "PMCNTENCLR", 15,9,12, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL0_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcnten), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmcntenclr_write, },
{ "PMCNTENCLR_EL0", 0,9,12, 3,3,2, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmcnten), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmcntenclr_write },
{ "PMOVSR", 15,9,12, 0,0,3, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmovsr_write, NULL, raw_write },
import
2015-08-21 07:04:50 +00:00
/* Unimplemented so WI. */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PMSWINC", 15,9,12, 0,0,4, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, },
import
2015-08-21 07:04:50 +00:00
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
* We choose to RAZ/WI.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PMSELR", 15,9,12, 0,0,5, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access },
import
2015-08-21 07:04:50 +00:00
#ifndef CONFIG_USER_ONLY
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PMCCNTR", 15,9,13, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL0_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, pmccntr_read, pmccntr_write32, },
{ "PMCCNTR_EL0", 0,9,13, 3,3,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL0_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, pmccntr_read, pmccntr_write, },
import
2015-08-21 07:04:50 +00:00
#endif
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PMCCFILTR_EL0", 0,14,15, 3,3,7, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmccfiltr_el0), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmccfiltr_write, },
{ "PMXEVTYPER", 15,9,13, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmxevtyper), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL, pmxevtyper_write, NULL, raw_write },
import
2015-08-21 07:04:50 +00:00
/* Unimplemented, RAZ/WI. */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PMXEVCNTR", 15,9,13, 0,0,2, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access },
{ "PMUSERENR", 15,9,14, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_R | PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmuserenr), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, pmuserenr_write, NULL, raw_write },
{ "PMINTENSET", 15,9,14, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, pmintenset_write, NULL, raw_write },
{ "PMINTENCLR", 15,9,14, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, pmintenclr_write, },
{ "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, ccsidr_read, },
{ "CSSELR", 0,0,0, 3,2,0, ARM_CP_STATE_BOTH,
target-arm: make CSSELR banked Rename CSSELR (cache size selection register) and add secure instance (AArch32). Backports commit b85a1fd61c4d72c7928cd9b70f9f59fb2895936d from qemu
2018-02-12 00:34:40 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, csselr_write, },
import
2015-08-21 07:04:50 +00:00
/* Auxiliary ID register: this actually has an IMPDEF value but for now
* just RAZ for all cores:
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AIDR", 0,0,0, 3,1,7, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* Auxiliary fault status registers: these also are IMPDEF, and we
* choose to RAZ/WI for all cores.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AFSR0_EL1", 0,5,1, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AFSR1_EL1", 0,5,1, 3,0,1, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* MAIR can just read-as-written because we don't implement caches
* and so don't need to care about memory attributes.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MAIR_EL1", 0,10,2, 3,0,0, ARM_CP_STATE_AA64,
target-arm: make MAIR0/1 banked Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Backports commit be693c87e440e671ed913784554384349ce8331d from qemu
2018-02-12 15:02:48 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[1]), },
import
2015-08-21 07:04:50 +00:00
/* For non-long-descriptor page tables these are PRRR and NMRR;
* regardless they still act as reads-as-written for QEMU.
*/
target-arm: make MAIR0/1 banked Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Backports commit be693c87e440e671ed913784554384349ce8331d from qemu
2018-02-12 15:02:48 +00:00
/* MAIR0/1 are defined separately from their 64-bit counterpart which
* allows them to assign the correct fieldoffset based on the endianness
* handled in the field definitions.
*/
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
{ "MAIR0", 15,10,2, 0,0,0, ARM_CP_STATE_AA32, 0,
PL1_RW, 0, NULL, 0, 0,
target-arm: make MAIR0/1 banked Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Backports commit be693c87e440e671ed913784554384349ce8331d from qemu
2018-02-12 15:02:48 +00:00
{ offsetof(CPUARMState, cp15.mair0_s), offsetof(CPUARMState, cp15.mair0_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
{ "MAIR1", 15,10,2, 0,0,1, ARM_CP_STATE_AA32, 0,
PL1_RW, 0, NULL, 0, 0,
target-arm: make MAIR0/1 banked Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Backports commit be693c87e440e671ed913784554384349ce8331d from qemu
2018-02-12 15:02:48 +00:00
{ offsetof(CPUARMState, cp15.mair1_s), offsetof(CPUARMState, cp15.mair1_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
{ "ISR_EL1", 0,12,1, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, isr_read },
import
2015-08-21 07:04:50 +00:00
/* 32 bit ITLB invalidates */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ITLBIALL", 15,8,5, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_write },
{ "ITLBIMVA", 15,8,5, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_write },
{ "ITLBIASID", 15,8,5, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiasid_write },
import
2015-08-21 07:04:50 +00:00
/* 32 bit DTLB invalidates */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DTLBIALL", 15,8,6, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_write },
{ "DTLBIMVA", 15,8,6, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_write },
{ "DTLBIASID", 15,8,6, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiasid_write },
import
2015-08-21 07:04:50 +00:00
/* 32 bit TLB invalidates */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TLBIALL", 15,8,7, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_write },
{ "TLBIMVA", 15,8,7, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_write },
{ "TLBIASID", 15,8,7, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiasid_write },
{ "TLBIMVAA", 15,8,7, 0,0,3, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimvaa_write },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo v7mp_cp_reginfo[] = {
/* 32 bit TLB invalidates, Inner Shareable */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TLBIALLIS", 15,8,3, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_is_write },
{ "TLBIMVAIS", 15,8,3, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_is_write },
{ "TLBIASIDIS", 15,8,3, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiasid_is_write },
{ "TLBIMVAAIS", 15,8,3, 0,0,3, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimvaa_is_write },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
value &= 1;
env->teecr = value;
}
static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (arm_current_el(env) == 0 && (env->teecr & 1)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TEECR", 14,0,0, 0,6,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, teecr), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, teecr_write },
{ "TEEHBR", 14,1,0, 0,6,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, teehbr), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
teehbr_access, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo v6k_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TPIDR_EL0", 0,13,0, 3,3,2, ARM_CP_STATE_AA64,
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[0]), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TPIDRURW", 15,13,0, 0,0,2, 0,
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
0, PL0_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.tpidrurw_s), offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
{ "TPIDRRO_EL0", 0,13,0, 3,3,3, ARM_CP_STATE_AA64,
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
0, PL0_R|PL1_W, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidrro_el[0]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TPIDRURO", 15,13,0, 0,0,3, 0,
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
0, PL0_R|PL1_W, 0, NULL, 0, 0,
{offsetoflow32(CPUARMState, cp15.tpidruro_s), offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
{ "TPIDR_EL1", 0,13,0, 3,0,4, ARM_CP_STATE_AA64,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[1]) },
{ "TPIDRPRW", 15,13,0, 0,0,4, 0,0,
PL1_RW, 0, NULL, 0,0,
{ offsetoflow32(CPUARMState, cp15.tpidrprw_s), offsetoflow32(CPUARMState, cp15.tpidrprw_ns)} },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
#ifndef CONFIG_USER_ONLY
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
{
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
import
2015-08-21 07:04:50 +00:00
/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
if (cur_el == 0 &&
import
2015-08-21 07:04:50 +00:00
!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
return CP_ACCESS_TRAP;
}
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
if (arm_feature(env, ARM_FEATURE_EL2) &&
timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
!extract32(env->cp15.cnthctl_el2, 0, 1)) {
return CP_ACCESS_TRAP_EL2;
}
import
2015-08-21 07:04:50 +00:00
return CP_ACCESS_OK;
}
static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
{
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
import
2015-08-21 07:04:50 +00:00
/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
* EL0[PV]TEN is zero.
*/
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
if (cur_el == 0 &&
import
2015-08-21 07:04:50 +00:00
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
return CP_ACCESS_TRAP;
}
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
if (arm_feature(env, ARM_FEATURE_EL2) &&
timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
!extract32(env->cp15.cnthctl_el2, 1, 1)) {
return CP_ACCESS_TRAP_EL2;
}
import
2015-08-21 07:04:50 +00:00
return CP_ACCESS_OK;
}
static CPAccessResult gt_pct_access(CPUARMState *env,
const ARMCPRegInfo *ri)
{
return gt_counter_access(env, GTIMER_PHYS);
}
static CPAccessResult gt_vct_access(CPUARMState *env,
const ARMCPRegInfo *ri)
{
return gt_counter_access(env, GTIMER_VIRT);
}
static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_timer_access(env, GTIMER_PHYS);
}
static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_timer_access(env, GTIMER_VIRT);
}
static uint64_t gt_get_countervalue(CPUARMState *env)
{
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
}
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
{
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
if (gt->ctl & 1) {
/* Timer enabled: calculate and set current ISTATUS, irq, and
* reset timer to when ISTATUS next has to change
*/
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
uint64_t offset = timeridx == GTIMER_VIRT ?
cpu->env.cp15.cntvoff_el2 : 0;
import
2015-08-21 07:04:50 +00:00
uint64_t count = gt_get_countervalue(&cpu->env);
/* Note that this must be unsigned 64 bit arithmetic: */
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
int istatus = count - offset >= gt->cval;
import
2015-08-21 07:04:50 +00:00
uint64_t nexttick;
gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
//qemu_set_irq(cpu->gt_timer_outputs[timeridx],
// (istatus && !(gt->ctl & 2)));
if (istatus) {
/* Next transition is when count rolls back over to zero */
nexttick = UINT64_MAX;
} else {
/* Next transition is when we hit cval */
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
nexttick = gt->cval + offset;
import
2015-08-21 07:04:50 +00:00
}
/* Note that the desired next expiry time might be beyond the
* signed-64-bit range of a QEMUTimer -- in this case we just
* set the timer for as far in the future as possible. When the
* timer expires we will reset the timer for any remaining period.
*/
if (nexttick > INT64_MAX / GTIMER_SCALE) {
nexttick = INT64_MAX / GTIMER_SCALE;
}
//timer_mod(cpu->gt_timer[timeridx], nexttick);
} else {
/* Timer disabled: ISTATUS and timer output always clear */
gt->ctl &= ~4;
//qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
//timer_del(cpu->gt_timer[timeridx]);
}
}
target-arm: Rename and move gt_cnt_reset Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Backports commit d57b9ee84f6b2786f025712609edb259d0de086d from qemu
2018-02-15 01:01:45 +00:00
static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
import
2015-08-21 07:04:50 +00:00
{
}
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_get_countervalue(env);
}
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
}
import
2015-08-21 07:04:50 +00:00
static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int timeridx = ri->opc1 & 1;
env->cp15.c14_timer[timeridx].cval = value;
//gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
int timeridx = ri->crm & 1;
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
import
2015-08-21 07:04:50 +00:00
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
(gt_get_countervalue(env) - offset));
import
2015-08-21 07:04:50 +00:00
}
static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int timeridx = ri->crm & 1;
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
import
2015-08-21 07:04:50 +00:00
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
target-arm: Remove unneeded '+' Backports commit 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502 from qemu
2018-02-13 02:37:59 +00:00
sextract64(value, 0, 32);
import
2015-08-21 07:04:50 +00:00
gt_recalc_timer(arm_env_get_cpu(env), timeridx);
}
static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int timeridx = ri->crm & 1;
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
if ((oldval ^ value) & 1) {
/* Enable toggled */
gt_recalc_timer(cpu, timeridx);
} else if ((oldval ^ value) & 2) {
/* IMASK toggled: don't need to recalculate,
* just set the interrupt line based on ISTATUS
*/
//qemu_set_irq(cpu->gt_timer_outputs[timeridx],
// (oldval & 4) && !(value & 2));
}
}
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
raw_write(env, ri, value);
gt_recalc_timer(cpu, GTIMER_VIRT);
}
import
2015-08-21 07:04:50 +00:00
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
gt_recalc_timer(cpu, GTIMER_PHYS);
}
void arm_gt_vtimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
gt_recalc_timer(cpu, GTIMER_VIRT);
}
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* Note that CNTFRQ is purely reads-as-written for the benefit
* of software; writing it doesn't actually change the timer frequency.
* Our reset value matches the fixed frequency we implement the timer at.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTFRQ", 15,14,0, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_cntfrq), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
gt_cntfrq_access, NULL, NULL, NULL, NULL, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTFRQ_EL0", 0,14,0, 3,3,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW | PL0_R, 0, NULL, (1000 * 1000 * 1000) / GTIMER_SCALE, offsetof(CPUARMState, cp15.c14_cntfrq), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_cntfrq_access, },
import
2015-08-21 07:04:50 +00:00
/* overall control: mostly access permissions */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTKCTL", 0,14,1, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_cntkctl), },
import
2015-08-21 07:04:50 +00:00
/* per-timer control */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTP_CTL", 15,14,2, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
gt_ptimer_access, NULL, gt_ctl_write, NULL, raw_write, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTP_CTL_EL0", 0,14,2, 3,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_ptimer_access, NULL,gt_ctl_write, NULL,raw_write, },
{ "CNTV_CTL", 15,14,3, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
gt_vtimer_access, NULL, gt_ctl_write, NULL, raw_write, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTV_CTL_EL0", 0,14,3, 3,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_vtimer_access, NULL,gt_ctl_write, NULL,raw_write, },
import
2015-08-21 07:04:50 +00:00
/* TimerValue views: a 32 bit downcounting view of the underlying state */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTP_TVAL", 15,14,2, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_ptimer_access, gt_tval_read, gt_tval_write, },
{ "CNTP_TVAL_EL0", 0,14,2, 3,3,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
target-arm: Rename and move gt_cnt_reset Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Backports commit d57b9ee84f6b2786f025712609edb259d0de086d from qemu
2018-02-15 01:01:45 +00:00
gt_ptimer_access, gt_tval_read, gt_tval_write, NULL, NULL, gt_timer_reset },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTV_TVAL", 15,14,3, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_vtimer_access, gt_tval_read, gt_tval_write, },
{ "CNTV_TVAL_EL0", 0,14,3, 3,3,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
target-arm: Rename and move gt_cnt_reset Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Backports commit d57b9ee84f6b2786f025712609edb259d0de086d from qemu
2018-02-15 01:01:45 +00:00
gt_vtimer_access, gt_tval_read, gt_tval_write, NULL, NULL, gt_timer_reset },
import
2015-08-21 07:04:50 +00:00
/* The counter itself */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTPCT", 15,0,14, 0,0, 0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, PL0_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_pct_access, gt_cnt_read,NULL, NULL,NULL, arm_cp_reset_ignore, },
{ "CNTPCT_EL0", 0,14,0, 3,3,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW | ARM_CP_IO, PL0_R, 0, NULL, 0, 0, {0, 0},
target-arm: Rename and move gt_cnt_reset Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Backports commit d57b9ee84f6b2786f025712609edb259d0de086d from qemu
2018-02-15 01:01:45 +00:00
gt_pct_access, gt_cnt_read, NULL, NULL, NULL, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTVCT", 15,0,14, 0,1,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, PL0_R, 0, NULL, 0, 0, {0, 0},
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
gt_vct_access, gt_virt_cnt_read, NULL, NULL, NULL, arm_cp_reset_ignore, },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTVCT_EL0", 0,14,0, 3,3,2, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW | ARM_CP_IO, PL0_R, 0, NULL, 0, 0, {0, 0},
target-arm: Rename and move gt_cnt_reset Rename gt_cnt_reset to gt_timer_reset as the function really resets the timers and not the counters. Move the registration from counter regs to timer regs. Backports commit d57b9ee84f6b2786f025712609edb259d0de086d from qemu
2018-02-15 01:01:45 +00:00
gt_vct_access, gt_virt_cnt_read, NULL, NULL, NULL, NULL },
import
2015-08-21 07:04:50 +00:00
/* Comparison value, indicating when the timer goes off */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTP_CVAL", 15, 0,14, 0,2, 0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTP_CVAL_EL0", 0,14,2, 3,3,2, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
target-arm: Correct accessfn for CNTP_{CT}VAL_EL0 Backports commit 12cde08aaf571de65d3fbbdf93c83f0a4321267f from qemu
2018-02-13 02:35:41 +00:00
gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTV_CVAL", 15, 0,14, 0,3,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CNTV_CVAL_EL0", 0,14,3, 3,3,2, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
#else
/* In user-mode none of the generic timer registers are accessible,
* and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
* so instead just don't register any of them.
*/
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
REGINFO_SENTINEL
};
#endif
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
if (arm_feature(env, ARM_FEATURE_LPAE)) {
raw_write(env, ri, value);
} else if (arm_feature(env, ARM_FEATURE_V7)) {
raw_write(env, ri, value & 0xfffff6ff);
} else {
raw_write(env, ri, value & 0xfffff1ff);
}
}
#ifndef CONFIG_USER_ONLY
/* get_phys_addr() isn't present for user-mode-only targets */
static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (ri->opc2 & 4) {
/* Other states are only available with TrustZone; in
* a non-TZ implementation these registers don't exist
* at all, which is an Uncategorized trap. This underdecoding
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
* is safe because the reginfo is NO_RAW.
import
2015-08-21 07:04:50 +00:00
*/
return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return CP_ACCESS_OK;
}
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
int access_type, ARMMMUIdx mmu_idx)
import
2015-08-21 07:04:50 +00:00
{
hwaddr phys_addr;
target_ulong page_size;
int prot;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
uint32_t fsr;
bool ret;
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
uint64_t par64;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
MemTxAttrs attrs = {0};
import
2015-08-21 07:04:50 +00:00
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
ret = get_phys_addr(env, value, access_type, mmu_idx,
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
&phys_addr, &attrs, &prot, &page_size, &fsr);
import
2015-08-21 07:04:50 +00:00
if (extended_addresses_enabled(env)) {
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
/* fsr is a DFSR/IFSR value for the long descriptor
import
2015-08-21 07:04:50 +00:00
* translation table format, but with WnR always clear.
* Convert it to a 64-bit PAR.
*/
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
par64 = (1 << 11); /* LPAE bit always set */
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
if (!ret) {
import
2015-08-21 07:04:50 +00:00
par64 |= phys_addr & ~0xfffULL;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
if (!attrs.secure) {
par64 |= (1 << 9); /* NS */
}
import
2015-08-21 07:04:50 +00:00
/* We don't set the ATTR or SH fields in the PAR. */
} else {
par64 |= 1; /* F */
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
par64 |= (fsr & 0x3f) << 1; /* FS */
import
2015-08-21 07:04:50 +00:00
/* Note that S2WLK and FSTAGE are always zero, because we don't
* implement virtualization and therefore there can't be a stage 2
* fault.
*/
}
} else {
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
/* fsr is a DFSR/IFSR value for the short descriptor
import
2015-08-21 07:04:50 +00:00
* translation table format (with WnR always clear).
* Convert it to a 32-bit PAR.
*/
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
if (!ret) {
import
2015-08-21 07:04:50 +00:00
/* We do not set any attribute bits in the PAR */
if (page_size == (1 << 24)
&& arm_feature(env, ARM_FEATURE_V7)) {
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
par64 = (phys_addr & 0xff000000) | 1 << 1;
import
2015-08-21 07:04:50 +00:00
} else {
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
par64 = phys_addr & 0xfffff000;
import
2015-08-21 07:04:50 +00:00
}
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
if (!attrs.secure) {
par64 |= (1 << 9); /* NS */
}
import
2015-08-21 07:04:50 +00:00
} else {
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
((fsr & 0xf) << 1) | 1;
import
2015-08-21 07:04:50 +00:00
}
}
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
return par64;
}
static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
int access_type = ri->opc2 & 1;
uint64_t par64;
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
ARMMMUIdx mmu_idx;
int el = arm_current_el(env);
bool secure = arm_is_secure_below_el3(env);
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
switch (ri->opc2 & 6) {
case 0:
/* stage 1 current state PL1: ATS1CPR, ATS1CPW */
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_S1E3;
break;
case 2:
mmu_idx = ARMMMUIdx_S1NSE1;
break;
case 1:
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
break;
default:
g_assert_not_reached();
}
break;
case 2:
/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_S1SE0;
break;
case 2:
mmu_idx = ARMMMUIdx_S1NSE0;
break;
case 1:
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break;
default:
g_assert_not_reached();
}
break;
case 4:
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
mmu_idx = ARMMMUIdx_S12NSE1;
break;
case 6:
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
mmu_idx = ARMMMUIdx_S12NSE0;
break;
default:
g_assert_not_reached();
}
par64 = do_ats_write(env, value, access_type, mmu_idx);
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
A32_BANKED_CURRENT_REG_SET(env, par, par64);
import
2015-08-21 07:04:50 +00:00
}
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
int access_type = ri->opc2 & 1;
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
ARMMMUIdx mmu_idx;
int secure = arm_is_secure_below_el3(env);
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
switch (ri->opc2 & 6) {
case 0:
switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W */
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
break;
case 4: /* AT S1E2R, AT S1E2W */
mmu_idx = ARMMMUIdx_S1E2;
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx = ARMMMUIdx_S1E3;
break;
default:
g_assert_not_reached();
}
break;
case 2: /* AT S1E0R, AT S1E0W */
mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
break;
case 4: /* AT S12E1R, AT S12E1W */
mmu_idx = ARMMMUIdx_S12NSE1;
break;
case 6: /* AT S12E0R, AT S12E0W */
mmu_idx = ARMMMUIdx_S12NSE0;
break;
default:
g_assert_not_reached();
}
env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
}
import
2015-08-21 07:04:50 +00:00
#endif
static const ARMCPRegInfo vapa_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PAR", 15,7,4, 0,0,0, 0,
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.par_s), offsetoflow32(CPUARMState, cp15.par_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, par_write },
import
2015-08-21 07:04:50 +00:00
#ifndef CONFIG_USER_ONLY
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ATS", 15,7,8, 0,0,CP_ANY, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
ats_access, NULL, ats_write },
import
2015-08-21 07:04:50 +00:00
#endif
REGINFO_SENTINEL
};
/* Return basic MPU access permission bits. */
static uint32_t simple_mpu_ap_bits(uint32_t val)
{
uint32_t ret;
uint32_t mask;
int i;
ret = 0;
mask = 3;
for (i = 0; i < 16; i += 2) {
ret |= (val >> i) & mask;
mask <<= 2;
}
return ret;
}
/* Pad basic MPU access permission bits to extended format. */
static uint32_t extended_mpu_ap_bits(uint32_t val)
{
uint32_t ret;
uint32_t mask;
int i;
ret = 0;
mask = 3;
for (i = 0; i < 16; i += 2) {
ret |= (val & mask) << i;
mask <<= 2;
}
return ret;
}
static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
}
static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
}
static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
}
static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
}
target-arm: Add registers for PMSAv7 Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Backports commit 6cb0b013a1fa421cdfb83257cd33f855cc90649a from qemu
2018-02-13 21:06:06 +00:00
static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
if (!u32p) {
return 0;
}
u32p += env->cp15.c6_rgnr;
return *u32p;
}
static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
if (!u32p) {
return;
}
u32p += env->cp15.c6_rgnr;
tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
*u32p = value;
}
static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
if (!u32p) {
return;
}
memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
}
static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t nrgs = cpu->pmsav7_dregion;
if (value >= nrgs) {
qemu_log_mask(LOG_GUEST_ERROR,
"PMSAv7 RGNR write >= # supported regions, %" PRIu32
" > %" PRIu32 "\n", (uint32_t)value, nrgs);
return;
}
raw_write(env, ri, value);
}
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
{ "DRBAR", 15,6,1, 0,0,0, 0,ARM_CP_NO_RAW,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drbar), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
{ "DRSR", 15,6,1, 0,0,2, 0,ARM_CP_NO_RAW,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drsr), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
{ "DRACR", 15,6,1, 0,0,4, 0,ARM_CP_NO_RAW,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
{ "RGNR", 15,6,2, 0,0,0, 0,0,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_rgnr), {0, 0},
NULL, NULL, pmsav7_rgnr_write },
REGINFO_SENTINEL
};
import
2015-08-21 07:04:50 +00:00
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DATA_AP", 15,5,0, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_data_ap), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, pmsav5_data_ap_read, pmsav5_data_ap_write, },
{ "INSN_AP", 15,5,0, 0,0,1, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS,PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_insn_ap), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, pmsav5_insn_ap_read, pmsav5_insn_ap_write, },
{ "DATA_EXT_AP", 15,5,0, 0,0,2, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_data_ap), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "INSN_EXT_AP", 15,5,0, 0,0,3, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_insn_ap), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DCACHE_CFG", 15,2,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c2_data), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ICACHE_CFG", 15,2,0, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c2_insn), },
import
2015-08-21 07:04:50 +00:00
/* Protection region base and size registers */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS0", 15,6,0, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[0]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS1", 15,6,1, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[1]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS2", 15,6,2, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[2]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS3", 15,6,3, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[3]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS4", 15,6,4, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[4]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS5", 15,6,5, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[5]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS6", 15,6,6, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[6]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "946_PRBS7", 15,6,7, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_region[7]) },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
TCR *tcr = raw_ptr(env, ri);
import
2015-08-21 07:04:50 +00:00
int maskshift = extract32(value, 0, 3);
if (!arm_feature(env, ARM_FEATURE_V8)) {
if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
/* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
* using Long-desciptor translation table format */
value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
} else if (arm_feature(env, ARM_FEATURE_EL3)) {
/* In an implementation that includes the Security Extensions
* TTBCR has additional fields PD0 [4] and PD1 [5] for
* Short-descriptor translation table format.
*/
value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
} else {
value &= TTBCR_N;
}
}
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
/* Update the masks corresponding to the the TCR bank being written
* Note that we always calculate mask and base_mask, but
import
2015-08-21 07:04:50 +00:00
* they are only used for short-descriptor tables (ie if EAE is 0);
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
* for long-descriptor tables the TCR fields are used differently
* and the mask and base_mask values are meaningless.
import
2015-08-21 07:04:50 +00:00
*/
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
tcr->raw_tcr = value;
tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
import
2015-08-21 07:04:50 +00:00
}
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (arm_feature(env, ARM_FEATURE_LPAE)) {
/* With LPAE the TTBCR could result in a change of ASID
* via the TTBCR.A1 bit, so do a TLB flush.
*/
tlb_flush(CPU(cpu), 1);
}
vmsa_ttbcr_raw_write(env, ri, value);
}
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
TCR *tcr = raw_ptr(env, ri);
/* Reset both the TCR as well as the masks corresponding to the bank of
* the TCR being reset.
*/
tcr->raw_tcr = 0;
tcr->mask = 0;
tcr->base_mask = 0xffffc000u;
import
2015-08-21 07:04:50 +00:00
}
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
TCR *tcr = raw_ptr(env, ri);
import
2015-08-21 07:04:50 +00:00
/* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
tlb_flush(CPU(cpu), 1);
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
tcr->raw_tcr = value;
import
2015-08-21 07:04:50 +00:00
}
static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* 64 bit accesses to the TTBRs can change the ASID and so we
* must flush the TLB.
*/
if (cpreg_field_is_64bit(ri)) {
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
}
raw_write(env, ri, value);
}
arm: helper: Factor out CP regs common to [pv]msa V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Backports commit 8e5d75c950a1241f6e1243c37f28cd58f68fedc9 from qemu
2018-02-13 19:39:32 +00:00
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DFSR", 15,5,0, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, 0,
target-arm: make DFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Backports commit 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b from qemu
2018-02-12 14:10:35 +00:00
{ offsetoflow32(CPUARMState, cp15.dfsr_s), offsetoflow32(CPUARMState, cp15.dfsr_ns) },
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
NULL, NULL, NULL, NULL, NULL, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "IFSR", 15,5,0, 0,0,1, 0,
target-arm: make IFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Backports commit 88ca1c2d70523486a952065f3ed7b8fc823b5863 from qemu
2018-02-12 14:07:49 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.ifsr_s), offsetoflow32(CPUARMState, cp15.ifsr_ns) }},
arm: helper: Factor out CP regs common to [pv]msa V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Backports commit 8e5d75c950a1241f6e1243c37f28cd58f68fedc9 from qemu
2018-02-13 19:39:32 +00:00
{ "FAR_EL1", 0,6,0, 3,0,0, ARM_CP_STATE_AA64,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[1]), },
{ "DFAR", 15,6,0, 0,0,0, 0,0,
PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.dfar_s), offsetof(CPUARMState, cp15.dfar_ns) } },
REGINFO_SENTINEL
};
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ESR_EL1", 0,5,2, 3,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[1]), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TTBR0_EL1", 0,2,0, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: make TTBR0/1 banked Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Backports commit 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc to qemu
2018-02-12 00:45:04 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, vmsa_ttbr_write, },
{ "TTBR1_EL1", 0,2,0, 3,0,1, ARM_CP_STATE_BOTH,
target-arm: make TTBR0/1 banked Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Backports commit 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc to qemu
2018-02-12 00:45:04 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, vmsa_ttbr_write, },
{ "TCR_EL1", 0,2,0, 3,0,2, ARM_CP_STATE_AA64,
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[1]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,vmsa_tcr_el1_write, NULL,raw_write, vmsa_ttbcr_reset, },
{ "TTBCR", 15,2,0, 0,0,2, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, 0,
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
{ offsetoflow32(CPUARMState, cp15.tcr_el[3]), offsetoflow32(CPUARMState, cp15.tcr_el[1]) },
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
NULL, NULL, vmsa_ttbcr_write, NULL, vmsa_ttbcr_raw_write, NULL },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c15_ticonfig = value & 0xe7;
/* The OS_TYPE bit in this register changes the reported CPUID! */
env->cp15.c0_cpuid = (value & (1 << 5)) ?
ARM_CPUID_TI915T : ARM_CPUID_TI925T;
}
static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c15_threadid = value & 0xffff;
}
static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Wait-for-interrupt (deprecated) */
cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
}
static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* On OMAP there are registers indicating the max/min index of dcache lines
* containing a dirty line; cache flush operations have to reset these.
*/
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
}
static const ARMCPRegInfo omap_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DFSR", 15,5,CP_ANY, 0,CP_ANY,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.esr_el[1]), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "", 15,15,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_NOP, PL1_RW, 0, NULL, 0, 0, },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TICONFIG", 15,15,1, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c15_ticonfig), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, omap_ticonfig_write },
{ "IMAX", 15,15,2, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c15_i_max), },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "IMIN", 15,15,3, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0xff0, offsetof(CPUARMState, cp15.c15_i_min) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "THREADID", 15,15,4, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c15_threadid), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, omap_threadid_write },
{ "TI925T_STATUS", 15,15,8, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, arm_cp_read_zero, omap_wfi_write, },
import
2015-08-21 07:04:50 +00:00
/* TODO: Peripheral port remap register:
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
* when MMU is off.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "OMAP_CACHEMAINT", 15,7,CP_ANY, 0,0,CP_ANY, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_OVERRIDE | ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, omap_cachemaint_write },
{ "C9", 15,9,CP_ANY, 0,CP_ANY,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST | ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, 0, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c15_cpar = value & 0x3fff;
}
static const ARMCPRegInfo xscale_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "XSCALE_CPAR", 15,15,1, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c15_cpar), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, xscale_cpar_write, },
{ "XSCALE_AUXCR", 15,1,0, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c1_xscaleauxcr), },
import
2015-08-21 07:04:50 +00:00
/* XScale specific cache-lockdown: since we have no cache we NOP these
* and hope the guest does not really rely on cache behaviour.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "XSCALE_LOCK_ICACHE_LINE", 15,9,1, 0,0,0, 0,
ARM_CP_NOP, PL1_W },
{ "XSCALE_UNLOCK_ICACHE", 15,9,1, 0,0,1, 0,
ARM_CP_NOP, PL1_W, },
{ "XSCALE_DCACHE_LOCK", 15,9,2, 0,0,0, 0,
ARM_CP_NOP, PL1_RW },
{ "XSCALE_UNLOCK_DCACHE", 15,9,2, 0,0,1, 0,
ARM_CP_NOP, PL1_W, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
/* RAZ/WI the whole crn=15 space, when we don't have a more specific
* implementation of this implementation-defined space.
* Ideally this should eventually disappear in favour of actually
* implementing the correct behaviour for all cores.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "C15_IMPDEF", 15,15,CP_ANY, 0,CP_ANY,CP_ANY, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
/* Cache status: RAZ because we have no cache so it's always clean */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CDSR", 15,7,10, 0,0,6, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_NO_RAW, PL1_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
/* We never have a a block transfer operation in progress */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "BXSR", 15,7,12, 0,0,4, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_NO_RAW, PL0_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* The cache ops themselves: these all NOP for QEMU */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "IICR", 15, 0,5, 0,0, 0, 0,
ARM_CP_NOP|ARM_CP_64BIT, PL1_W },
{ "IDCR", 15, 0,6, 0,0, 0, 0,
ARM_CP_NOP|ARM_CP_64BIT, PL1_W, },
{ "CDCR", 15, 0,12, 0,0, 0, 0,
ARM_CP_NOP|ARM_CP_64BIT, PL0_W, },
{ "PIR", 15, 0,12, 0,1, 0, 0,
ARM_CP_NOP|ARM_CP_64BIT, PL0_W, },
{ "PDR", 15, 0,12, 0,2, 0, 0,
ARM_CP_NOP|ARM_CP_64BIT, PL0_W, },
{ "CIDCR", 15, 0,14, 0,0, 0, 0,
ARM_CP_NOP|ARM_CP_64BIT, PL1_W, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
/* The cache test-and-clean instructions always return (1 << 30)
* to indicate that there are no dirty cache lines.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TC_DCACHE", 15,7,10, 0,0,3, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_NO_RAW, PL0_R, 0, NULL, (1 << 30) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TCI_DCACHE", 15,7,14, 0,0,3, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_NO_RAW, PL0_R, 0, NULL, (1 << 30) },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
/* Ignore ReadBuffer accesses */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "C9_READBUFFER", 15,9,CP_ANY, 0,CP_ANY,CP_ANY, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW, PL1_RW, 0, NULL, 0, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
target-arm: Use the kernel's idea of MPIDR if we're using KVM When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Backports commit eb5e1d3c85dffe677da2550d211f9304a7d5ba3b from qemu
2018-02-13 19:31:09 +00:00
ARMCPU *cpu = ARM_CPU(env->uc, arm_env_get_cpu(env));
uint64_t mpidr = cpu->mp_affinity;
import
2015-08-21 07:04:50 +00:00
if (arm_feature(env, ARM_FEATURE_V7MP)) {
mpidr |= (1U << 31);
/* Cores which are uniprocessor (non-coherent)
* but still implement the MP extensions set
arm: Implement uniprocessor with MP config Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Backports commit a8e81b319d1ae1224cc7059877dcdf04a5aad59d from qemu
2018-02-13 19:50:12 +00:00
* bit 30. (For instance, Cortex-R5).
import
2015-08-21 07:04:50 +00:00
*/
arm: Implement uniprocessor with MP config Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Backports commit a8e81b319d1ae1224cc7059877dcdf04a5aad59d from qemu
2018-02-13 19:50:12 +00:00
if (cpu->mp_is_up) {
mpidr |= (1u << 30);
}
import
2015-08-21 07:04:50 +00:00
}
return mpidr;
}
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MPIDR", 0,0,0, 3,0,5, ARM_CP_STATE_BOTH,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, mpidr_read, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo lpae_cp_reginfo[] = {
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
/* NOP AMAIR0/1 */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AMAIR0", 0,10,3, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AMAIR1", 15,10,3, 0,0,1, 0,
target-arm: Break down TLB_LOCKDOWN Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Backports commit a903c449b41f105aadd5f762a7aede531b4950f0 from qemu
2018-02-13 04:21:15 +00:00
ARM_CP_CONST, PL1_RW, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "PAR", 15, 0,7, 0,0, 0, 0,
target-arm: make PAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
2018-02-12 14:37:39 +00:00
ARM_CP_64BIT, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.par_s), offsetof(CPUARMState, cp15.par_ns) } },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TTBR0", 15, 0,2, 0,0, 0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_64BIT | ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, 0,
target-arm: make TTBR0/1 banked Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Backports commit 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc to qemu
2018-02-12 00:45:04 +00:00
{ offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) },
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
NULL, NULL, vmsa_ttbr_write, NULL, NULL, NULL },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TTBR1", 15, 0,2, 0,1, 0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_64BIT | ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, 0,
target-arm: make TTBR0/1 banked Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Backports commit 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc to qemu
2018-02-12 00:45:04 +00:00
{ offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) },
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
NULL, NULL, vmsa_ttbr_write, NULL, NULL, NULL },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return vfp_get_fpcr(env);
}
static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
vfp_set_fpcr(env, value);
}
static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return vfp_get_fpsr(env);
}
static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
vfp_set_fpsr(env, value);
}
static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
import
2015-08-21 07:04:50 +00:00
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->daif = value & PSTATE_DAIF;
}
static CPAccessResult aa64_cacheop_access(CPUARMState *env,
const ARMCPRegInfo *ri)
{
/* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
* SCTLR_EL1.UCI is set.
*/
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
import
2015-08-21 07:04:50 +00:00
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
* Page D4-1736 (DDI0487A.b)
*/
static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by VA (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page(CPU(cpu), pageaddr);
}
static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by VA, all ASIDs (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page(CPU(cpu), pageaddr);
}
static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env);
int asid = extract64(value, 48, 16);
tlb_flush(CPU(cpu), asid == 0);
}
static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm64: disable deadcode introduced by PR #643
2016-09-29 04:34:44 +00:00
//uint64_t pageaddr = sextract64(value << 12, 0, 56);
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, pageaddr);
import
2015-08-21 07:04:50 +00:00
}
static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm64: disable deadcode introduced by PR #643
2016-09-29 04:34:44 +00:00
//uint64_t pageaddr = sextract64(value << 12, 0, 56);
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, pageaddr);
import
2015-08-21 07:04:50 +00:00
}
static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
arm64: disable deadcode introduced by PR #643
2016-09-29 04:34:44 +00:00
//int asid = extract64(value, 48, 16);
//struct uc_struct *uc = env->uc;
remove uc->cpus
2016-09-23 14:38:21 +00:00
// TODO: issue #642
// tlb_flush(other_cpu, asid == 0);
import
2015-08-21 07:04:50 +00:00
}
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* We don't implement EL2, so the only control on DC ZVA is the
* bit in the SCTLR which can prohibit access for EL0.
*/
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
import
2015-08-21 07:04:50 +00:00
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int dzp_bit = 1 << 4;
/* DZP indicates whether DC ZVA access is allowed */
if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
dzp_bit = 0;
}
return cpu->dcz_blocksize | dzp_bit;
}
static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (!(env->pstate & PSTATE_SP)) {
/* Access to SP_EL0 is undefined if it's being used as
* the stack pointer.
*/
return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return CP_ACCESS_OK;
}
static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return env->pstate & PSTATE_SP;
}
static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
{
update_spsel(env, val);
}
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (raw_read(env, ri) == value) {
/* Skip the TLB flush if nothing actually changed; Linux likes
* to do a lot of pointless SCTLR writes.
*/
return;
}
raw_write(env, ri, value);
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu), 1);
}
import
2015-08-21 07:04:50 +00:00
static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "NZCV", 0,4,2, 3,3,0, ARM_CP_STATE_AA64,
ARM_CP_NZCV, PL0_RW, },
{ "DAIF", 0,4,2, 3,3,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, daif), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
aa64_daif_access, NULL, aa64_daif_write, NULL,NULL, arm_cp_reset_ignore },
{ "FPCR", 0,4,4, 3,3,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, aa64_fpcr_read, aa64_fpcr_write },
{ "FPSR", 0,4,4, 3,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL0_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, aa64_fpsr_read, aa64_fpsr_write },
{ "DCZID_EL0", 0,0,0, 3,3,7, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL0_R, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, aa64_dczid_read },
{ "DC_ZVA", 0,7,4, 1,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_DC_ZVA, PL0_W, 0, NULL, 0, 0, {0, 0},
import
2015-08-21 07:04:50 +00:00
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
aa64_zva_access,
import
2015-08-21 07:04:50 +00:00
#endif
},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CURRENTEL", 0,4,2, 3,0,2, ARM_CP_STATE_AA64,
ARM_CP_CURRENTEL, PL1_R, },
import
2015-08-21 07:04:50 +00:00
/* Cache ops: all NOPs since we don't emulate caches */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "IC_IALLUIS", 0,7,1, 1,0,0, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
{ "IC_IALLU", 0,7,5, 1,0,0, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
{ "IC_IVAU", 0,7,5, 1,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
aa64_cacheop_access },
{ "DC_IVAC", 0,7,6, 1,0,1, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
{ "DC_ISW", 0,7,6, 1,0,2, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
{ "DC_CVAC", 0,7,10, 1,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
aa64_cacheop_access },
{ "DC_CSW", 0,7,10, 1,0,2, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
{ "DC_CVAU", 0,7,11, 1,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
aa64_cacheop_access },
{ "DC_CIVAC", 0,7,14, 1,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
aa64_cacheop_access },
{ "DC_CISW", 0,7,14, 1,0,2, ARM_CP_STATE_AA64,
ARM_CP_NOP, PL1_W, },
import
2015-08-21 07:04:50 +00:00
/* TLBI operations */
target-arm: Add TLBI_ALLE1{IS} Backports commit bdb9e2d66afbe0571dce48a9430c35ae4d6bbd32 from qemu
2018-02-13 13:07:38 +00:00
{ "TLBI_ALLE1", 0,8,7, 1,4,4, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_write },
{ "TLBI_ALLE1IS", 0,8,3, 1,4,4, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
target-arm: fix write helper for TLBI ALLE1IS TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Backports commit 2a6332d968297266dbabf9d33f959e3a5efdd0f9 from qemu
2018-02-14 03:43:17 +00:00
NULL, NULL, tlbiall_is_write },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TLBI_VMALLE1IS", 0,8,3, 1,0,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_is_write },
{ "TLBI_VAE1IS", 0,8,3, 1,0,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_va_is_write },
{ "TLBI_ASIDE1IS", 0,8,3, 1,0,2, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_asid_is_write },
{ "TLBI_VAAE1IS", 0,8,3, 1,0,3, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_vaa_is_write },
{ "TLBI_VALE1IS", 0,8,3, 1,0,5, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_va_is_write },
{ "TLBI_VAALE1IS", 0,8,3, 1,0,7, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_vaa_is_write },
{ "TLBI_VMALLE1", 0,8,7, 1,0,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbiall_write },
{ "TLBI_VAE1", 0,8,7, 1,0,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_va_write },
{ "TLBI_ASIDE1", 0,8,7, 1,0,2, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_asid_write },
{ "TLBI_VAAE1", 0,8,7, 1,0,3, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_vaa_write },
{ "TLBI_VALE1", 0,8,7, 1,0,5, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_va_write },
{ "TLBI_VAALE1", 0,8,7, 1,0,7, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbi_aa64_vaa_write },
import
2015-08-21 07:04:50 +00:00
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AT_S1E1R", 0,7,8, 1,0,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
NULL, NULL, ats_write64 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AT_S1E1W", 0,7,8, 1,0,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
NULL, NULL, ats_write64 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AT_S1E0R", 0,7,8, 1,0,2, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
NULL, NULL, ats_write64 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "AT_S1E0W", 0,7,8, 1,0,3, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
target-arm: Split AArch64 cases out of ats_write() Instead of simply reusing ats_write() as the handler for both AArch32 and AArch64 address translation operations, use a different function for each with the common code in a third function. This is necessary because the semantics for selecting the right translation regime are different; we are only getting away with sharing currently because we don't support EL2 and only support EL3 in AArch32. Backports commit 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6 from qemu
2018-02-12 16:35:48 +00:00
NULL, NULL, ats_write64 },
import
2015-08-21 07:04:50 +00:00
#endif
/* TLB invalidate last level of translation table walk */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TLBIMVALIS", 15,8,3, 0,0,5, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_is_write },
{ "TLBIMVAALIS", 15,8,3, 0,0,7, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimvaa_is_write },
{ "TLBIMVAL", 15,8,7, 0,0,5, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimva_write },
{ "TLBIMVAAL", 15,8,7, 0,0,7, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_W, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, tlbimvaa_write },
import
2015-08-21 07:04:50 +00:00
/* 32 bit cache operations */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ICIALLUIS", 15,7,1, 0,0,0, 0,
ARM_CP_NOP, PL1_W },
{ "BPIALLUIS", 15,7,1, 0,0,6, 0,
ARM_CP_NOP, PL1_W },
{ "ICIALLU", 15,7,5, 0,0,0, 0,
ARM_CP_NOP, PL1_W },
Arm issue fix. (#738) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file * Arm issue fix.
2017-01-24 09:45:01 +00:00
{ "ICIMVAU", 15,7,5, 0,0,1, 0,
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
ARM_CP_NOP, PL1_W },
{ "BPIALL", 15,7,5, 0,0,6, 0,
ARM_CP_NOP, PL1_W },
{ "BPIMVA", 15,7,5, 0,0,7, 0,
ARM_CP_NOP, PL1_W },
{ "DCIMVAC", 15,7,6, 0,0,1, 0,
ARM_CP_NOP, PL1_W },
{ "DCISW", 15,7,6, 0,0,2, 0,
ARM_CP_NOP, PL1_W },
{ "DCCMVAC", 15,7,10, 0,0,1, 0,
ARM_CP_NOP, PL1_W },
{ "DCCSW", 15,7,10, 0,0,2, 0,
ARM_CP_NOP, PL1_W },
{ "DCCMVAU", 15,7,11, 0,0,1, 0,
ARM_CP_NOP, PL1_W },
{ "DCCIMVAC", 15,7,14, 0,0,1, 0,
ARM_CP_NOP, PL1_W },
{ "DCCISW", 15,7,14, 0,0,2, 0,
ARM_CP_NOP, PL1_W },
import
2015-08-21 07:04:50 +00:00
/* MMU Domain access control / MPU write buffer control */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DACR", 15,3,0, 0,0,0, 0,
target-arm: make DACR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Backports commit 0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0 from qemu
2018-02-12 14:01:14 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,dacr_write, NULL,raw_write, },
{ "ELR_EL1", 0,4,0, 3,0,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[1]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "SPSR_EL1", 0,4,0, 3,0,0, ARM_CP_STATE_AA64,
target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) The AArch64 SPSR_EL1 register is architecturally mandated to be mapped to the AArch32 SPSR_svc register. This means its state should live in QEMU's env->banked_spsr[1] field. Correct the various places in the code that incorrectly put it in banked_spsr[0]. Backports commit 7847f9ea9fce15a9ecfb62ab72c1e84ff516b0db from qemu
2018-02-12 21:36:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[1]) },
import
2015-08-21 07:04:50 +00:00
/* We rely on the access checks not allowing the guest to write to the
* state field when SPSel indicates that it's being used as the stack
* pointer.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "SP_EL0", 0,4,1, 3,0,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, sp_el[0]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
sp_el0_access, },
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
{ "SP_EL1", 0,4,1, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
target-arm: Add missing SP_ELx register definition Added CP register definitions for SP_EL1 and SP_EL2. Backports commit 884b4deeeb8b158ed3db5792161902bc8b41b62d from qemu
2018-02-12 15:38:12 +00:00
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, sp_el[1]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "SPSel", 0,4,2, 3,0,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL1_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, spsel_read, spsel_write },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arrays The ARMCPRegInfo arrays v8_el3_no_el2_cp_reginfo and v8_el2_cp_reginfo are actually used on non-v8 CPUs as well. Remove the incorrect v8_ prefix from their names. Backports commit 4771cd01daaccb2a8929fa04c88c608e378cf814 from qemu
2018-02-13 13:15:53 +00:00
static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL2_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, arm_cp_read_zero, arm_cp_write_ignore },
{ "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_NO_RAW, PL2_RW, 0, NULL, 0, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, arm_cp_read_zero, arm_cp_write_ignore },
target-arm: Add AArch64 CPTR registers Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Backports commit c6f191642a4027909813b4e6e288411f8371e951 from qemu
2018-02-13 03:53:01 +00:00
{ "CPTR_EL2", 0,1,1, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add MAIR_EL2 Backports commit 95f949ac3dc7d4a6ebee512a9d122db18210df64 from qemu
2018-02-13 04:26:35 +00:00
{ "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add TCR_EL2 Backports commit 06ec4c8c9f9e21b7671c79296f3a47ab63d50067 from qemu
2018-02-13 04:32:35 +00:00
{ "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add SCTLR_EL2 Backports commit b9cb5323bb671a0f2bfecc36168d3a3763e90261 from qemu
2018-02-13 12:57:35 +00:00
{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add TPIDR_EL2 Backports commit ff05f37babe7874f28dcead6e9e4f1904d35a13a from qemu
2018-02-13 13:00:09 +00:00
{ "TPIDR_EL2", 0,13,0, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add TTBR0_EL2 Backports commit a57633c08fa861807a0713505785bd4d441d7df8 from qemu
2018-02-13 13:04:32 +00:00
{ "TTBR0_EL2", 0,2,0, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "HTTBR", 15,0,2, 0,4,0, 0, ARM_CP_64BIT | ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
{ "CNTHCTL_EL2", 0,14,1, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
{ "CNTVOFF_EL2", 0,14,0, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "CNTVOFF", 15,0,14, 0,4,0, ARM_CP_64BIT | ARM_CP_CONST, 0,
PL2_RW, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t valid_mask = HCR_MASK;
if (arm_feature(env, ARM_FEATURE_EL3)) {
valid_mask &= ~HCR_HCD;
} else {
valid_mask &= ~HCR_TSC;
}
/* Clear RES0 bits. */
value &= valid_mask;
/* These bits change the MMU setup:
* HCR_VM enables stage 2 translation
* HCR_PTW forbids certain page-table setups
* HCR_DC Disables stage1 and enables stage2 translation
*/
if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
tlb_flush(CPU(cpu), 1);
}
raw_write(env, ri, value);
}
target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arrays The ARMCPRegInfo arrays v8_el3_no_el2_cp_reginfo and v8_el2_cp_reginfo are actually used on non-v8 CPUs as well. Remove the incorrect v8_ prefix from their names. Backports commit 4771cd01daaccb2a8929fa04c88c608e378cf814 from qemu
2018-02-13 13:15:53 +00:00
static const ARMCPRegInfo el2_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, hcr_write },
target-arm: make DACR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Backports commit 0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0 from qemu
2018-02-12 14:01:14 +00:00
{ "DACR32_EL2", 0,3,0, 3,4,0, ARM_CP_STATE_AA64,0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dacr32_el2), {0, 0},
NULL, NULL, dacr_write, NULL, raw_write },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
target-arm: make IFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Backports commit 88ca1c2d70523486a952065f3ed7b8fc823b5863 from qemu
2018-02-12 14:07:49 +00:00
{ "IFSR32_EL2", 0,5,0, 3,4,1, ARM_CP_STATE_AA64,0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ifsr32_el2) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[6]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[2]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, vbar_write, },
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
{ "SP_EL2", 0,4,1, 3,6,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
target-arm: Add missing SP_ELx register definition Added CP register definitions for SP_EL1 and SP_EL2. Backports commit 884b4deeeb8b158ed3db5792161902bc8b41b62d from qemu
2018-02-12 15:38:12 +00:00
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, sp_el[2]) },
target-arm: Add AArch64 CPTR registers Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Backports commit c6f191642a4027909813b4e6e288411f8371e951 from qemu
2018-02-13 03:53:01 +00:00
{ "CPTR_EL2", 0,1,1, 3,4,2, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cptr_el[2]), {0, 0},
cptr_access },
target-arm: Add MAIR_EL2 Backports commit 95f949ac3dc7d4a6ebee512a9d122db18210df64 from qemu
2018-02-13 04:26:35 +00:00
{ "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[2]) },
{ "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
target-arm: Add TCR_EL2 Backports commit 06ec4c8c9f9e21b7671c79296f3a47ab63d50067 from qemu
2018-02-13 04:32:35 +00:00
{ "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[2]), {0, 0},
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
target-arm: Add SCTLR_EL2 Backports commit b9cb5323bb671a0f2bfecc36168d3a3763e90261 from qemu
2018-02-13 12:57:35 +00:00
{ "SCTLR_EL2", 0,1,0, 3,4,0, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[2]), {0, 0},
NULL, NULL, sctlr_write, NULL, raw_write },
target-arm: Add TPIDR_EL2 Backports commit ff05f37babe7874f28dcead6e9e4f1904d35a13a from qemu
2018-02-13 13:00:09 +00:00
{ "TPIDR_EL2", 0,13,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[2]) },
target-arm: Add TTBR0_EL2 Backports commit a57633c08fa861807a0713505785bd4d441d7df8 from qemu
2018-02-13 13:04:32 +00:00
{ "TTBR0_EL2", 0,2,0, 3,4,0, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ "HTTBR", 15,0,2, 0,4,0, 0, ARM_CP_64BIT | ARM_CP_ALIAS,
target-arm: Add TLBI_ALLE2 Backports commit 51da90140bba4333eeb9c1d8d8d8afc2ca790628 from qemu
2018-02-13 13:10:34 +00:00
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ "TLBI_ALLE2", 0,8,7, 1,4,0, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbiall_write },
target-arm: Add TLBI_VAE2{IS} Backports commit 8742d49d6f2278d353a1623dfa8a5e237dbfd906 from qemu
2018-02-13 13:13:30 +00:00
{ "TLBI_VAE2", 0,8,7, 1,4,1, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbi_aa64_vaa_write },
{ "TLBI_VAE2IS", 0,8,3, 1,4,1, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
PL2_W, 0, NULL, 0, 0, {0, 0},
NULL, NULL, tlbi_aa64_vaa_write },
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
#ifndef CONFIG_USER_ONLY
target-arm: Add CNTHCTL_EL2 Adds control for trapping selected timer and counter accesses to EL2. Backports commit 0b6440afb807a80c6d64dcc987bcfed87e1ace17 from qemu
2018-02-15 00:52:20 +00:00
/* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
* reset values as IMPDEF. We choose to reset to 3 to comply with
* both ARMv7 and ARMv8.
*/
{ "CNTHCTL_EL2", 0,14,1, 3,4,0, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 3, offsetof(CPUARMState, cp15.cnthctl_el2) },
target-arm: Add CNTVOFF_EL2 Adds support for the virtual timer offset controlled by EL2. Backports commit edac4d8a168b9c0c4a765bbc5507e46fa5557b78 from qemu
2018-02-15 00:43:51 +00:00
{ "CNTVOFF_EL2", 0,140,0, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cntvoff_el2), {0, 0},
NULL, NULL, gt_cntvoff_write },
{ "CNTVOFF", 15,0,14, 0,4,0, 0, ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cntvoff_el2), {0, 0},
NULL, NULL, gt_cntvoff_write },
#endif
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
target-arm: Merge EL3 CP15 register lists Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists. Previously, some EL3 registers were restricted to the ARMv8 list under the impression that they were not needed on ARMv7. However, this is not the case as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle migration and reset. For this reason they must always exist. Backports commit 60fb1a87b47b14e4ea67043aa56f353e77fbd70a from qemu
2018-02-12 15:13:24 +00:00
static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "SCR_EL3", 0,1,1, 3,6,0, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.scr_el3), {0, 0},
NULL, NULL, scr_write },
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
{ "SCR", 15,1,1, 0,0,0, 0,ARM_CP_ALIAS,
target-arm: Merge EL3 CP15 register lists Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists. Previously, some EL3 registers were restricted to the ARMv8 list under the impression that they were not needed on ARMv7. However, this is not the case as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle migration and reset. For this reason they must always exist. Backports commit 60fb1a87b47b14e4ea67043aa56f353e77fbd70a from qemu
2018-02-12 15:13:24 +00:00
PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
NULL, NULL, scr_write, NULL, NULL, NULL },
target-arm: Merge EL3 CP15 register lists Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists. Previously, some EL3 registers were restricted to the ARMv8 list under the impression that they were not needed on ARMv7. However, this is not the case as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle migration and reset. For this reason they must always exist. Backports commit 60fb1a87b47b14e4ea67043aa56f353e77fbd70a from qemu
2018-02-12 15:13:24 +00:00
{ "SDER32_EL3", 0,1,1, 3,6,1, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sder) },
{ "SDER", 15,1,1, 0,0,1, 0,0,
PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.sder) },
/* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
{ "NSACR", 15,1,1, 0,0,2, 0,0,
PL3_W | PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.nsacr) },
{ "MVBAR", 15,12,0, 0,0,1, 0,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
NULL, NULL, vbar_write },
target-arm: Fix broken SCTLR_EL3 reset The SCTLR_EL3 cpreg definition was implicitly resetting the register state to 0, which is both wrong and clashes with the reset done via the SCTLR definition (since sctlr[3] is unioned with sctlr_s). This went unnoticed until recently, when an unrelated change (commit a903c449b41f105aa) happened to perturb the order of enumeration through the cpregs hashtable for reset such that the erroneous reset happened after the correct one rather than before it. Fix this by marking SCTLR_EL3 as an alias, so its reset is left up to the AArch32 view. Backports commit e46e1a74ef482f1ef773e750df9654ef4442ca29 from qemu
2018-02-14 20:08:44 +00:00
{ "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, /* reset handled by AArch32 view */
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},
NULL, NULL, sctlr_write, NULL, raw_write, },
target-arm: make TTBR0/1 banked Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Backports commit 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc to qemu
2018-02-12 00:45:04 +00:00
{ "TTBR0_EL3", 0,2,0, 3,6,0, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el[3]), {0, 0},
NULL, NULL, vmsa_ttbr_write },
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
{ "TCR_EL3", 0,2,0, 3,6,2, ARM_CP_STATE_AA64,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[3]), {0, 0},
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ELR_EL3", 0,4,0, 3,6,1, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[3]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[3]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "FAR_EL3", 0,6,0, 3,6,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[3]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "SPSR_EL3", 0,4,0, 3,6,0, ARM_CP_STATE_AA64,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[7]) },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "VBAR_EL3", 0,12,0, 3,6,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[3]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL, vbar_write, },
target-arm: Add AArch64 CPTR registers Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Backports commit c6f191642a4027909813b4e6e288411f8371e951 from qemu
2018-02-13 03:53:01 +00:00
{ "CPTR_EL3", 0,1,1, 3,6,2, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cptr_el[3]), {0, 0},
cptr_access },
target-arm: move AArch32 SCR into security reglist Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving AArch32 SCR into Security Extension register group. Backports commit 0f1a3b2470d798ad5335eb9d6236f02ff64e31a8 from qemu
2018-02-11 23:48:06 +00:00
REGINFO_SENTINEL
};
import
2015-08-21 07:04:50 +00:00
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
* but the AArch32 CTR has its own reginfo struct)
*/
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
import
2015-08-21 07:04:50 +00:00
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
static const ARMCPRegInfo debug_cp_reginfo[] = {
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
* debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
* unlike DBGDRAR it is never accessible from EL0.
* DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
* accessor.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGDRAR", 14,1,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MDRAR_EL1", 0,1,0, 2,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGDSAR", 14,2,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
/* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MDSCR_EL1", 14,0,2, 2,0,2, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdscr_el1), },
import
2015-08-21 07:04:50 +00:00
/* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
* We don't implement the configurable EL0 access.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MDCCSR_EL0", 14,0,1, 2,0,0, ARM_CP_STATE_BOTH,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_ALIAS, PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.mdscr_el1), {0, 0},
target-arm: Do not reset sysregs marked as ALIAS cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Backports commit b061a82b8afcc45ce09d770d9c0acdf429401054 from qemu
2018-02-13 20:16:03 +00:00
NULL, NULL, NULL, NULL, NULL, NULL },
import
2015-08-21 07:04:50 +00:00
/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "OSLAR_EL1", 14,1,0, 2,0,4, ARM_CP_STATE_BOTH,
ARM_CP_NOP, PL1_W, },
import
2015-08-21 07:04:50 +00:00
/* Dummy OSDLR_EL1: 32-bit Linux will read this */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "OSDLR_EL1", 14,1,3, 2,0,4, ARM_CP_STATE_BOTH,
ARM_CP_NOP, PL1_RW, },
import
2015-08-21 07:04:50 +00:00
/* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
* implement vector catch debug events yet.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGVCR", 14,0,7, 0,0,0, 0,
ARM_CP_NOP, PL1_RW, },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
/* 64 bit access versions of the (dummy) debug registers */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGDRAR", 14, 0,1, 0,0, 0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST|ARM_CP_64BIT, PL0_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGDSAR", 14, 0,2, 0,0, 0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST|ARM_CP_64BIT, PL0_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
vaddr len = 0;
vaddr wvr = env->cp15.dbgwvr[n];
uint64_t wcr = env->cp15.dbgwcr[n];
int mask;
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
if (env->cpu_watchpoint[n]) {
cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
env->cpu_watchpoint[n] = NULL;
}
if (!extract64(wcr, 0, 1)) {
/* E bit clear : watchpoint disabled */
return;
}
switch (extract64(wcr, 3, 2)) {
case 0:
/* LSC 00 is reserved and must behave as if the wp is disabled */
return;
case 1:
flags |= BP_MEM_READ;
break;
case 2:
flags |= BP_MEM_WRITE;
break;
case 3:
flags |= BP_MEM_ACCESS;
break;
}
/* Attempts to use both MASK and BAS fields simultaneously are
* CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
* thus generating a watchpoint for every byte in the masked region.
*/
mask = extract64(wcr, 24, 4);
if (mask == 1 || mask == 2) {
/* Reserved values of MASK; we must act as if the mask value was
* some non-reserved value, or as if the watchpoint were disabled.
* We choose the latter.
*/
return;
} else if (mask) {
/* Watchpoint covers an aligned area up to 2GB in size */
len = 1ULL << mask;
/* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
* whether the watchpoint fires when the unmasked bits match; we opt
* to generate the exceptions.
*/
wvr &= ~(len - 1);
} else {
/* Watchpoint covers bytes defined by the byte address select bits */
int bas = extract64(wcr, 5, 8);
int basstart;
if (bas == 0) {
/* This must act as if the watchpoint is disabled */
return;
}
if (extract64(wvr, 2, 1)) {
/* Deprecated case of an only 4-aligned address. BAS[7:4] are
* ignored, and BAS[3:0] define which bytes to watch.
*/
bas &= 0xf;
}
/* The BAS bits are supposed to be programmed to indicate a contiguous
* range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
* we fire for each byte in the word/doubleword addressed by the WVR.
* We choose to ignore any non-zero bits after the first range of 1s.
*/
basstart = ctz32(bas);
len = cto32(bas >> basstart);
wvr += basstart;
}
cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
&env->cpu_watchpoint[n]);
}
void hw_watchpoint_update_all(ARMCPU *cpu)
{
int i;
CPUARMState *env = &cpu->env;
/* Completely clear out existing QEMU watchpoints and our array, to
* avoid possible stale entries following migration load.
*/
cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
hw_watchpoint_update(cpu, i);
}
}
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int i = ri->crm;
/* Bits [63:49] are hardwired to the value of bit [48]; that is, the
* register reads and behaves as if values written are sign extended.
* Bits [1:0] are RES0.
*/
value = sextract64(value, 0, 49) & ~3ULL;
raw_write(env, ri, value);
hw_watchpoint_update(cpu, i);
}
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int i = ri->crm;
raw_write(env, ri, value);
hw_watchpoint_update(cpu, i);
}
void hw_breakpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
uint64_t bvr = env->cp15.dbgbvr[n];
uint64_t bcr = env->cp15.dbgbcr[n];
vaddr addr;
int bt;
int flags = BP_CPU;
if (env->cpu_breakpoint[n]) {
cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
env->cpu_breakpoint[n] = NULL;
}
if (!extract64(bcr, 0, 1)) {
/* E bit clear : watchpoint disabled */
return;
}
bt = extract64(bcr, 20, 4);
switch (bt) {
case 4: /* unlinked address mismatch (reserved if AArch64) */
case 5: /* linked address mismatch (reserved if AArch64) */
qemu_log_mask(LOG_UNIMP,
"arm: address mismatch breakpoint types not implemented");
return;
case 0: /* unlinked address match */
case 1: /* linked address match */
{
/* Bits [63:49] are hardwired to the value of bit [48]; that is,
* we behave as if the register was sign extended. Bits [1:0] are
* RES0. The BAS field is used to allow setting breakpoints on 16
* bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
* a bp will fire if the addresses covered by the bp and the addresses
* covered by the insn overlap but the insn doesn't start at the
* start of the bp address range. We choose to require the insn and
* the bp to have the same address. The constraints on writing to
* BAS enforced in dbgbcr_write mean we have only four cases:
* 0b0000 => no breakpoint
* 0b0011 => breakpoint on addr
* 0b1100 => breakpoint on addr + 2
* 0b1111 => breakpoint on addr
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
*/
int bas = extract64(bcr, 5, 4);
addr = sextract64(bvr, 0, 49) & ~3ULL;
if (bas == 0) {
return;
}
if (bas == 0xc) {
addr += 2;
}
break;
}
case 2: /* unlinked context ID match */
case 8: /* unlinked VMID match (reserved if no EL2) */
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
qemu_log_mask(LOG_UNIMP,
"arm: unlinked context breakpoint types not implemented");
return;
case 9: /* linked VMID match (reserved if no EL2) */
case 11: /* linked context ID and VMID match (reserved if no EL2) */
case 3: /* linked context ID match */
default:
/* We must generate no events for Linked context matches (unless
* they are linked to by some other bp/wp, which is handled in
* updates for the linking bp/wp). We choose to also generate no events
* for reserved values.
*/
return;
}
cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
}
void hw_breakpoint_update_all(ARMCPU *cpu)
{
int i;
CPUARMState *env = &cpu->env;
/* Completely clear out existing QEMU breakpoints and our array, to
* avoid possible stale entries following migration load.
*/
cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
hw_breakpoint_update(cpu, i);
}
}
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int i = ri->crm;
raw_write(env, ri, value);
hw_breakpoint_update(cpu, i);
}
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int i = ri->crm;
/* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
* copy of BAS[0].
*/
value = deposit64(value, 6, 1, extract64(value, 5, 1));
value = deposit64(value, 8, 1, extract64(value, 7, 1));
raw_write(env, ri, value);
hw_breakpoint_update(cpu, i);
}
static void define_debug_regs(ARMCPU *cpu)
{
/* Define v7 and v8 architectural debug registers.
* These are just dummy implementations for now.
*/
int i;
int wrps, brps, ctx_cmps;
ARMCPRegInfo dbgdidr = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"DBGDIDR", 14,0,0, 0,0,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_R, 0, NULL, cpu->dbgdidr,
import
2015-08-21 07:04:50 +00:00
};
/* Note that all these register fields hold "number of Xs minus 1". */
brps = extract32(cpu->dbgdidr, 24, 4);
wrps = extract32(cpu->dbgdidr, 28, 4);
ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
assert(ctx_cmps <= brps);
/* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
* of the debug registers such as number of breakpoints;
* check that if they both exist then they agree.
*/
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
}
define_one_arm_cp_reg(cpu, &dbgdidr);
define_arm_cp_regs(cpu, debug_cp_reginfo);
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
}
for (i = 0; i < brps + 1; i++) {
ARMCPRegInfo dbgregs[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGBVR", 14,0,i, 2,0,4,ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dbgbvr[i]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,dbgbvr_write, NULL,raw_write
import
2015-08-21 07:04:50 +00:00
},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGBCR", 14,0,i, 2,0,5, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dbgbcr[i]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,dbgbcr_write, NULL,raw_write
import
2015-08-21 07:04:50 +00:00
},
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, dbgregs);
}
for (i = 0; i < wrps + 1; i++) {
ARMCPRegInfo dbgregs[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGWVR", 14,0,i, 2,0,6, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dbgwvr[i]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,dbgwvr_write, NULL,raw_write
import
2015-08-21 07:04:50 +00:00
},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DBGWCR", 14,0,i, 2,0,7, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dbgwcr[i]), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,dbgwcr_write, NULL,raw_write
import
2015-08-21 07:04:50 +00:00
},
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, dbgregs);
}
}
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
CPUARMState *env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_M)) {
/* M profile has no coprocessor registers */
return;
}
define_arm_cp_regs(cpu, cp_reginfo);
if (!arm_feature(env, ARM_FEATURE_V8)) {
/* Must go early as it is full of wildcards that may be
* overridden by later definitions.
*/
define_arm_cp_regs(cpu, not_v8_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V6)) {
/* The ID registers all have impdef reset values */
ARMCPRegInfo v6_idregs[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_PFR0", 0,0,1, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_pfr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_PFR1", 0,0,1, 3,0,1, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_pfr1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_DFR0", 0,0,1, 3,0,2, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_dfr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AFR0", 0,0,1, 3,0,3, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_afr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_MMFR0", 0,0,1, 3,0,4, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_mmfr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_MMFR1", 0,0,1, 3,0,5, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_mmfr1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_MMFR2", 0,0,1, 3,0,6, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_mmfr2 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_MMFR3", 0,0,1, 3,0,7, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_mmfr3 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR0", 0,0,2, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR1", 0,0,2, 3,0,1, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR2", 0,0,2, 3,0,2, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar2 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR3", 0,0,2, 3,0,3, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar3 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR4", 0,0,2, 3,0,4, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar4 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR5", 0,0,2, 3,0,5, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar5 },
import
2015-08-21 07:04:50 +00:00
/* 6..7 are as yet unallocated and must RAZ */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR6", 15,0,2, 0,0,6, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_ISAR7", 15,0,2, 0,0,7, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, v6_idregs);
define_arm_cp_regs(cpu, v6_cp_reginfo);
} else {
define_arm_cp_regs(cpu, not_v6_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V6K)) {
define_arm_cp_regs(cpu, v6k_cp_reginfo);
}
arm: Don't add v7mp registers in MPU systems These registers are VMSA specific so they should be conditional on VMSA (i.e. !MPU). Backports commit 5e5cf9e35f25f9f932a6ce25107c11b67b426a43 from qemu
2018-02-13 19:37:01 +00:00
if (arm_feature(env, ARM_FEATURE_V7MP) &&
!arm_feature(env, ARM_FEATURE_MPU)) {
import
2015-08-21 07:04:50 +00:00
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7)) {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
ARMCPRegInfo clidr = {
"CLIDR", 0,0,0, 3,1,1, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->clidr
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
};
import
2015-08-21 07:04:50 +00:00
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement only the cycle
* count register.
*/
#ifndef CONFIG_USER_ONLY
ARMCPRegInfo pmcr = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"PMCR", 15,9,12, 0,0,0, 0,
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
ARM_CP_IO | ARM_CP_ALIAS, PL0_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcr), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL,pmcr_write, NULL,raw_write,
import
2015-08-21 07:04:50 +00:00
};
ARMCPRegInfo pmcr64 = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"PMCR_EL0", 0,9,12, 3,3,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_IO, PL0_RW, 0, NULL, cpu->midr & 0xff000000, offsetof(CPUARMState, cp15.c9_pmcr), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
pmreg_access, NULL,pmcr_write, NULL,raw_write,
import
2015-08-21 07:04:50 +00:00
};
define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64);
#endif
define_one_arm_cp_reg(cpu, &clidr);
define_arm_cp_regs(cpu, v7_cp_reginfo);
define_debug_regs(cpu);
} else {
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V8)) {
/* AArch64 ID registers, which all have impdef reset values */
ARMCPRegInfo v8_idregs[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64pfr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64pfr1},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64DFR0_EL1", 0,0,5, 3,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL,
import
2015-08-21 07:04:50 +00:00
/* We mask out the PMUVer field, because we don't currently
* implement the PMU. Not advertising it prevents the guest
* from trying to use it and getting UNDEFs on registers we
* don't implement.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
cpu->id_aa64dfr0 & ~0xf00 },
{ "ID_AA64DFR1_EL1", 0,0,5, 3,0,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64dfr1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64AFR0_EL1", 0,0,5, 3,0,4, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64afr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64AFR1_EL1", 0,0,5, 3,0,5, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64afr1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64ISAR0_EL1", 0,0,6, 3,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64isar0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64ISAR1_EL1", 0,0,6, 3,0,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64isar1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64MMFR0_EL1", 0,0,7, 3,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64mmfr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "ID_AA64MMFR1_EL1", 0,0,7, 3,0,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64mmfr1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MVFR0_EL1", 0,0,3, 3,0,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MVFR1_EL1", 0,0,3, 3,0,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr1 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MVFR2_EL1", 0,0,3, 3,0,2, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr2 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
target-arm: Add extended RVBAR support Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers point to the same location and only the highest EL version exists at any one time. Backports commit be8e8128595b41b9f609c1507e67d121e65e7173 from qemu
2018-02-12 15:31:23 +00:00
/* RVBAR_EL1 is only implemented if EL1 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2)) {
ARMCPRegInfo rvbar = {
"RVBAR_EL1", 0,12,0, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
}
import
2015-08-21 07:04:50 +00:00
define_arm_cp_regs(cpu, v8_idregs);
define_arm_cp_regs(cpu, v8_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_EL2)) {
target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arrays The ARMCPRegInfo arrays v8_el3_no_el2_cp_reginfo and v8_el2_cp_reginfo are actually used on non-v8 CPUs as well. Remove the incorrect v8_ prefix from their names. Backports commit 4771cd01daaccb2a8929fa04c88c608e378cf814 from qemu
2018-02-13 13:15:53 +00:00
define_arm_cp_regs(cpu, el2_cp_reginfo);
target-arm: Add extended RVBAR support Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers point to the same location and only the highest EL version exists at any one time. Backports commit be8e8128595b41b9f609c1507e67d121e65e7173 from qemu
2018-02-12 15:31:23 +00:00
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3)) {
ARMCPRegInfo rvbar = {
"RVBAR_EL2", 0,12,0, 3,4,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL2_R, 0, NULL, cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
}
import
2015-08-21 07:04:50 +00:00
} else {
/* If EL2 is missing but higher ELs are enabled, we need to
* register the no_el2 reginfos.
*/
if (arm_feature(env, ARM_FEATURE_EL3)) {
target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arrays The ARMCPRegInfo arrays v8_el3_no_el2_cp_reginfo and v8_el2_cp_reginfo are actually used on non-v8 CPUs as well. Remove the incorrect v8_ prefix from their names. Backports commit 4771cd01daaccb2a8929fa04c88c608e378cf814 from qemu
2018-02-13 13:15:53 +00:00
define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
import
2015-08-21 07:04:50 +00:00
}
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
target-arm: move AArch32 SCR into security reglist Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving AArch32 SCR into Security Extension register group. Backports commit 0f1a3b2470d798ad5335eb9d6236f02ff64e31a8 from qemu
2018-02-11 23:48:06 +00:00
define_arm_cp_regs(cpu, el3_cp_reginfo);
target-arm: Add extended RVBAR support Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers point to the same location and only the highest EL version exists at any one time. Backports commit be8e8128595b41b9f609c1507e67d121e65e7173 from qemu
2018-02-12 15:31:23 +00:00
ARMCPRegInfo rvbar = {
"RVBAR_EL3", 0,12,0, 3,6,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL3_R, 0, NULL, cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
import
2015-08-21 07:04:50 +00:00
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
target-arm: Add registers for PMSAv7 Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Backports commit 6cb0b013a1fa421cdfb83257cd33f855cc90649a from qemu
2018-02-13 21:06:06 +00:00
if (arm_feature(env, ARM_FEATURE_V6)) {
/* PMSAv6 not implemented */
assert(arm_feature(env, ARM_FEATURE_V7));
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
} else {
define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
}
import
2015-08-21 07:04:50 +00:00
} else {
arm: helper: Factor out CP regs common to [pv]msa V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Backports commit 8e5d75c950a1241f6e1243c37f28cd58f68fedc9 from qemu
2018-02-13 19:39:32 +00:00
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
import
2015-08-21 07:04:50 +00:00
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_VAPA)) {
define_arm_cp_regs(cpu, vapa_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
define_arm_cp_regs(cpu, omap_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
define_arm_cp_regs(cpu, strongarm_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
define_arm_cp_regs(cpu, xscale_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_LPAE)) {
define_arm_cp_regs(cpu, lpae_cp_reginfo);
}
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
* be read-only (ie write causes UNDEF exception).
*/
{
ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
/* Pre-v8 MIDR space.
* Note that the MIDR isn't a simple constant register because
* of the TI925 behaviour where writes to another register can
* cause the MIDR value to change.
*
* Unimplemented registers in the c15 0 0 0 space default to
* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
* and friends override accordingly.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MIDR", 15,0,0, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_OVERRIDE, PL1_R, 0, NULL, cpu->midr, offsetof(CPUARMState, cp15.c0_cpuid), {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,arm_cp_write_ignore, NULL,raw_write, },
import
2015-08-21 07:04:50 +00:00
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DUMMY",
15,0,3, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DUMMY",
15,0,4, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DUMMY",
15,0,5, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DUMMY",
15,0,6, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "DUMMY",
15,0,7, 0,0,CP_ANY, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "MIDR_EL1", 0,0,0, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->midr },
target-arm: add AArch32 MIDR aliases in ARMv8 According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Backports commit ac00c79ff6635ae9fd732ff357ada0d05e795500 from qemu
2018-02-13 19:27:51 +00:00
/* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
{ "MIDR", 15,0,0, 0,0,4, 0, ARM_CP_ALIAS | ARM_CP_CONST,
PL1_R, 0, NULL, cpu->midr },
{ "MIDR", 15,0,0, 0,0,7, 0, ARM_CP_ALIAS | ARM_CP_CONST,
PL1_R, 0, NULL, cpu->midr },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "REVIDR_EL1", 0,0,0, 3,0,6, ARM_CP_STATE_BOTH,
target-arm: Fix REVIDR reset value According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57. Backports commit 13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932 from qemu
2018-02-13 19:22:43 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->revidr },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CTR", 15,0,0, 0,0,1, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->ctr },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CTR_EL0", 0,0,0, 3,3,1, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL0_R, 0, NULL, cpu->ctr, 0, {0, 0},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
ctr_el0_access, },
import
2015-08-21 07:04:50 +00:00
/* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "TCMTR", 15,0,0, 0,0,2, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, 0 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
arm: Do not define TLBTR in PMSA systems If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Backports commit 8085ce63c5967d200f1241b6c0a189371993c5df from qemu
2018-02-13 19:35:11 +00:00
ARMCPRegInfo id_tlbtr_reginfo = {
"TLBTR", 15,0,0, 0,0,3, 0,
ARM_CP_CONST, PL1_R, 0, NULL, 0,
};
target-arm/helper.c: define MPUIR register Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Backports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu
2018-02-13 20:35:04 +00:00
/* MPUIR is specific to PMSA V6+ */
ARMCPRegInfo id_mpuir_reginfo = {
"MPUIR", 15,0,0, 0,0,4, 0,ARM_CP_CONST,
PL1_R, 0, NULL, cpu->pmsav7_dregion << 8
};
import
2015-08-21 07:04:50 +00:00
ARMCPRegInfo crn0_wi_reginfo = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"CRN0_WI", 15,0,CP_ANY, 0,CP_ANY,CP_ANY, 0,
ARM_CP_NOP | ARM_CP_OVERRIDE, PL1_W,
import
2015-08-21 07:04:50 +00:00
};
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
arm_feature(env, ARM_FEATURE_STRONGARM)) {
ARMCPRegInfo *r;
/* Register the blanket "writes ignored" value first to cover the
* whole space. Then update the specific ID registers to allow write
* access, so that they ignore writes rather than causing them to
* UNDEF.
*/
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
for (r = id_pre_v8_midr_cp_reginfo;
r->type != ARM_CP_SENTINEL; r++) {
r->access = PL1_RW;
}
for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
r->access = PL1_RW;
}
arm: Do not define TLBTR in PMSA systems If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Backports commit 8085ce63c5967d200f1241b6c0a189371993c5df from qemu
2018-02-13 19:35:11 +00:00
id_tlbtr_reginfo.access = PL1_RW;
target-arm/helper.c: define MPUIR register Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Backports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu
2018-02-13 20:35:04 +00:00
id_tlbtr_reginfo.access = PL1_RW;
import
2015-08-21 07:04:50 +00:00
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
} else {
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
}
define_arm_cp_regs(cpu, id_cp_reginfo);
arm: Do not define TLBTR in PMSA systems If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Backports commit 8085ce63c5967d200f1241b6c0a189371993c5df from qemu
2018-02-13 19:35:11 +00:00
if (!arm_feature(env, ARM_FEATURE_MPU)) {
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
target-arm/helper.c: define MPUIR register Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Backports commit 3281af8114c6b8ead02f08b58e3c36895c1ea047 from qemu
2018-02-13 20:35:04 +00:00
} else if (arm_feature(env, ARM_FEATURE_V7)) {
define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
arm: Do not define TLBTR in PMSA systems If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Backports commit 8085ce63c5967d200f1241b6c0a189371993c5df from qemu
2018-02-13 19:35:11 +00:00
}
import
2015-08-21 07:04:50 +00:00
}
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
define_arm_cp_regs(cpu, mpidr_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
ARMCPRegInfo auxcr = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"ACTLR_EL1", 0,1,0, 3,0,1, ARM_CP_STATE_BOTH,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_RW, 0, NULL, cpu->reset_auxcr
import
2015-08-21 07:04:50 +00:00
};
define_one_arm_cp_reg(cpu, &auxcr);
}
if (arm_feature(env, ARM_FEATURE_CBAR)) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
/* 32 bit view is [31:18] 0...0 [43:32]. */
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
| extract64(cpu->reset_cbar, 32, 12);
ARMCPRegInfo cbar_reginfo[] = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CBAR", 15,15,0, 0,4,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cpu->reset_cbar },
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
{ "CBAR_EL1", 0,15,3, 3,1,0, ARM_CP_STATE_AA64,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
ARM_CP_CONST, PL1_R, 0, NULL, cbar32 },
import
2015-08-21 07:04:50 +00:00
REGINFO_SENTINEL
};
/* We don't implement a r/w 64 bit CBAR currently */
assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
define_arm_cp_regs(cpu, cbar_reginfo);
} else {
ARMCPRegInfo cbar = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"CBAR", 15,15,0, 0,4,0, 0,
target-arm: add CPREG secure state support Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Backports commit c3e302606253a17568dc3ef30238f102468f7ee1 from qemu
2018-02-11 22:52:55 +00:00
0, PL1_R|PL3_W, 0, NULL, cpu->reset_cbar, offsetof(CPUARMState, cp15.c15_config_base_address)
import
2015-08-21 07:04:50 +00:00
};
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
cbar.access = PL1_R;
cbar.fieldoffset = 0;
cbar.type = ARM_CP_CONST;
}
define_one_arm_cp_reg(cpu, &cbar);
}
}
Backport the VBAR feature flag Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn
2018-02-02 13:23:47 +00:00
if (arm_feature(env, ARM_FEATURE_VBAR)) {
ARMCPRegInfo vbar_cp_reginfo[] = {
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: make VBAR banked When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Backports commit fb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b from qemu
2018-02-12 14:40:05 +00:00
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) },
Backport the VBAR feature flag Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn
2018-02-02 13:23:47 +00:00
NULL, NULL, vbar_write, },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vbar_cp_reginfo);
}
import
2015-08-21 07:04:50 +00:00
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
"SCTLR", 0,1,0, 3,0,0, ARM_CP_STATE_BOTH,
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
0, PL1_RW, 0, NULL, cpu->reset_sctlr, 0,
{offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns)},
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
NULL, NULL,sctlr_write, NULL,raw_write,
import
2015-08-21 07:04:50 +00:00
};
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
/* Normally we would always end the TB on an SCTLR write, but Linux
* arch/arm/mach-pxa/sleep.S expects two instructions following
* an MMU enable to execute from cache. Imitate this behaviour.
*/
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
}
define_one_arm_cp_reg(cpu, &sctlr);
}
}
ARMCPU *cpu_arm_init(struct uc_struct *uc, const char *cpu_model)
{
return ARM_CPU(uc, cpu_generic_init(uc, TYPE_ARM_CPU, cpu_model));
}
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
{
#if 0
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
aarch64_fpu_gdb_set_reg,
34, "aarch64-fpu.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP3)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0);
} else if (arm_feature(env, ARM_FEATURE_VFP)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
#endif
}
/* Sort alphabetically by type name, except for "any". */
#if 0
static void arm_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
CPUListState *s = user_data;
const char *typename;
char *name;
typename = object_class_get_name(oc);
name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
(*s->cpu_fprintf)(s->file, " %s\n",
name);
revert to use of g_free to make future qemu integrations easier (#695) * revert to use of g_free to make future qemu integrations easier * bracing
2016-12-21 14:28:36 +00:00
g_free(name);
import
2015-08-21 07:04:50 +00:00
}
#endif
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
#if 0
CPUListState s = {
.file = f,
.cpu_fprintf = cpu_fprintf,
};
GSList *list;
list = object_class_get_list(TYPE_ARM_CPU, false);
list = g_slist_sort(list, arm_cpu_list_compare);
(*cpu_fprintf)(f, "Available CPUs:\n");
g_slist_foreach(list, arm_cpu_list_entry, &s);
g_slist_free(list);
#ifdef CONFIG_KVM
/* The 'host' CPU type is dynamically registered only if KVM is
* enabled, so we have to special-case it here:
*/
(*cpu_fprintf)(f, " host (only available in KVM mode)\n");
#endif
#endif
}
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
target-arm: add secure state bit to CPREG hash Added additional NS-bit to CPREG hash encoding. Updated hash lookup locations to specify hash bit currently set to non-secure. Backports commit 51a79b039728277e35fd19f7a7b4bc6cb323697f from qemu
2018-02-11 23:32:39 +00:00
void *opaque, int state, int secstate,
import
2015-08-21 07:04:50 +00:00
int crm, int opc1, int opc2)
{
/* Private utility function for define_one_arm_cp_reg_with_opaque():
* add a single reginfo struct to the hash table.
*/
uint32_t *key = g_new(uint32_t, 1);
ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
/* Reset the secure state to the specific incoming state. This is
* necessary as the register may have been defined with both states.
*/
r2->secure = secstate;
if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
/* Register is banked (using both entries in array).
* Overwriting fieldoffset as the array is only used to define
* banked registers but later only fieldoffset is used.
import
2015-08-21 07:04:50 +00:00
*/
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
r2->fieldoffset = r->bank_fieldoffsets[ns];
}
if (state == ARM_CP_STATE_AA32) {
if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
/* If the register is banked then we don't need to migrate or
* reset the 32-bit instance in certain cases:
*
* 1) If the register has both 32-bit and 64-bit instances then we
* can count on the 64-bit instance taking care of the
* non-secure bank.
* 2) If ARMv8 is enabled then we can count on a 64-bit version
* taking care of the secure bank. This requires that separate
* 32 and 64-bit definitions are provided.
*/
if ((r->state == ARM_CP_STATE_BOTH && ns) ||
(arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
r2->type |= ARM_CP_ALIAS;
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
}
} else if ((secstate != r->secure) && !ns) {
/* The register is not banked so we only want to allow migration of
* the non-secure instance.
*/
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
r2->type |= ARM_CP_ALIAS;
import
2015-08-21 07:04:50 +00:00
}
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
if (r->state == ARM_CP_STATE_BOTH) {
/* We assume it is a cp15 register if the .cp field is left unset.
*/
if (r2->cp == 0) {
r2->cp = 15;
}
import
2015-08-21 07:04:50 +00:00
#ifdef HOST_WORDS_BIGENDIAN
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
if (r2->fieldoffset) {
r2->fieldoffset += sizeof(uint32_t);
}
import
2015-08-21 07:04:50 +00:00
#endif
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
}
import
2015-08-21 07:04:50 +00:00
}
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
import
2015-08-21 07:04:50 +00:00
if (state == ARM_CP_STATE_AA64) {
/* To allow abbreviation of ARMCPRegInfo
* definitions, we treat cp == 0 as equivalent to
* the value for "standard guest-visible sysreg".
* STATE_BOTH definitions are also always "standard
* sysreg" in their AArch64 view (the .cp value may
* be non-zero for the benefit of the AArch32 view).
*/
if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
r2->cp = CP_REG_ARM64_SYSREG_CP;
}
*key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
r2->opc0, opc1, opc2);
} else {
target-arm: add secure state bit to CPREG hash Added additional NS-bit to CPREG hash encoding. Updated hash lookup locations to specify hash bit currently set to non-secure. Backports commit 51a79b039728277e35fd19f7a7b4bc6cb323697f from qemu
2018-02-11 23:32:39 +00:00
*key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
import
2015-08-21 07:04:50 +00:00
}
if (opaque) {
r2->opaque = opaque;
}
/* reginfo passed to helpers is correct for the actual access,
* and is never ARM_CP_STATE_BOTH:
*/
r2->state = state;
/* Make sure reginfo passed to helpers for wildcarded regs
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
*/
r2->crm = crm;
r2->opc1 = opc1;
r2->opc2 = opc2;
/* By convention, for wildcarded registers only the first
* entry is used for migration; the others are marked as
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
* ALIAS so we don't try to transfer the register
import
2015-08-21 07:04:50 +00:00
* multiple times. Special registers (ie NOP/WFI) are
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
* never migratable and not even raw-accessible.
import
2015-08-21 07:04:50 +00:00
*/
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
if ((r->type & ARM_CP_SPECIAL)) {
r2->type |= ARM_CP_NO_RAW;
}
if (((r->crm == CP_ANY) && crm != 0) ||
import
2015-08-21 07:04:50 +00:00
((r->opc1 == CP_ANY) && opc1 != 0) ||
((r->opc2 == CP_ANY) && opc2 != 0)) {
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW We currently mark ARM coprocessor/system register definitions with the flag ARM_CP_NO_MIGRATE for two different reasons: 1) register is an alias on to state that's also visible via some other register, and that other register is the one responsible for migrating the state 2) register is not actually state at all (for instance the TLB or cache maintenance operation "registers") and it makes no sense to attempt to migrate it or otherwise access the raw state This works fine for identifying which registers should be ignored when performing migration, but we also use the same functions for synchronizing system register state between QEMU and the kernel when using KVM. In this case we don't want to try to sync state into registers in category 2, but we do want to sync into registers in category 1, because the kernel might have picked a different one of the aliases as its choice for which one to expose for migration. (In particular, on 32 bit hosts the kernel will expose the state in the AArch32 version of the register, but TCG's convention is to mark the AArch64 version as the version to migrate, even if the CPU being emulated happens to be 32 bit, so almost all system registers will hit this issue now that we've added AArch64 system emulation.) Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW) corresponding to the two different reasons we might not want to migrate a register. When setting up the TCG list of registers to migrate we honour both flags; when populating the list from KVM, only ignore registers which are NO_RAW. Backports commit 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0 from qemu
2018-02-12 15:58:13 +00:00
r2->type |= ARM_CP_ALIAS;
import
2015-08-21 07:04:50 +00:00
}
target-arm: Add checks that cpreg raw accesses are handled Add assertion checking when cpreg structures are registered that they either forbid raw-access attempts or at least make an attempt at handling them. Also add an assert in the raw-accessor-of-last-resort, to avoid silently doing a read or write from offset zero, which is actually AArch32 CPU register r0. Backports commit 375421ccaeebae8212eb8f9a36835ad4d9dc60a8 from qemu
2018-02-12 16:01:36 +00:00
/* Check that raw accesses are either forbidden or handled. Note that
* we can't assert this earlier because the setup of fieldoffset for
* banked registers has to be done first.
*/
if (!(r2->type & ARM_CP_NO_RAW)) {
assert(!raw_accessors_invalid(r2));
}
import
2015-08-21 07:04:50 +00:00
/* Overriding of an existing definition must be explicitly
* requested.
*/
if (!(r->type & ARM_CP_OVERRIDE)) {
ARMCPRegInfo *oldreg;
oldreg = g_hash_table_lookup(cpu->cp_regs, key);
if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
fprintf(stderr, "Register redefined: cp=%d %d bit "
"crn=%d crm=%d opc1=%d opc2=%d, "
"was %s, now %s\n", r2->cp, 32 + 32 * is64,
r2->crn, r2->crm, r2->opc1, r2->opc2,
oldreg->name, r2->name);
g_assert_not_reached();
}
}
g_hash_table_insert(cpu->cp_regs, key, r2);
}
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
const ARMCPRegInfo *r, void *opaque)
{
/* Define implementations of coprocessor registers.
* We store these in a hashtable because typically
* there are less than 150 registers in a space which
* is 16*16*16*8*8 = 262144 in size.
* Wildcarding is supported for the crm, opc1 and opc2 fields.
* If a register is defined twice then the second definition is
* used, so this can be used to define some generic registers and
* then override them with implementation specific variations.
* At least one of the original and the second definition should
* include ARM_CP_OVERRIDE in its type bits -- this is just a guard
* against accidental use.
*
* The state field defines whether the register is to be
* visible in the AArch32 or AArch64 execution state. If the
* state is set to ARM_CP_STATE_BOTH then we synthesise a
* reginfo structure for the AArch32 view, which sees the lower
* 32 bits of the 64 bit register.
*
* Only registers visible in AArch64 may set r->opc0; opc0 cannot
* be wildcarded. AArch64 registers are always considered to be 64
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
* the register, if any.
*/
int crm, opc1, opc2, state;
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
/* 64 bit registers have only CRm and Opc1 fields */
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
/* op0 only exists in the AArch64 encodings */
assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
/* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
/* The AArch64 pseudocode CheckSystemAccess() specifies that op1
* encodes a minimum access level for the register. We roll this
* runtime check into our general permission check code, so check
* here that the reginfo's specified permissions are strict enough
* to encompass the generic architectural permission check.
*/
if (r->state != ARM_CP_STATE_AA32) {
int mask = 0;
switch (r->opc1) {
case 0: case 1: case 2:
/* min_EL EL1 */
mask = PL1_RW;
break;
case 3:
/* min_EL EL0 */
mask = PL0_RW;
break;
case 4:
/* min_EL EL2 */
mask = PL2_RW;
break;
case 5:
/* unallocated encoding, so not possible */
assert(false);
break;
case 6:
/* min_EL EL3 */
mask = PL3_RW;
break;
case 7:
/* min_EL EL1, secure mode only (we don't check the latter) */
mask = PL1_RW;
break;
default:
/* broken reginfo with out-of-range opc1 */
assert(false);
break;
}
/* assert our permissions are not too lax (stricter is fine) */
assert((r->access & ~mask) == 0);
}
/* Check that the register definition has enough info to handle
* reads and writes if they are permitted.
*/
if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
if (r->access & PL3_R) {
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
assert((r->fieldoffset ||
(r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
r->readfn);
import
2015-08-21 07:04:50 +00:00
}
if (r->access & PL3_W) {
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
assert((r->fieldoffset ||
(r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
r->writefn);
import
2015-08-21 07:04:50 +00:00
}
}
/* Bad type field probably means missing sentinel at end of reg list */
assert(cptype_valid(r->type));
for (crm = crmmin; crm <= crmmax; crm++) {
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
for (state = ARM_CP_STATE_AA32;
state <= ARM_CP_STATE_AA64; state++) {
if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
continue;
}
target-arm: insert AArch32 cpregs twice into hashtable Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Backports commit 3f3c82a57d128aa3ec823aa8032867c3a6e2e795 from qemu
2018-02-11 23:40:52 +00:00
if (state == ARM_CP_STATE_AA32) {
/* Under AArch32 CP registers can be common
* (same for secure and non-secure world) or banked.
*/
switch (r->secure) {
case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
add_cpreg_to_hashtable(cpu, r, opaque, state,
r->secure, crm, opc1, opc2);
break;
default:
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_S,
crm, opc1, opc2);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2);
break;
}
} else {
/* AArch64 registers get mapped to non-secure instance
* of AArch32 */
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2);
}
import
2015-08-21 07:04:50 +00:00
}
}
}
}
}
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
const ARMCPRegInfo *regs, void *opaque)
{
/* Define a whole list of registers */
const ARMCPRegInfo *r;
for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
}
}
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
{
return g_hash_table_lookup(cpregs, &encoded_cp);
}
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Helper coprocessor write function for write-ignore registers */
}
uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Helper coprocessor write function for read-as-zero registers */
return 0;
}
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
{
/* Helper coprocessor reset function for do-nothing-on-reset registers */
}
static int bad_mode_switch(CPUARMState *env, int mode)
{
/* Return true if it is not valid for us to switch to
* this CPU mode (ie all the UNPREDICTABLE cases in
* the ARM ARM CPSRWriteByInstr pseudocode).
*/
switch (mode) {
case ARM_CPU_MODE_USR:
case ARM_CPU_MODE_SYS:
case ARM_CPU_MODE_SVC:
case ARM_CPU_MODE_ABT:
case ARM_CPU_MODE_UND:
case ARM_CPU_MODE_IRQ:
case ARM_CPU_MODE_FIQ:
return 0;
case ARM_CPU_MODE_MON:
return !arm_is_secure(env);
default:
return 1;
}
}
uint32_t cpsr_read(CPUARMState *env)
{
int ZF;
ZF = (env->ZF == 0);
return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
| (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
| ((env->condexec_bits & 0xfc) << 8)
| (env->GE << 16) | (env->daif & CPSR_AIF);
}
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits are used to control whether the CPSR masking bits can be adjusted from non-secure state. Backports commit 6e8801f9dea9e10449f4fd7d85dbe8cab708a686 from qemu
2018-02-12 00:29:59 +00:00
uint32_t changed_daif;
import
2015-08-21 07:04:50 +00:00
if (mask & CPSR_NZCV) {
env->ZF = (~val) & CPSR_Z;
env->NF = val;
env->CF = (val >> 29) & 1;
env->VF = (val << 3) & 0x80000000;
}
if (mask & CPSR_Q)
env->QF = ((val & CPSR_Q) != 0);
if (mask & CPSR_T)
env->thumb = ((val & CPSR_T) != 0);
if (mask & CPSR_IT_0_1) {
env->condexec_bits &= ~3;
env->condexec_bits |= (val >> 25) & 3;
}
if (mask & CPSR_IT_2_7) {
env->condexec_bits &= 3;
env->condexec_bits |= (val >> 8) & 0xfc;
}
if (mask & CPSR_GE) {
env->GE = (val >> 16) & 0xf;
}
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits are used to control whether the CPSR masking bits can be adjusted from non-secure state. Backports commit 6e8801f9dea9e10449f4fd7d85dbe8cab708a686 from qemu
2018-02-12 00:29:59 +00:00
/* In a V7 implementation that includes the security extensions but does
* not include Virtualization Extensions the SCR.FW and SCR.AW bits control
* whether non-secure software is allowed to change the CPSR_F and CPSR_A
* bits respectively.
*
* In a V8 implementation, it is permitted for privileged software to
* change the CPSR A/F bits regardless of the SCR.AW/FW bits.
*/
if (!arm_feature(env, ARM_FEATURE_V8) &&
arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2) &&
!arm_is_secure(env)) {
changed_daif = (env->daif ^ val) & mask;
if (changed_daif & CPSR_A) {
/* Check to see if we are allowed to change the masking of async
* abort exceptions from a non-secure state.
*/
if (!(env->cp15.scr_el3 & SCR_AW)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Ignoring attempt to switch CPSR_A flag from "
"non-secure world with SCR.AW bit clear\n");
mask &= ~CPSR_A;
}
}
if (changed_daif & CPSR_F) {
/* Check to see if we are allowed to change the masking of FIQ
* exceptions from a non-secure state.
*/
if (!(env->cp15.scr_el3 & SCR_FW)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Ignoring attempt to switch CPSR_F flag from "
"non-secure world with SCR.FW bit clear\n");
mask &= ~CPSR_F;
}
/* Check whether non-maskable FIQ (NMFI) support is enabled.
* If this bit is set software is not allowed to mask
* FIQs, but is allowed to set CPSR_F to 0.
*/
if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
(val & CPSR_F)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Ignoring attempt to enable CPSR_F flag "
"(non-maskable FIQ [NMFI] support enabled)\n");
mask &= ~CPSR_F;
}
}
}
import
2015-08-21 07:04:50 +00:00
env->daif &= ~(CPSR_AIF & mask);
env->daif |= val & CPSR_AIF & mask;
if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
if (bad_mode_switch(env, val & CPSR_M)) {
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
* We choose to ignore the attempt and leave the CPSR M field
* untouched.
*/
mask &= ~CPSR_M;
} else {
switch_mode(env, val & CPSR_M);
}
}
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}
/* Sign/zero extend */
uint32_t HELPER(sxtb16)(uint32_t x)
{
uint32_t res;
res = (uint16_t)(int8_t)x;
res |= (uint32_t)(int8_t)(x >> 16) << 16;
return res;
}
uint32_t HELPER(uxtb16)(uint32_t x)
{
uint32_t res;
res = (uint16_t)(uint8_t)x;
res |= (uint32_t)(uint8_t)(x >> 16) << 16;
return res;
}
uint32_t HELPER(clz_arm)(uint32_t x)
{
return clz32(x);
}
int32_t HELPER(sdiv)(int32_t num, int32_t den)
{
if (den == 0)
return 0;
if (num == INT_MIN && den == -1)
return INT_MIN;
return num / den;
}
uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
{
if (den == 0)
return 0;
return num / den;
}
uint32_t HELPER(rbit)(uint32_t x)
{
target-arm: Use new revbit functions Backports commit 42fedbca8f5b54324ed89be3484d4a3dc9946387 from qemu
2018-02-11 06:56:37 +00:00
return revbit32(x);
import
2015-08-21 07:04:50 +00:00
}
#if defined(CONFIG_USER_ONLY)
/* These should probably raise undefined insn exceptions. */
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
ARMCPU *cpu = arm_env_get_cpu(env);
cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
}
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
ARMCPU *cpu = arm_env_get_cpu(env);
cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
return 0;
}
void switch_mode(CPUARMState *env, int mode)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (mode != ARM_CPU_MODE_USR) {
cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
}
}
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
ARMCPU *cpu = arm_env_get_cpu(env);
cpu_abort(CPU(cpu), "banked r13 write\n");
}
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
{
ARMCPU *cpu = arm_env_get_cpu(env);
cpu_abort(CPU(cpu), "banked r13 read\n");
return 0;
}
target-arm: Update interrupt handling to use target EL Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Backports commit 012a906b19e99b126403ff4a257617dab9b34163 from qemu
2018-02-13 03:40:02 +00:00
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure)
import
2015-08-21 07:04:50 +00:00
{
return 1;
}
target-arm: Add 32/64-bit register sync Add AArch32 to AArch64 register sychronization functions. Replace manual register synchronization with new functions in aarch64_cpu_do_interrupt() and HELPER(exception_return)(). Backports commit ce02049dbf1828b4bc77d921b108a9d84246e5aa from qemu
2018-02-12 19:56:55 +00:00
void aarch64_sync_64_to_32(CPUARMState *env)
{
g_assert_not_reached();
}
import
2015-08-21 07:04:50 +00:00
#else
/* Map CPU modes onto saved register banks. */
int bank_number(int mode)
{
switch (mode) {
default:
case ARM_CPU_MODE_USR:
case ARM_CPU_MODE_SYS:
return 0;
case ARM_CPU_MODE_SVC:
return 1;
case ARM_CPU_MODE_ABT:
return 2;
case ARM_CPU_MODE_UND:
return 3;
case ARM_CPU_MODE_IRQ:
return 4;
case ARM_CPU_MODE_FIQ:
return 5;
case ARM_CPU_MODE_HYP:
return 6;
case ARM_CPU_MODE_MON:
return 7;
}
//hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
}
void switch_mode(CPUARMState *env, int mode)
{
int old_mode;
int i;
old_mode = env->uncached_cpsr & CPSR_M;
if (mode == old_mode)
return;
if (old_mode == ARM_CPU_MODE_FIQ) {
memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
} else if (mode == ARM_CPU_MODE_FIQ) {
memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
}
i = bank_number(old_mode);
env->banked_r13[i] = env->regs[13];
env->banked_r14[i] = env->regs[14];
env->banked_spsr[i] = env->spsr;
i = bank_number(mode);
env->regs[13] = env->banked_r13[i];
env->regs[14] = env->banked_r14[i];
env->spsr = env->banked_spsr[i];
}
target-arm: add async excp target_el function Adds a dedicated function and a lookup table for determining the target exception level of IRQ and FIQ exceptions. The lookup table is taken from the ARMv7 and ARMv8 specification exception routing tables. Backports commit 0eeb17d618361a0f4faddc160e33598b23da6dd5 from qemu
2018-02-11 22:42:00 +00:00
/* Physical Interrupt Target EL Lookup Table
*
* [ From ARM ARM section G1.13.4 (Table G1-15) ]
*
* The below multi-dimensional table is used for looking up the target
* exception level given numerous condition criteria. Specifically, the
* target EL is based on SCR and HCR routing controls as well as the
* currently executing EL and secure state.
*
* Dimensions:
* target_el_table[2][2][2][2][2][4]
* | | | | | +--- Current EL
* | | | | +------ Non-secure(0)/Secure(1)
* | | | +--------- HCR mask override
* | | +------------ SCR exec state control
* | +--------------- SCR mask override
* +------------------ 32-bit(0)/64-bit(1) EL3
*
* The table values are as such:
* 0-3 = EL0-EL3
* -1 = Cannot occur
*
* The ARM ARM target EL table includes entries indicating that an "exception
* is not taken". The two cases where this is applicable are:
* 1) An exception is taken from EL3 but the SCR does not have the exception
* routed to EL3.
* 2) An exception is taken from EL2 but the HCR does not have the exception
* routed to EL2.
* In these two cases, the below table contain a target of EL1. This value is
* returned as it is expected that the consumer of the table data will check
* for "target EL >= current EL" to ensure the exception is not taken.
*
* SCR HCR
* 64 EA AMO From
* BIT IRQ IMO Non-secure Secure
* EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
*/
const int8_t target_el_table[2][2][2][2][2][4] = {
{{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
{/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
{{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
{/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
{{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
{/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
{{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
{/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
{{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
{/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
{{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
{/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
{{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
{/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
{{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
{/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
};
/*
* Determine the target EL for physical exceptions
*/
target-arm: Update interrupt handling to use target EL Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Backports commit 012a906b19e99b126403ff4a257617dab9b34163 from qemu
2018-02-13 03:40:02 +00:00
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure)
target-arm: add async excp target_el function Adds a dedicated function and a lookup table for determining the target exception level of IRQ and FIQ exceptions. The lookup table is taken from the ARMv7 and ARMv8 specification exception routing tables. Backports commit 0eeb17d618361a0f4faddc160e33598b23da6dd5 from qemu
2018-02-11 22:42:00 +00:00
{
CPUARMState *env = cs->env_ptr;
int rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
int scr;
int hcr;
int target_el;
int is64 = arm_el_is_aa64(env, 3);
switch (excp_idx) {
case EXCP_IRQ:
scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
break;
case EXCP_FIQ:
scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
break;
default:
scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
break;
};
/* If HCR.TGE is set then HCR is treated as being 1 */
hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
/* Perform a table-lookup for the target EL given the current state */
target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
assert(target_el > 0);
return target_el;
import
2015-08-21 07:04:50 +00:00
}
static void v7m_push(CPUARMState *env, uint32_t val)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
env->regs[13] -= 4;
stl_phys(cs->as, env->regs[13], val);
}
static uint32_t v7m_pop(CPUARMState *env)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
uint32_t val;
val = ldl_phys(cs->as, env->regs[13]);
env->regs[13] += 4;
return val;
}
/* Switch to V7M main or process stack pointer. */
static void switch_v7m_sp(CPUARMState *env, int process)
{
uint32_t tmp;
if (env->v7m.current_sp != process) {
tmp = env->v7m.other_sp;
env->v7m.other_sp = env->regs[13];
env->regs[13] = tmp;
env->v7m.current_sp = process;
}
}
static void do_v7m_exception_exit(CPUARMState *env)
{
uint32_t type;
uint32_t xpsr;
type = env->regs[15];
//if (env->v7m.exception != 0)
// armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
/* Switch to the target stack. */
switch_v7m_sp(env, (type & 4) != 0);
/* Pop registers. */
env->regs[0] = v7m_pop(env);
env->regs[1] = v7m_pop(env);
env->regs[2] = v7m_pop(env);
env->regs[3] = v7m_pop(env);
env->regs[12] = v7m_pop(env);
env->regs[14] = v7m_pop(env);
env->regs[15] = v7m_pop(env);
target-arm: Ignore low bit of PC in M-profile exception return For the ARM M-profile cores, exception return pops various registers including the PC from the stack. The architecture defines that if the lowest bit in the new PC value is set (ie the PC is not halfword aligned) then behaviour is UNPREDICTABLE. In practice hardware implementations seem to simply ignore the low bit, and some buggy RTOSes incorrectly rely on this. QEMU's behaviour was architecturally permitted, but bringing QEMU into line with the hardware behaviour allows more guest code to run. We log the situation as a guest error. This was reported as LP:1428657. Backports commit fcf83ab103dce6d2951f24f48e30820e7dbb3622 from qemu
2018-02-12 21:17:37 +00:00
if (env->regs[15] & 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"M profile return from interrupt with misaligned "
"PC is UNPREDICTABLE\n");
/* Actual hardware seems to ignore the lsbit, and there are several
* RTOSes out there which incorrectly assume the r15 in the stack
* frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
*/
env->regs[15] &= ~1U;
}
import
2015-08-21 07:04:50 +00:00
xpsr = v7m_pop(env);
xpsr_write(env, xpsr, 0xfffffdff);
/* Undo stack alignment. */
if (xpsr & 0x200)
env->regs[13] |= 4;
/* ??? The exception return type specifies Thread/Handler mode. However
this is also implied by the xPSR value. Not sure what to do
if there is a mismatch. */
/* ??? Likewise for mismatches between the CONTROL register and the stack
pointer. */
}
void arm_v7m_cpu_do_interrupt(CPUState *cs)
{
CPUARMState *env = cs->env_ptr;
uint32_t xpsr = xpsr_read(env);
uint32_t lr;
uint32_t addr;
arm_log_exception(cs->exception_index);
lr = 0xfffffff1;
if (env->v7m.current_sp)
lr |= 4;
if (env->v7m.exception == 0)
lr |= 8;
/* For exceptions we just mark as pending on the NVIC, and let that
handle it. */
/* TODO: Need to escalate if the current priority is higher than the
one we're raising. */
switch (cs->exception_index) {
case EXCP_UDEF:
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
return;
case EXCP_SWI:
/* The PC already points to the next instruction. */
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
return;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
/* TODO: if we implemented the MPU registers, this is where we
* should set the MMFAR, etc from exception.fsr and exception.vaddress.
*/
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
return;
case EXCP_BKPT:
#if 0
if (semihosting_enabled) {
int nr;
nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (nr == 0xab) {
env->regs[15] += 2;
env->regs[0] = do_arm_semihosting(env);
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
return;
}
}
#endif
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
return;
case EXCP_IRQ:
//env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
break;
case EXCP_EXCEPTION_EXIT:
do_v7m_exception_exit(env);
return;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
/* Align stack pointer. */
/* ??? Should only do this if Configuration Control Register
STACKALIGN bit is set. */
if (env->regs[13] & 4) {
env->regs[13] -= 4;
xpsr |= 0x200;
}
/* Switch to the handler mode. */
v7m_push(env, xpsr);
v7m_push(env, env->regs[15]);
v7m_push(env, env->regs[14]);
v7m_push(env, env->regs[12]);
v7m_push(env, env->regs[3]);
v7m_push(env, env->regs[2]);
v7m_push(env, env->regs[1]);
v7m_push(env, env->regs[0]);
switch_v7m_sp(env, 0);
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
}
target-arm: Add 32/64-bit register sync Add AArch32 to AArch64 register sychronization functions. Replace manual register synchronization with new functions in aarch64_cpu_do_interrupt() and HELPER(exception_return)(). Backports commit ce02049dbf1828b4bc77d921b108a9d84246e5aa from qemu
2018-02-12 19:56:55 +00:00
/* Function used to synchronize QEMU's AArch64 register set with AArch32
* register set. This is necessary when switching between AArch32 and AArch64
* execution state.
*/
void aarch64_sync_32_to_64(CPUARMState *env)
{
int i;
uint32_t mode = env->uncached_cpsr & CPSR_M;
/* We can blanket copy R[0:7] to X[0:7] */
for (i = 0; i < 8; i++) {
env->xregs[i] = env->regs[i];
}
/* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
* Otherwise, they come from the banked user regs.
*/
if (mode == ARM_CPU_MODE_FIQ) {
for (i = 8; i < 13; i++) {
env->xregs[i] = env->usr_regs[i - 8];
}
} else {
for (i = 8; i < 13; i++) {
env->xregs[i] = env->regs[i];
}
}
/* Registers x13-x23 are the various mode SP and FP registers. Registers
* r13 and r14 are only copied if we are in that mode, otherwise we copy
* from the mode banked register.
*/
if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
env->xregs[13] = env->regs[13];
env->xregs[14] = env->regs[14];
} else {
env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
/* HYP is an exception in that it is copied from r14 */
if (mode == ARM_CPU_MODE_HYP) {
env->xregs[14] = env->regs[14];
} else {
env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
}
}
if (mode == ARM_CPU_MODE_HYP) {
env->xregs[15] = env->regs[13];
} else {
env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
}
if (mode == ARM_CPU_MODE_IRQ) {
env->xregs[16] = env->regs[13];
env->xregs[17] = env->regs[14];
} else {
env->xregs[16] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
env->xregs[17] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
}
if (mode == ARM_CPU_MODE_SVC) {
env->xregs[18] = env->regs[13];
env->xregs[19] = env->regs[14];
} else {
env->xregs[18] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
env->xregs[19] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
}
if (mode == ARM_CPU_MODE_ABT) {
env->xregs[20] = env->regs[13];
env->xregs[21] = env->regs[14];
} else {
env->xregs[20] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
env->xregs[21] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
}
if (mode == ARM_CPU_MODE_UND) {
env->xregs[22] = env->regs[13];
env->xregs[23] = env->regs[14];
} else {
env->xregs[22] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
env->xregs[23] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
}
/* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
* mode, then we can copy from r8-r14. Otherwise, we copy from the
* FIQ bank for r8-r14.
*/
if (mode == ARM_CPU_MODE_FIQ) {
for (i = 24; i < 31; i++) {
env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
}
} else {
for (i = 24; i < 29; i++) {
env->xregs[i] = env->fiq_regs[i - 24];
}
env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
}
env->pc = env->regs[15];
}
/* Function used to synchronize QEMU's AArch32 register set with AArch64
* register set. This is necessary when switching between AArch32 and AArch64
* execution state.
*/
void aarch64_sync_64_to_32(CPUARMState *env)
{
int i;
uint32_t mode = env->uncached_cpsr & CPSR_M;
/* We can blanket copy X[0:7] to R[0:7] */
for (i = 0; i < 8; i++) {
env->regs[i] = env->xregs[i];
}
/* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
* Otherwise, we copy x8-x12 into the banked user regs.
*/
if (mode == ARM_CPU_MODE_FIQ) {
for (i = 8; i < 13; i++) {
env->usr_regs[i - 8] = env->xregs[i];
}
} else {
for (i = 8; i < 13; i++) {
env->regs[i] = env->xregs[i];
}
}
/* Registers r13 & r14 depend on the current mode.
* If we are in a given mode, we copy the corresponding x registers to r13
* and r14. Otherwise, we copy the x register to the banked r13 and r14
* for the mode.
*/
if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
env->regs[13] = env->xregs[13];
env->regs[14] = env->xregs[14];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
/* HYP is an exception in that it does not have its own banked r14 but
* shares the USR r14
*/
if (mode == ARM_CPU_MODE_HYP) {
env->regs[14] = env->xregs[14];
} else {
env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
}
}
if (mode == ARM_CPU_MODE_HYP) {
env->regs[13] = env->xregs[15];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
}
if (mode == ARM_CPU_MODE_IRQ) {
env->regs[13] = env->xregs[16];
env->regs[14] = env->xregs[17];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
}
if (mode == ARM_CPU_MODE_SVC) {
env->regs[13] = env->xregs[18];
env->regs[14] = env->xregs[19];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
}
if (mode == ARM_CPU_MODE_ABT) {
env->regs[13] = env->xregs[20];
env->regs[14] = env->xregs[21];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
}
if (mode == ARM_CPU_MODE_UND) {
env->regs[13] = env->xregs[22];
env->regs[14] = env->xregs[23];
} else {
env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
}
/* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
* mode, then we can copy to r8-r14. Otherwise, we copy to the
* FIQ bank for r8-r14.
*/
if (mode == ARM_CPU_MODE_FIQ) {
for (i = 24; i < 31; i++) {
env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
}
} else {
for (i = 24; i < 29; i++) {
env->fiq_regs[i - 24] = env->xregs[i];
}
env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
}
env->regs[15] = env->pc;
}
import
2015-08-21 07:04:50 +00:00
/* Handle a CPU exception. */
void arm_cpu_do_interrupt(CPUState *cs)
{
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = ARM_CPU(env->uc, cs);
uint32_t addr;
uint32_t mask;
int new_mode;
uint32_t offset;
uint32_t moe;
assert(!IS_M(env));
arm_log_exception(cs->exception_index);
if (arm_is_psci_call(cpu, cs->exception_index)) {
arm_handle_psci_call(cpu);
qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
return;
}
/* If this is a debug exception we must update the DBGDSCR.MOE bits */
switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
case EC_BREAKPOINT:
case EC_BREAKPOINT_SAME_EL:
moe = 1;
break;
case EC_WATCHPOINT:
case EC_WATCHPOINT_SAME_EL:
moe = 10;
break;
case EC_AA32_BKPT:
moe = 3;
break;
case EC_VECTORCATCH:
moe = 5;
break;
default:
moe = 0;
break;
}
if (moe) {
env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
}
/* TODO: Vectored interrupt controller. */
switch (cs->exception_index) {
case EXCP_UDEF:
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
mask = CPSR_I;
if (env->thumb)
offset = 2;
else
offset = 4;
break;
case EXCP_SWI:
#if 0
if (semihosting_enabled) {
/* Check for semihosting interrupt. */
if (env->thumb) {
mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
& 0xff;
} else {
mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
& 0xffffff;
}
/* Only intercept calls from privileged modes, to provide some
semblance of security. */
if (((mask == 0x123456 && !env->thumb)
|| (mask == 0xab && env->thumb))
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
env->regs[0] = do_arm_semihosting(env);
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
return;
}
}
#endif
new_mode = ARM_CPU_MODE_SVC;
addr = 0x08;
mask = CPSR_I;
/* The PC already points to the next instruction. */
offset = 0;
break;
case EXCP_BKPT:
#if 0
/* See if this is a semihosting syscall. */
if (env->thumb && semihosting_enabled) {
mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
if (mask == 0xab
&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
env->regs[15] += 2;
env->regs[0] = do_arm_semihosting(env);
qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
return;
}
}
#endif
env->exception.fsr = 2;
/* Fall through to prefetch abort. */
case EXCP_PREFETCH_ABORT:
target-arm: make IFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Backports commit 88ca1c2d70523486a952065f3ed7b8fc823b5863 from qemu
2018-02-12 14:07:49 +00:00
A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
target-arm: make IFAR/DFAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Backports commit b848ce2b9cbd38da3f2530fd93dba76dba0621c0 from qemu
2018-02-12 14:17:49 +00:00
A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
import
2015-08-21 07:04:50 +00:00
qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
target-arm: make IFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Backports commit 88ca1c2d70523486a952065f3ed7b8fc823b5863 from qemu
2018-02-12 14:07:49 +00:00
env->exception.fsr, (uint32_t)env->exception.vaddress);
import
2015-08-21 07:04:50 +00:00
new_mode = ARM_CPU_MODE_ABT;
addr = 0x0c;
mask = CPSR_A | CPSR_I;
offset = 4;
break;
case EXCP_DATA_ABORT:
target-arm: make DFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Backports commit 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b from qemu
2018-02-12 14:10:35 +00:00
A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
target-arm: make IFAR/DFAR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Backports commit b848ce2b9cbd38da3f2530fd93dba76dba0621c0 from qemu
2018-02-12 14:17:49 +00:00
A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
import
2015-08-21 07:04:50 +00:00
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
target-arm: make DFSR banked When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Backports commit 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b from qemu
2018-02-12 14:10:35 +00:00
env->exception.fsr,
import
2015-08-21 07:04:50 +00:00
(uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x10;
mask = CPSR_A | CPSR_I;
offset = 8;
break;
case EXCP_IRQ:
new_mode = ARM_CPU_MODE_IRQ;
addr = 0x18;
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
target-arm: implement IRQ/FIQ routing to Monitor mode SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Backports commit de38d23b542efca54108ef28bcc0efe96f378d2e from qemu
2018-02-11 23:50:51 +00:00
if (env->cp15.scr_el3 & SCR_IRQ) {
/* IRQ routed to monitor mode */
new_mode = ARM_CPU_MODE_MON;
mask |= CPSR_F;
}
import
2015-08-21 07:04:50 +00:00
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 4;
target-arm: implement IRQ/FIQ routing to Monitor mode SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Backports commit de38d23b542efca54108ef28bcc0efe96f378d2e from qemu
2018-02-11 23:50:51 +00:00
if (env->cp15.scr_el3 & SCR_FIQ) {
/* FIQ routed to monitor mode */
new_mode = ARM_CPU_MODE_MON;
}
import
2015-08-21 07:04:50 +00:00
break;
case EXCP_SMC:
new_mode = ARM_CPU_MODE_MON;
addr = 0x08;
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 0;
break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
/* High vectors. */
target-arm: add MVBAR support Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Backports commit e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 from qemu
2018-02-12 00:07:56 +00:00
if (new_mode == ARM_CPU_MODE_MON) {
addr += env->cp15.mvbar;
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
} else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
target-arm: add MVBAR support Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Backports commit e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 from qemu
2018-02-12 00:07:56 +00:00
/* High vectors. When enabled, base address cannot be remapped. */
import
2015-08-21 07:04:50 +00:00
addr += 0xffff0000;
} else {
/* ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
target-arm: add MVBAR support Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Backports commit e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 from qemu
2018-02-12 00:07:56 +00:00
* This register is only followed in non-monitor mode, and is banked.
import
2015-08-21 07:04:50 +00:00
* Note: only bits 31:5 are valid.
*/
target-arm: make VBAR banked When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Backports commit fb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b from qemu
2018-02-12 14:40:05 +00:00
addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
import
2015-08-21 07:04:50 +00:00
}
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
env->cp15.scr_el3 &= ~SCR_NS;
}
switch_mode (env, new_mode);
/* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
*/
env->uncached_cpsr &= ~PSTATE_SS;
env->spsr = cpsr_read(env);
/* Clear IT bits. */
env->condexec_bits = 0;
/* Switch to the new mode, and to the correct instruction set. */
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
env->daif |= mask;
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
* and we should just guard the thumb mode on V4 */
if (arm_feature(env, ARM_FEATURE_V4T)) {
target-arm: add SCTLR_EL3 and make SCTLR banked Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Backports commit 137feaa9a1622620adf19c0b707883dd990738e2 from qemu
2018-02-12 00:21:26 +00:00
env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
import
2015-08-21 07:04:50 +00:00
}
env->regs[14] = env->regs[15] + offset;
env->regs[15] = addr;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* Return the exception level which controls this address translation regime */
static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_S2NS:
case ARMMMUIdx_S1E2:
return 2;
case ARMMMUIdx_S1E3:
return 3;
case ARMMMUIdx_S1SE0:
return arm_el_is_aa64(env, 3) ? 1 : 3;
case ARMMMUIdx_S1SE1:
case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1:
return 1;
default:
g_assert_not_reached();
}
}
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
/* Return true if this address translation regime is secure */
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_S12NSE0:
case ARMMMUIdx_S12NSE1:
case ARMMMUIdx_S1NSE0:
case ARMMMUIdx_S1NSE1:
case ARMMMUIdx_S1E2:
case ARMMMUIdx_S2NS:
return false;
case ARMMMUIdx_S1E3:
case ARMMMUIdx_S1SE0:
case ARMMMUIdx_S1SE1:
return true;
default:
g_assert_not_reached();
}
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* Return the SCTLR value which controls this address translation regime */
static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
}
/* Return true if the specified stage of address translation is disabled */
static inline bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_S2NS) {
return (env->cp15.hcr_el2 & HCR_VM) == 0;
}
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}
/* Return the TCR controlling this translation regime */
static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_S2NS) {
/* TODO: return VTCR_EL2 */
g_assert_not_reached();
}
return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
}
target-arm: Add TTBR regime function and use Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Backports commit aef878be4e7ab1bdb30b408007320400b0a29c83 from qemu
2018-02-13 02:29:07 +00:00
/* Return the TTBR associated with this translation regime */
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn)
{
if (mmu_idx == ARMMMUIdx_S2NS) {
/* TODO: return VTTBR_EL2 */
g_assert_not_reached();
}
if (ttbrn == 0) {
return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
} else {
return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
}
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* Return true if the translation regime is using LPAE format page tables */
static inline bool regime_using_lpae_format(CPUARMState *env,
ARMMMUIdx mmu_idx)
{
int el = regime_el(env, mmu_idx);
if (el == 2 || arm_el_is_aa64(env, el)) {
return true;
}
if (arm_feature(env, ARM_FEATURE_LPAE)
&& (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
return true;
}
return false;
}
static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_S1SE0:
case ARMMMUIdx_S1NSE0:
return true;
default:
return false;
case ARMMMUIdx_S12NSE0:
case ARMMMUIdx_S12NSE1:
g_assert_not_reached();
}
}
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
/* Translate section/page access permissions to page
* R/W protection flags
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check Introduce simple_ap_to_rw_prot(), which has the same behavior as ap_to_rw_prot(), but takes the 2-bit simple AP[2:1] instead of the 3-bit AP[2:0]. Use this in get_phys_addr_v6 when SCTLR_AFE is set, as that bit indicates we should be using the simple AP format. It's unlikely this path is getting used. I don't see CR_AFE getting used by Linux, so possibly not. If it had been, then the check would have been wrong for all but AP[2:1] = 0b11. Anyway, this should fix it up, in case it ever does get used. Backports commit d76951b65dfb1be4e41cfae6abebf8db7a1243a3 from qemu
2018-02-13 01:22:34 +00:00
*
* @env: CPUARMState
* @mmu_idx: MMU index indicating required translation regime
* @ap: The 3-bit access permissions (AP[2:0])
* @domain_prot: The 2-bit domain access permissions
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
*/
static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
int ap, int domain_prot)
{
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
bool is_user = regime_is_user(env, mmu_idx);
if (domain_prot == 3) {
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
return PAGE_READ | PAGE_WRITE;
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
}
switch (ap) {
case 0:
if (arm_feature(env, ARM_FEATURE_V7)) {
return 0;
}
switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
case SCTLR_S:
return is_user ? 0 : PAGE_READ;
case SCTLR_R:
return PAGE_READ;
default:
return 0;
}
case 1:
return is_user ? 0 : PAGE_READ | PAGE_WRITE;
case 2:
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (is_user) {
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
return PAGE_READ;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
} else {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
return PAGE_READ | PAGE_WRITE;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
case 3:
return PAGE_READ | PAGE_WRITE;
case 4: /* Reserved. */
return 0;
case 5:
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
return is_user ? 0 : PAGE_READ;
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
case 6:
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
return PAGE_READ;
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
case 7:
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (!arm_feature (env, ARM_FEATURE_V6K)) {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
return 0;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
return PAGE_READ;
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
default:
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
g_assert_not_reached();
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
}
import
2015-08-21 07:04:50 +00:00
}
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check Introduce simple_ap_to_rw_prot(), which has the same behavior as ap_to_rw_prot(), but takes the 2-bit simple AP[2:1] instead of the 3-bit AP[2:0]. Use this in get_phys_addr_v6 when SCTLR_AFE is set, as that bit indicates we should be using the simple AP format. It's unlikely this path is getting used. I don't see CR_AFE getting used by Linux, so possibly not. If it had been, then the check would have been wrong for all but AP[2:1] = 0b11. Anyway, this should fix it up, in case it ever does get used. Backports commit d76951b65dfb1be4e41cfae6abebf8db7a1243a3 from qemu
2018-02-13 01:22:34 +00:00
/* Translate section/page access permissions to page
* R/W protection flags.
*
* @ap: The 2-bit simple AP (AP[2:1])
target-arm: get_phys_addr_lpae: more xn control This patch makes the following changes to the determination of whether an address is executable, when translating addresses using LPAE. 1. No longer assumes that PL0 can't execute when it can't read. It can in AArch64, a difference from AArch32. 2. Use va_size == 64 to determine we're in AArch64, rather than arm_feature(env, ARM_FEATURE_V8), which is insufficient. 3. Add additional XN determinants - NS && is_secure && (SCR & SCR_SIF) - WXN && (prot & PAGE_WRITE) - AArch64: (prot_PL0 & PAGE_WRITE) - AArch32: UWXN && (prot_PL0 & PAGE_WRITE) - XN determination should also work in secure mode (untested) - XN may even work in EL2 (currently impossible to test) 4. Cleans up the bloated PAGE_EXEC condition - by removing it. The helper get_S1prot is introduced. It may even work in EL2, when support for that comes, but, as the function name implies, it only works for stage 1 translations. Backports commit d8e052b387635639a6ba4a09a7874fd2f113b218 from qemu
2018-02-13 01:28:06 +00:00
* @is_user: TRUE if accessing from PL0
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check Introduce simple_ap_to_rw_prot(), which has the same behavior as ap_to_rw_prot(), but takes the 2-bit simple AP[2:1] instead of the 3-bit AP[2:0]. Use this in get_phys_addr_v6 when SCTLR_AFE is set, as that bit indicates we should be using the simple AP format. It's unlikely this path is getting used. I don't see CR_AFE getting used by Linux, so possibly not. If it had been, then the check would have been wrong for all but AP[2:1] = 0b11. Anyway, this should fix it up, in case it ever does get used. Backports commit d76951b65dfb1be4e41cfae6abebf8db7a1243a3 from qemu
2018-02-13 01:22:34 +00:00
*/
target-arm: get_phys_addr_lpae: more xn control This patch makes the following changes to the determination of whether an address is executable, when translating addresses using LPAE. 1. No longer assumes that PL0 can't execute when it can't read. It can in AArch64, a difference from AArch32. 2. Use va_size == 64 to determine we're in AArch64, rather than arm_feature(env, ARM_FEATURE_V8), which is insufficient. 3. Add additional XN determinants - NS && is_secure && (SCR & SCR_SIF) - WXN && (prot & PAGE_WRITE) - AArch64: (prot_PL0 & PAGE_WRITE) - AArch32: UWXN && (prot_PL0 & PAGE_WRITE) - XN determination should also work in secure mode (untested) - XN may even work in EL2 (currently impossible to test) 4. Cleans up the bloated PAGE_EXEC condition - by removing it. The helper get_S1prot is introduced. It may even work in EL2, when support for that comes, but, as the function name implies, it only works for stage 1 translations. Backports commit d8e052b387635639a6ba4a09a7874fd2f113b218 from qemu
2018-02-13 01:28:06 +00:00
static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check Introduce simple_ap_to_rw_prot(), which has the same behavior as ap_to_rw_prot(), but takes the 2-bit simple AP[2:1] instead of the 3-bit AP[2:0]. Use this in get_phys_addr_v6 when SCTLR_AFE is set, as that bit indicates we should be using the simple AP format. It's unlikely this path is getting used. I don't see CR_AFE getting used by Linux, so possibly not. If it had been, then the check would have been wrong for all but AP[2:1] = 0b11. Anyway, this should fix it up, in case it ever does get used. Backports commit d76951b65dfb1be4e41cfae6abebf8db7a1243a3 from qemu
2018-02-13 01:22:34 +00:00
{
switch (ap) {
case 0:
return is_user ? 0 : PAGE_READ | PAGE_WRITE;
case 1:
return PAGE_READ | PAGE_WRITE;
case 2:
return is_user ? 0 : PAGE_READ;
case 3:
return PAGE_READ;
default:
g_assert_not_reached();
return 0;
}
}
target-arm: get_phys_addr_lpae: more xn control This patch makes the following changes to the determination of whether an address is executable, when translating addresses using LPAE. 1. No longer assumes that PL0 can't execute when it can't read. It can in AArch64, a difference from AArch32. 2. Use va_size == 64 to determine we're in AArch64, rather than arm_feature(env, ARM_FEATURE_V8), which is insufficient. 3. Add additional XN determinants - NS && is_secure && (SCR & SCR_SIF) - WXN && (prot & PAGE_WRITE) - AArch64: (prot_PL0 & PAGE_WRITE) - AArch32: UWXN && (prot_PL0 & PAGE_WRITE) - XN determination should also work in secure mode (untested) - XN may even work in EL2 (currently impossible to test) 4. Cleans up the bloated PAGE_EXEC condition - by removing it. The helper get_S1prot is introduced. It may even work in EL2, when support for that comes, but, as the function name implies, it only works for stage 1 translations. Backports commit d8e052b387635639a6ba4a09a7874fd2f113b218 from qemu
2018-02-13 01:28:06 +00:00
static inline int
simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
{
return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
}
/* Translate section/page access permissions to protection flags
*
* @env: CPUARMState
* @mmu_idx: MMU index indicating required translation regime
* @is_aa64: TRUE if AArch64
* @ap: The 2-bit simple AP (AP[2:1])
* @ns: NS (non-secure) bit
* @xn: XN (execute-never) bit
* @pxn: PXN (privileged execute-never) bit
*/
static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
int ap, int ns, int xn, int pxn)
{
bool is_user = regime_is_user(env, mmu_idx);
int prot_rw, user_rw;
bool have_wxn;
int wxn = 0;
assert(mmu_idx != ARMMMUIdx_S2NS);
user_rw = simple_ap_to_rw_prot_is_user(ap, true);
if (is_user) {
prot_rw = user_rw;
} else {
prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
}
if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
return prot_rw;
}
/* TODO have_wxn should be replaced with
* ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
* when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
* compatible processors have EL2, which is required for [U]WXN.
*/
have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
if (have_wxn) {
wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
}
if (is_aa64) {
switch (regime_el(env, mmu_idx)) {
case 1:
if (!is_user) {
xn = pxn || (user_rw & PAGE_WRITE);
}
break;
case 2:
case 3:
break;
}
} else if (arm_feature(env, ARM_FEATURE_V7)) {
switch (regime_el(env, mmu_idx)) {
case 1:
case 3:
if (is_user) {
xn = xn || !(user_rw & PAGE_READ);
} else {
int uwxn = 0;
if (have_wxn) {
uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
}
xn = xn || !(prot_rw & PAGE_READ) || pxn ||
(uwxn && (user_rw & PAGE_WRITE));
}
break;
case 2:
break;
}
} else {
xn = wxn = 0;
}
if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
return prot_rw;
}
return prot_rw | PAGE_EXEC;
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
uint32_t *table, uint32_t address)
import
2015-08-21 07:04:50 +00:00
{
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* Note that we can only get here for an AArch32 PL0/PL1 lookup */
TCR *tcr = regime_tcr(env, mmu_idx);
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
if (address & tcr->mask) {
if (tcr->raw_tcr & TTBCR_PD1) {
import
2015-08-21 07:04:50 +00:00
/* Translation table walk disabled for TTBR1 */
return false;
}
target-arm: Add TTBR regime function and use Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Backports commit aef878be4e7ab1bdb30b408007320400b0a29c83 from qemu
2018-02-13 02:29:07 +00:00
*table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
import
2015-08-21 07:04:50 +00:00
} else {
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
if (tcr->raw_tcr & TTBCR_PD0) {
import
2015-08-21 07:04:50 +00:00
/* Translation table walk disabled for TTBR0 */
return false;
}
target-arm: Add TTBR regime function and use Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Backports commit aef878be4e7ab1bdb30b408007320400b0a29c83 from qemu
2018-02-13 02:29:07 +00:00
*table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
import
2015-08-21 07:04:50 +00:00
}
*table |= (address >> 18) & 0x3ffc;
return true;
}
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
/* All loads done in the course of a page table walk go through here.
* TODO: rather than ignoring errors from physical memory reads (which
* are external aborts in ARM terminology) we should propagate this
* error out so that we can turn it into a Data Abort if this walk
* was being done for a CPU load/store or an address translation instruction
* (but not if it was for a debug access).
*/
static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
{
MemTxAttrs attrs = {};
attrs.secure = is_secure;
return address_space_ldl(cs->as, addr, attrs, NULL);
}
static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure)
{
MemTxAttrs attrs = {};
attrs.secure = is_secure;
return address_space_ldq(cs->as, addr, attrs, NULL);
}
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, int *prot,
target_ulong *page_size, uint32_t *fsr)
import
2015-08-21 07:04:50 +00:00
{
CPUState *cs = CPU(arm_env_get_cpu(env));
int code;
uint32_t table;
uint32_t desc;
int type;
int ap;
int domain = 0;
int domain_prot;
hwaddr phys_addr;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
uint32_t dacr;
import
2015-08-21 07:04:50 +00:00
/* Pagetable walk. */
/* Lookup l1 descriptor. */
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (!get_level1_table_address(env, mmu_idx, &table, address)) {
import
2015-08-21 07:04:50 +00:00
/* Section translation fault if page walk is disabled by PD0 or PD1 */
code = 5;
goto do_fault;
}
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
import
2015-08-21 07:04:50 +00:00
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (regime_el(env, mmu_idx) == 1) {
dacr = env->cp15.dacr_ns;
} else {
dacr = env->cp15.dacr_s;
}
domain_prot = (dacr >> (domain * 2)) & 3;
import
2015-08-21 07:04:50 +00:00
if (type == 0) {
/* Section translation fault. */
code = 5;
goto do_fault;
}
if (domain_prot == 0 || domain_prot == 2) {
if (type == 2)
code = 9; /* Section domain fault. */
else
code = 11; /* Page domain fault. */
goto do_fault;
}
if (type == 2) {
/* 1Mb section. */
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
ap = (desc >> 10) & 3;
code = 13;
*page_size = 1024 * 1024;
} else {
/* Lookup l2 entry. */
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
if (type == 1) {
/* Coarse pagetable. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
} else {
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
import
2015-08-21 07:04:50 +00:00
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
goto do_fault;
case 1: /* 64k page. */
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
*page_size = 0x10000;
break;
case 2: /* 4k page. */
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
*page_size = 0x1000;
break;
target-arm: Handle "extended small page" descriptors correctly The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Backports commit fc1891c74ae122a9dc7854f38bae7db03cd911e6 from qemu
2018-02-13 19:17:17 +00:00
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
if (type == 1) {
target-arm: Handle "extended small page" descriptors correctly The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Backports commit fc1891c74ae122a9dc7854f38bae7db03cd911e6 from qemu
2018-02-13 19:17:17 +00:00
/* ARMv6/XScale extended small page format */
if (arm_feature(env, ARM_FEATURE_XSCALE)
|| arm_feature(env, ARM_FEATURE_V6)) {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
target-arm: Handle "extended small page" descriptors correctly The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Backports commit fc1891c74ae122a9dc7854f38bae7db03cd911e6 from qemu
2018-02-13 19:17:17 +00:00
*page_size = 0x1000;
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
} else {
target-arm: Handle "extended small page" descriptors correctly The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Backports commit fc1891c74ae122a9dc7854f38bae7db03cd911e6 from qemu
2018-02-13 19:17:17 +00:00
/* UNPREDICTABLE in ARMv5; we choose to take a
* page translation fault.
*/
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
code = 7;
goto do_fault;
}
} else {
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
target-arm: Handle "extended small page" descriptors correctly The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Backports commit fc1891c74ae122a9dc7854f38bae7db03cd911e6 from qemu
2018-02-13 19:17:17 +00:00
*page_size = 0x400;
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
}
import
2015-08-21 07:04:50 +00:00
ap = (desc >> 4) & 3;
break;
default:
/* Never happens, but compiler isn't smart enough to tell. */
abort();
}
code = 15;
}
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
*prot |= *prot ? PAGE_EXEC : 0;
if (!(*prot & (1 << access_type))) {
import
2015-08-21 07:04:50 +00:00
/* Access permission fault. */
goto do_fault;
}
*phys_ptr = phys_addr;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
return false;
import
2015-08-21 07:04:50 +00:00
do_fault:
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = code | (domain << 4);
return true;
import
2015-08-21 07:04:50 +00:00
}
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
target_ulong *page_size, uint32_t *fsr)
import
2015-08-21 07:04:50 +00:00
{
CPUState *cs = CPU(arm_env_get_cpu(env));
int code;
uint32_t table;
uint32_t desc;
uint32_t xn;
uint32_t pxn = 0;
int type;
int ap;
int domain = 0;
int domain_prot;
hwaddr phys_addr;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
uint32_t dacr;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
bool ns;
import
2015-08-21 07:04:50 +00:00
/* Pagetable walk. */
/* Lookup l1 descriptor. */
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (!get_level1_table_address(env, mmu_idx, &table, address)) {
import
2015-08-21 07:04:50 +00:00
/* Section translation fault if page walk is disabled by PD0 or PD1 */
code = 5;
goto do_fault;
}
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
import
2015-08-21 07:04:50 +00:00
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
* which is Reserved on implementations without PXN.
*/
code = 5;
goto do_fault;
}
if ((type == 1) || !(desc & (1 << 18))) {
/* Page or Section. */
domain = (desc >> 5) & 0x0f;
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (regime_el(env, mmu_idx) == 1) {
dacr = env->cp15.dacr_ns;
} else {
dacr = env->cp15.dacr_s;
}
domain_prot = (dacr >> (domain * 2)) & 3;
import
2015-08-21 07:04:50 +00:00
if (domain_prot == 0 || domain_prot == 2) {
if (type != 1) {
code = 9; /* Section domain fault. */
} else {
code = 11; /* Page domain fault. */
}
goto do_fault;
}
if (type != 1) {
if (desc & (1 << 18)) {
/* Supersection. */
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
target-arm: use extended address bits from supersection short descriptor Since ARMv7 with LPAE support, a supersection short translation table descriptor has had extended base address fields which hold bits 39:32 of translated address. These fields are IMPDEF in ARMv6 and ARMv7 without LPAE support. Backports commit 4e42a6ca37e39e56725518851f4388e46bd91129 from qemu
2018-02-13 19:18:38 +00:00
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
import
2015-08-21 07:04:50 +00:00
*page_size = 0x1000000;
} else {
/* Section. */
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
*page_size = 0x100000;
}
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
xn = desc & (1 << 4);
pxn = desc & 1;
code = 13;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
ns = extract32(desc, 19, 1);
import
2015-08-21 07:04:50 +00:00
} else {
if (arm_feature(env, ARM_FEATURE_PXN)) {
pxn = (desc >> 2) & 1;
}
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
ns = extract32(desc, 3, 1);
import
2015-08-21 07:04:50 +00:00
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
import
2015-08-21 07:04:50 +00:00
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
goto do_fault;
case 1: /* 64k page. */
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
xn = desc & (1 << 15);
*page_size = 0x10000;
break;
case 2: case 3: /* 4k page. */
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
xn = desc & 1;
*page_size = 0x1000;
break;
default:
/* Never happens, but compiler isn't smart enough to tell. */
abort();
}
code = 15;
}
if (domain_prot == 3) {
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
} else {
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (pxn && !regime_is_user(env, mmu_idx)) {
import
2015-08-21 07:04:50 +00:00
xn = 1;
}
if (xn && access_type == 2)
goto do_fault;
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check Introduce simple_ap_to_rw_prot(), which has the same behavior as ap_to_rw_prot(), but takes the 2-bit simple AP[2:1] instead of the 3-bit AP[2:0]. Use this in get_phys_addr_v6 when SCTLR_AFE is set, as that bit indicates we should be using the simple AP format. It's unlikely this path is getting used. I don't see CR_AFE getting used by Linux, so possibly not. If it had been, then the check would have been wrong for all but AP[2:1] = 0b11. Anyway, this should fix it up, in case it ever does get used. Backports commit d76951b65dfb1be4e41cfae6abebf8db7a1243a3 from qemu
2018-02-13 01:22:34 +00:00
if (arm_feature(env, ARM_FEATURE_V6K) &&
(regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
/* The simplified model uses AP[0] as an access control bit. */
if ((ap & 1) == 0) {
/* Access flag fault. */
code = (code == 15) ? 6 : 3;
goto do_fault;
}
*prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
} else {
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
import
2015-08-21 07:04:50 +00:00
}
target-arm: convert check_ap to ap_to_rw_prot Instead of mixing access permission checking with access permissions to page protection flags translation, just do the translation, and leave it to the caller to check the protection flags against the access type. Also rename to ap_to_rw_prot to better describe the new behavior. Backports commit 0fbf5238203041f734c51b49778223686f14366b from qemu
2018-02-13 01:06:02 +00:00
if (*prot && !xn) {
*prot |= PAGE_EXEC;
}
if (!(*prot & (1 << access_type))) {
import
2015-08-21 07:04:50 +00:00
/* Access permission fault. */
goto do_fault;
}
}
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
if (ns) {
/* The NS bit will (as required by the architecture) have no effect if
* the CPU doesn't support TZ or this is a non-secure translation
* regime, because the attribute will already be non-secure.
*/
attrs->secure = false;
}
import
2015-08-21 07:04:50 +00:00
*phys_ptr = phys_addr;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
return false;
import
2015-08-21 07:04:50 +00:00
do_fault:
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = code | (domain << 4);
return true;
import
2015-08-21 07:04:50 +00:00
}
/* Fault type for long-descriptor MMU fault reporting; this corresponds
* to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
*/
typedef enum {
translation_fault = 1,
access_fault = 2,
permission_fault = 3,
} MMUFaultType;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
target_ulong *page_size_ptr, uint32_t *fsr)
import
2015-08-21 07:04:50 +00:00
{
CPUState *cs = CPU(arm_env_get_cpu(env));
/* Read an LPAE long-descriptor translation table. */
MMUFaultType fault_type = translation_fault;
uint32_t level = 1;
uint32_t epd;
int32_t tsz;
uint32_t tg;
uint64_t ttbr;
int ttbr_select;
hwaddr descaddr, descmask;
uint32_t tableattrs;
target_ulong page_size;
uint32_t attrs;
int32_t granule_sz = 9;
int32_t va_size = 32;
int32_t tbi = 0;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
TCR *tcr = regime_tcr(env, mmu_idx);
target-arm: get_phys_addr_lpae: more xn control This patch makes the following changes to the determination of whether an address is executable, when translating addresses using LPAE. 1. No longer assumes that PL0 can't execute when it can't read. It can in AArch64, a difference from AArch32. 2. Use va_size == 64 to determine we're in AArch64, rather than arm_feature(env, ARM_FEATURE_V8), which is insufficient. 3. Add additional XN determinants - NS && is_secure && (SCR & SCR_SIF) - WXN && (prot & PAGE_WRITE) - AArch64: (prot_PL0 & PAGE_WRITE) - AArch32: UWXN && (prot_PL0 & PAGE_WRITE) - XN determination should also work in secure mode (untested) - XN may even work in EL2 (currently impossible to test) 4. Cleans up the bloated PAGE_EXEC condition - by removing it. The helper get_S1prot is introduced. It may even work in EL2, when support for that comes, but, as the function name implies, it only works for stage 1 translations. Backports commit d8e052b387635639a6ba4a09a7874fd2f113b218 from qemu
2018-02-13 01:28:06 +00:00
int ap, ns, xn, pxn;
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
uint32_t el = regime_el(env, mmu_idx);
bool ttbr1_valid = true;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* TODO:
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
* This code does not handle the different format TCR for VTCR_EL2.
* This code also does not support shareability levels.
* Attribute and permission bit handling should also be checked when adding
* support for those page table walks.
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
*/
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
if (arm_el_is_aa64(env, el)) {
import
2015-08-21 07:04:50 +00:00
va_size = 64;
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
if (el > 1) {
tbi = extract64(tcr->raw_tcr, 20, 1);
} else {
if (extract64(address, 55, 1)) {
tbi = extract64(tcr->raw_tcr, 38, 1);
} else {
tbi = extract64(tcr->raw_tcr, 37, 1);
}
}
import
2015-08-21 07:04:50 +00:00
tbi *= 8;
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
/* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
* invalid.
*/
if (el > 1) {
ttbr1_valid = false;
}
import
2015-08-21 07:04:50 +00:00
}
/* Determine whether this address is in the region controlled by
* TTBR0 or TTBR1 (or if it is in neither region and should fault).
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (va_size == 64) {
import
2015-08-21 07:04:50 +00:00
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
}
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (va_size == 64) {
import
2015-08-21 07:04:50 +00:00
t1sz = MIN(t1sz, 39);
t1sz = MAX(t1sz, 16);
}
if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
/* there is a ttbr0 region and we are in it (high bits all zero) */
ttbr_select = 0;
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
} else if (ttbr1_valid && t1sz &&
!extract64(~address, va_size - t1sz, t1sz - tbi)) {
import
2015-08-21 07:04:50 +00:00
/* there is a ttbr1 region and we are in it (high bits all one) */
ttbr_select = 1;
} else if (!t0sz) {
/* ttbr0 region is "everything not in the ttbr1 region" */
ttbr_select = 0;
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
} else if (!t1sz && ttbr1_valid) {
import
2015-08-21 07:04:50 +00:00
/* ttbr1 region is "everything not in the ttbr0 region" */
ttbr_select = 1;
} else {
/* in the gap between the two regions, this is a Translation fault */
fault_type = translation_fault;
goto do_fault;
}
/* Note that QEMU ignores shareability and cacheability attributes,
* so we don't need to do anything with the SH, ORGN, IRGN fields
* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
* ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
* implement any ASID-like capability so we can ignore it (instead
* we will always flush the TLB any time the ASID is changed).
*/
if (ttbr_select == 0) {
target-arm: Add TTBR regime function and use Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Backports commit aef878be4e7ab1bdb30b408007320400b0a29c83 from qemu
2018-02-13 02:29:07 +00:00
ttbr = regime_ttbr(env, mmu_idx, 0);
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
epd = extract32(tcr->raw_tcr, 7, 1);
import
2015-08-21 07:04:50 +00:00
tsz = t0sz;
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
tg = extract32(tcr->raw_tcr, 14, 2);
import
2015-08-21 07:04:50 +00:00
if (tg == 1) { /* 64KB pages */
granule_sz = 13;
}
if (tg == 2) { /* 16KB pages */
granule_sz = 11;
}
} else {
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
/* We should only be here if TTBR1 is valid */
assert(ttbr1_valid);
target-arm: Add TTBR regime function and use Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Backports commit aef878be4e7ab1bdb30b408007320400b0a29c83 from qemu
2018-02-13 02:29:07 +00:00
ttbr = regime_ttbr(env, mmu_idx, 1);
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
epd = extract32(tcr->raw_tcr, 23, 1);
import
2015-08-21 07:04:50 +00:00
tsz = t1sz;
target-arm: make TTBCR banked Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Backports commit 11f136ee25232a00f433cefe98ee33cd614ecccc from qemu
2018-02-12 00:57:59 +00:00
tg = extract32(tcr->raw_tcr, 30, 2);
import
2015-08-21 07:04:50 +00:00
if (tg == 3) { /* 64KB pages */
granule_sz = 13;
}
if (tg == 1) { /* 16KB pages */
granule_sz = 11;
}
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* Here we should have set up all the parameters for the translation:
* va_size, ttbr, epd, tsz, granule_sz, tbi
*/
import
2015-08-21 07:04:50 +00:00
if (epd) {
target-arm: Add EL3 and EL2 TCR checking Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Backports commit 88e8add8b6656c349a96b447b074688d02dc5415 from qemu
2018-02-13 02:31:39 +00:00
/* Translation table walk disabled => Translation fault on TLB miss
* Note: This is always 0 on 64-bit EL2 and EL3.
*/
import
2015-08-21 07:04:50 +00:00
goto do_fault;
}
/* The starting level depends on the virtual address size (which can be
* up to 48 bits) and the translation granule size. It indicates the number
* of strides (granule_sz bits at a time) needed to consume the bits
* of the input address. In the pseudocode this is:
* level = 4 - RoundUp((inputsize - grainsize) / stride)
* where their 'inputsize' is our 'va_size - tsz', 'grainsize' is
* our 'granule_sz + 3' and 'stride' is our 'granule_sz'.
* Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
* = 4 - (va_size - tsz - granule_sz - 3 + granule_sz - 1) / granule_sz
* = 4 - (va_size - tsz - 4) / granule_sz;
*/
level = 4 - (va_size - tsz - 4) / granule_sz;
/* Clear the vaddr bits which aren't part of the within-region address,
* so that we don't have to special case things when calculating the
* first descriptor address.
*/
if (tsz) {
address &= (1ULL << (va_size - tsz)) - 1;
}
descmask = (1ULL << (granule_sz + 3)) - 1;
/* Now we can extract the actual base address from the TTBR */
descaddr = extract64(ttbr, 0, 48);
descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
/* Secure accesses start with the page table in secure memory and
* can be downgraded to non-secure at any step. Non-secure accesses
* remain non-secure. We implement this by just ORing in the NSTable/NS
* bits at each step.
*/
tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
import
2015-08-21 07:04:50 +00:00
for (;;) {
uint64_t descriptor;
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
bool nstable;
import
2015-08-21 07:04:50 +00:00
descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
descaddr &= ~7ULL;
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
nstable = extract32(tableattrs, 4, 1);
descriptor = arm_ldq_ptw(cs, descaddr, !nstable);
import
2015-08-21 07:04:50 +00:00
if (!(descriptor & 1) ||
(!(descriptor & 2) && (level == 3))) {
/* Invalid, or the Reserved level 3 encoding */
goto do_fault;
}
descaddr = descriptor & 0xfffffff000ULL;
if ((descriptor & 2) && (level < 3)) {
/* Table entry. The top five bits are attributes which may
* propagate down through lower levels of the table (and
* which are all arranged so that 0 means "no effect", so
* we can gather them up by ORing in the bits at each level).
*/
tableattrs |= extract64(descriptor, 59, 5);
level++;
continue;
}
/* Block entry at level 1 or 2, or page entry at level 3.
* These are basically the same thing, although the number
* of bits we pull in from the vaddr varies.
*/
page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor and merge with table attrs */
attrs = extract64(descriptor, 2, 10)
| (extract64(descriptor, 52, 12) << 10);
attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
* means "force PL1 access only", which means forcing AP[1] to 0.
*/
if (extract32(tableattrs, 2, 1)) {
attrs &= ~(1 << 4);
}
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
attrs |= nstable << 3; /* NS */
import
2015-08-21 07:04:50 +00:00
break;
}
/* Here descaddr is the final physical address, and attributes
* are all in attrs.
*/
fault_type = access_fault;
if ((attrs & (1 << 8)) == 0) {
/* Access flag */
goto do_fault;
}
target-arm: get_phys_addr_lpae: more xn control This patch makes the following changes to the determination of whether an address is executable, when translating addresses using LPAE. 1. No longer assumes that PL0 can't execute when it can't read. It can in AArch64, a difference from AArch32. 2. Use va_size == 64 to determine we're in AArch64, rather than arm_feature(env, ARM_FEATURE_V8), which is insufficient. 3. Add additional XN determinants - NS && is_secure && (SCR & SCR_SIF) - WXN && (prot & PAGE_WRITE) - AArch64: (prot_PL0 & PAGE_WRITE) - AArch32: UWXN && (prot_PL0 & PAGE_WRITE) - XN determination should also work in secure mode (untested) - XN may even work in EL2 (currently impossible to test) 4. Cleans up the bloated PAGE_EXEC condition - by removing it. The helper get_S1prot is introduced. It may even work in EL2, when support for that comes, but, as the function name implies, it only works for stage 1 translations. Backports commit d8e052b387635639a6ba4a09a7874fd2f113b218 from qemu
2018-02-13 01:28:06 +00:00
ap = extract32(attrs, 4, 2);
ns = extract32(attrs, 3, 1);
xn = extract32(attrs, 12, 1);
pxn = extract32(attrs, 11, 1);
*prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
import
2015-08-21 07:04:50 +00:00
fault_type = permission_fault;
target-arm: get_phys_addr_lpae: more xn control This patch makes the following changes to the determination of whether an address is executable, when translating addresses using LPAE. 1. No longer assumes that PL0 can't execute when it can't read. It can in AArch64, a difference from AArch32. 2. Use va_size == 64 to determine we're in AArch64, rather than arm_feature(env, ARM_FEATURE_V8), which is insufficient. 3. Add additional XN determinants - NS && is_secure && (SCR & SCR_SIF) - WXN && (prot & PAGE_WRITE) - AArch64: (prot_PL0 & PAGE_WRITE) - AArch32: UWXN && (prot_PL0 & PAGE_WRITE) - XN determination should also work in secure mode (untested) - XN may even work in EL2 (currently impossible to test) 4. Cleans up the bloated PAGE_EXEC condition - by removing it. The helper get_S1prot is introduced. It may even work in EL2, when support for that comes, but, as the function name implies, it only works for stage 1 translations. Backports commit d8e052b387635639a6ba4a09a7874fd2f113b218 from qemu
2018-02-13 01:28:06 +00:00
if (!(*prot & (1 << access_type))) {
import
2015-08-21 07:04:50 +00:00
/* Unprivileged access not enabled */
goto do_fault;
}
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
if (ns) {
/* The NS bit will (as required by the architecture) have no effect if
* the CPU doesn't support TZ or this is a non-secure translation
* regime, because the attribute will already be non-secure.
*/
txattrs->secure = false;
}
import
2015-08-21 07:04:50 +00:00
*phys_ptr = descaddr;
*page_size_ptr = page_size;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
return false;
import
2015-08-21 07:04:50 +00:00
do_fault:
/* Long-descriptor format IFSR/DFSR value */
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = (1 << 9) | (fault_type << 2) | level;
return true;
import
2015-08-21 07:04:50 +00:00
}
target-arm: Implement PMSAv7 MPU Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Backports commit f6bda88ff839e2adefe4959b7def420b90703855 from qemu
2018-02-13 21:28:10 +00:00
static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
ARMMMUIdx mmu_idx,
int32_t address, int *prot)
{
*prot = PAGE_READ | PAGE_WRITE;
switch (address) {
case 0xF0000000 ... 0xFFFFFFFF:
if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
*prot |= PAGE_EXEC;
}
break;
case 0x00000000 ... 0x7FFFFFFF:
*prot |= PAGE_EXEC;
break;
}
}
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int n;
bool is_user = regime_is_user(env, mmu_idx);
*phys_ptr = address;
*prot = 0;
if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
} else { /* MPU enabled */
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
/* region search */
uint32_t base = env->pmsav7.drbar[n];
uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
uint32_t rmask;
bool srdis = false;
if (!(env->pmsav7.drsr[n] & 0x1)) {
continue;
}
if (!rsize) {
qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
continue;
}
rsize++;
rmask = (1ull << rsize) - 1;
if (base & rmask) {
qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
"to DRSR region size, mask = %" PRIx32,
base, rmask);
continue;
}
if (address < base || address > base + rmask) {
continue;
}
/* Region matched */
if (rsize >= 8) { /* no subregions for regions < 256 bytes */
int i, snd;
uint32_t srdis_mask;
rsize -= 3; /* sub region size (power of 2) */
snd = ((address - base) >> rsize) & 0x7;
srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
srdis_mask = srdis ? 0x3 : 0x0;
for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
/* This will check in groups of 2, 4 and then 8, whether
* the subregion bits are consistent. rsize is incremented
* back up to give the region size, considering consistent
* adjacent subregions as one region. Stop testing if rsize
* is already big enough for an entire QEMU page.
*/
int snd_rounded = snd & ~(i - 1);
uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
snd_rounded + 8, i);
if (srdis_mask ^ srdis_multi) {
break;
}
srdis_mask = (srdis_mask << i) | srdis_mask;
rsize++;
}
}
if (rsize < TARGET_PAGE_BITS) {
qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
"alignment of %" PRIu32 " bits. Minimum is %d\n",
rsize, TARGET_PAGE_BITS);
continue;
}
if (srdis) {
continue;
}
break;
}
if (n == -1) { /* no hits */
if (cpu->pmsav7_dregion &&
(is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
/* background fault */
*fsr = 0;
return true;
}
get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
} else { /* a MPU hit! */
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
if (is_user) { /* User mode AP bit decoding */
switch (ap) {
case 0:
case 1:
case 5:
break; /* no access */
case 3:
*prot |= PAGE_WRITE;
/* fall through */
case 2:
case 6:
*prot |= PAGE_READ | PAGE_EXEC;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"Bad value for AP bits in DRACR %"
PRIx32 "\n", ap);
}
} else { /* Priv. mode AP bits decoding */
switch (ap) {
case 0:
break; /* no access */
case 1:
case 2:
case 3:
*prot |= PAGE_WRITE;
/* fall through */
case 5:
case 6:
*prot |= PAGE_READ | PAGE_EXEC;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"Bad value for AP bits in DRACR %"
PRIx32 "\n", ap);
}
}
/* execute never */
if (env->pmsav7.dracr[n] & (1 << 12)) {
*prot &= ~PAGE_EXEC;
}
}
}
*fsr = 0x00d; /* Permission fault */
return !(*prot & (1 << access_type));
}
arm: helper: rename get_phys_addr_mpu This get_phys_addr is really for pmsav5. Rename it accordingly. Backports commit 13689d43646482f7305282de1bdd662c0d2b8b77 from qemu
2018-02-13 19:57:10 +00:00
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
import
2015-08-21 07:04:50 +00:00
{
int n;
uint32_t mask;
uint32_t base;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
bool is_user = regime_is_user(env, mmu_idx);
import
2015-08-21 07:04:50 +00:00
*phys_ptr = address;
for (n = 7; n >= 0; n--) {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
base = env->cp15.c6_region[n];
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if ((base & 1) == 0) {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
continue;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
mask = 1 << ((base >> 1) & 0x1f);
/* Keep this shift separate from the above to avoid an
(undefined) << 32. */
mask = (mask << 1) - 1;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (((base ^ address) & ~mask) == 0) {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
break;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
import
2015-08-21 07:04:50 +00:00
}
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (n < 0) {
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = 2;
return true;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
import
2015-08-21 07:04:50 +00:00
if (access_type == 2) {
mask = env->cp15.pmsav5_insn_ap;
} else {
mask = env->cp15.pmsav5_data_ap;
}
mask = (mask >> (n * 4)) & 0xf;
switch (mask) {
case 0:
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = 1;
return true;
import
2015-08-21 07:04:50 +00:00
case 1:
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (is_user) {
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = 1;
return true;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
*prot = PAGE_READ | PAGE_WRITE;
break;
import
2015-08-21 07:04:50 +00:00
case 2:
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
*prot = PAGE_READ;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (!is_user) {
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
*prot |= PAGE_WRITE;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
break;
import
2015-08-21 07:04:50 +00:00
case 3:
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
*prot = PAGE_READ | PAGE_WRITE;
break;
import
2015-08-21 07:04:50 +00:00
case 5:
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
if (is_user) {
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = 1;
return true;
target-arm: Fix brace style in reindented code This patch fixes the brace style in the code reindented in the previous commit. Backports commit 87c3d486150917c8e286d29166c98a2035377b52 from qemu
2018-02-12 16:56:20 +00:00
}
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
*prot = PAGE_READ;
break;
import
2015-08-21 07:04:50 +00:00
case 6:
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
*prot = PAGE_READ;
break;
import
2015-08-21 07:04:50 +00:00
default:
target-arm: Reindent ancient page-table-walk code A few of the oldest parts of the page-table-walk code have broken indent (either hardcoded tabs or two-spaces). Reindent these sections. For ease of review, this patch does not touch the brace style and so is a whitespace-only change. Backports commit 554b0b09aec4579c8164f363b18a263150e91a2c from qemu
2018-02-12 16:53:53 +00:00
/* Bad permission. */
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
*fsr = 1;
return true;
import
2015-08-21 07:04:50 +00:00
}
*prot |= PAGE_EXEC;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
return false;
import
2015-08-21 07:04:50 +00:00
}
/* get_phys_addr - get the physical address for this virtual address
*
* Find the physical address corresponding to the given virtual address,
* by doing a translation table walk on MMU based systems or using the
* MPU state on MPU based systems.
*
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
* Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
* prot and page_size may not be filled in, and the populated fsr value provides
import
2015-08-21 07:04:50 +00:00
* information on why the translation aborted, in the format of a
* DFSR/IFSR fault register, with the following caveats:
* * we honour the short vs long DFSR format differences.
* * the WnR bit is never set (the caller must do this).
target-arm: Implement PMSAv7 MPU Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Backports commit f6bda88ff839e2adefe4959b7def420b90703855 from qemu
2018-02-13 21:28:10 +00:00
* * for PSMAv5 based systems we don't bother to return a full FSR format
import
2015-08-21 07:04:50 +00:00
* value.
*
* @env: CPUARMState
* @address: virtual address to get physical address for
* @access_type: 0 for read, 1 for write, 2 for execute
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
* @mmu_idx: MMU index indicating required translation regime
import
2015-08-21 07:04:50 +00:00
* @phys_ptr: set to the physical address corresponding to the virtual address
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
* @attrs: set to the memory transaction attributes to use
import
2015-08-21 07:04:50 +00:00
* @prot: set to the permissions for the page containing phys_ptr
* @page_size: set to the size of the page containing phys_ptr
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
* @fsr: set to the DFSR/IFSR value on failure
import
2015-08-21 07:04:50 +00:00
*/
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
static inline bool get_phys_addr(CPUARMState *env, target_ulong address,
int access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
target_ulong *page_size, uint32_t *fsr)
import
2015-08-21 07:04:50 +00:00
{
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
/* TODO: when we support EL2 we should here call ourselves recursively
target-arm: Use correct memory attributes for page table walks Factor out the page table walk memory accesses into their own function, so that we can specify the correct S/NS memory attributes for them. This will also provide a place to use the correct endianness and handle the need for a stage-2 translation when virtualization is supported. Backports commit ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 from qemu
2018-02-13 01:39:57 +00:00
* to do the stage 1 and then stage 2 translations. The arm_ld*_ptw
* functions will also need changing to perform ARMMMUIdx_S2NS loads
* rather than direct physical memory loads when appropriate.
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
* For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
*/
assert(!arm_feature(env, ARM_FEATURE_EL2));
mmu_idx += ARMMMUIdx_S1NSE0;
}
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
/* The page table entries may downgrade secure to non-secure, but
* cannot upgrade an non-secure translation regime's attributes
* to secure.
*/
attrs->secure = regime_is_secure(env, mmu_idx);
target-arm: Add user-mode transaction attribute Add a transaction attribute indicating that a memory access is being done from user-mode (unprivileged). This corresponds to an equivalent signal in ARM AMBA buses. Backports commit 0995bf8cd91b81ec9c1078e37b808794080dc5c0 from qemu
2018-02-13 01:41:38 +00:00
attrs->user = regime_is_user(env, mmu_idx);
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
/* Fast Context Switch Extension. This doesn't exist at all in v8.
* In v7 and earlier it affects all stage 1 translations.
*/
if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
&& !arm_feature(env, ARM_FEATURE_V8)) {
if (regime_el(env, mmu_idx) == 3) {
address += env->cp15.fcseidr_s;
} else {
address += env->cp15.fcseidr_ns;
}
target-arm: make c13 cp regs banked (FCSEIDR, ...) When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Backports commit 54bf36ed351c526cde0c853079f9ff1ab7e2ff89 from qemu
2018-02-12 14:42:08 +00:00
}
import
2015-08-21 07:04:50 +00:00
target-arm: Implement PMSAv7 MPU Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Backports commit f6bda88ff839e2adefe4959b7def420b90703855 from qemu
2018-02-13 21:28:10 +00:00
/* pmsav7 has special handling for when MPU is disabled so call it before
* the common MMU/MPU disabled check below.
*/
if (arm_feature(env, ARM_FEATURE_MPU) &&
arm_feature(env, ARM_FEATURE_V7)) {
*page_size = TARGET_PAGE_SIZE;
return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
phys_ptr, prot, fsr);
}
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
if (regime_translation_disabled(env, mmu_idx)) {
import
2015-08-21 07:04:50 +00:00
/* MMU/MPU disabled. */
*phys_ptr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
*page_size = TARGET_PAGE_SIZE;
return 0;
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
target-arm: Implement PMSAv7 MPU Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Backports commit f6bda88ff839e2adefe4959b7def420b90703855 from qemu
2018-02-13 21:28:10 +00:00
/* Pre-v7 MPU */
import
2015-08-21 07:04:50 +00:00
*page_size = TARGET_PAGE_SIZE;
arm: helper: rename get_phys_addr_mpu This get_phys_addr is really for pmsav5. Rename it accordingly. Backports commit 13689d43646482f7305282de1bdd662c0d2b8b77 from qemu
2018-02-13 19:57:10 +00:00
return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
phys_ptr, prot, fsr);
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
}
if (regime_using_lpae_format(env, mmu_idx)) {
return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
attrs, prot, page_size, fsr);
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
attrs, prot, page_size, fsr);
import
2015-08-21 07:04:50 +00:00
} else {
target-arm: Use mmu_idx in get_phys_addr() Now we have the mmu_idx in get_phys_addr(), use it correctly to determine the behaviour of virtual to physical address translations, rather than using just an is_user flag and the current CPU state. Some TODO comments have been added to indicate where changes will need to be made to add EL2 and 64-bit EL3 support. Backports commit 0480f69abf849ca0d48928cc6c669c1c7264239b from qemu
2018-02-12 16:49:31 +00:00
return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
prot, page_size, fsr);
import
2015-08-21 07:04:50 +00:00
}
}
target-arm: Move setting of exception info into tlb_fill Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Backports commit 8c6084bf10fe721929ca94cf16acd6687e61d3ec from qemu
2018-02-13 03:26:33 +00:00
/* Walk the page table and (if the mapping exists) add the page
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
* to the TLB. Return false on success, or true on failure. Populate
* fsr with ARM DFSR/IFSR fault register format value on failure.
target-arm: Move setting of exception info into tlb_fill Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Backports commit 8c6084bf10fe721929ca94cf16acd6687e61d3ec from qemu
2018-02-13 03:26:33 +00:00
*/
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
bool arm_tlb_fill(CPUState *cs, vaddr address,
int access_type, int mmu_idx, uint32_t *fsr)
import
2015-08-21 07:04:50 +00:00
{
CPUARMState *env = cs->env_ptr;
hwaddr phys_addr;
target_ulong page_size;
int prot;
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
int ret;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
MemTxAttrs attrs = {0};
import
2015-08-21 07:04:50 +00:00
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
&attrs, &prot, &page_size, fsr);
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
if (!ret) {
import
2015-08-21 07:04:50 +00:00
/* Map a single [sub]page. */
phys_addr &= TARGET_PAGE_MASK;
address &= TARGET_PAGE_MASK;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
prot, mmu_idx, page_size);
import
2015-08-21 07:04:50 +00:00
return 0;
}
target-arm: Move setting of exception info into tlb_fill Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Backports commit 8c6084bf10fe721929ca94cf16acd6687e61d3ec from qemu
2018-02-13 03:26:33 +00:00
return ret;
import
2015-08-21 07:04:50 +00:00
}
hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
arm: cleanup for ARM_CPU
2017-12-21 01:43:33 +00:00
ARMCPU *cpu = ARM_CPU(NULL, cs);
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
CPUARMState *env = &cpu->env;
import
2015-08-21 07:04:50 +00:00
hwaddr phys_addr;
target_ulong page_size;
int prot;
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
bool ret;
uint32_t fsr;
target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Backports commit 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc from qem
2018-02-13 01:36:04 +00:00
MemTxAttrs attrs = {0};
import
2015-08-21 07:04:50 +00:00
target-arm: Pass mmu_idx to get_phys_addr() Make all the callers of get_phys_addr() pass it the correct mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the logic for handling all the opc1/opc2 cases because we'll need them later for supporting EL2/EL3, even if we don't have the regdef stanzas yet. Backports commit d364970287c0ba68979711928c15e5d37414f87f from qemu
2018-02-12 16:40:47 +00:00
ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr,
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
&attrs, &prot, &page_size, &fsr);
import
2015-08-21 07:04:50 +00:00
arm: Refactor get_phys_addr FSR return mechanism Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Backports commit b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889 from qemu
2018-02-13 19:48:30 +00:00
if (ret) {
import
2015-08-21 07:04:50 +00:00
return -1;
}
return phys_addr;
}
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {
env->regs[13] = val;
} else {
env->banked_r13[bank_number(mode)] = val;
}
}
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {
return env->regs[13];
} else {
return env->banked_r13[bank_number(mode)];
}
}
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
ARMCPU *cpu = arm_env_get_cpu(env);
switch (reg) {
case 0: /* APSR */
return xpsr_read(env) & 0xf8000000;
case 1: /* IAPSR */
return xpsr_read(env) & 0xf80001ff;
case 2: /* EAPSR */
return xpsr_read(env) & 0xff00fc00;
case 3: /* xPSR */
return xpsr_read(env) & 0xff00fdff;
case 5: /* IPSR */
return xpsr_read(env) & 0x000001ff;
case 6: /* EPSR */
return xpsr_read(env) & 0x0700fc00;
case 7: /* IEPSR */
return xpsr_read(env) & 0x0700edff;
case 8: /* MSP */
return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
case 9: /* PSP */
return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
case 16: /* PRIMASK */
return (env->daif & PSTATE_I) != 0;
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
return env->v7m.basepri;
case 19: /* FAULTMASK */
return (env->daif & PSTATE_F) != 0;
case 20: /* CONTROL */
return env->v7m.control;
default:
/* ??? For debugging only. */
cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
return 0;
}
}
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
ARMCPU *cpu = arm_env_get_cpu(env);
switch (reg) {
case 0: /* APSR */
xpsr_write(env, val, 0xf8000000);
break;
case 1: /* IAPSR */
xpsr_write(env, val, 0xf8000000);
break;
case 2: /* EAPSR */
xpsr_write(env, val, 0xfe00fc00);
break;
case 3: /* xPSR */
xpsr_write(env, val, 0xfe00fc00);
break;
case 5: /* IPSR */
/* IPSR bits are readonly. */
break;
case 6: /* EPSR */
xpsr_write(env, val, 0x0600fc00);
break;
case 7: /* IEPSR */
xpsr_write(env, val, 0x0600fc00);
break;
case 8: /* MSP */
if (env->v7m.current_sp)
env->v7m.other_sp = val;
else
env->regs[13] = val;
break;
case 9: /* PSP */
if (env->v7m.current_sp)
env->regs[13] = val;
else
env->v7m.other_sp = val;
break;
case 16: /* PRIMASK */
if (val & 1) {
env->daif |= PSTATE_I;
} else {
env->daif &= ~PSTATE_I;
}
break;
case 17: /* BASEPRI */
env->v7m.basepri = val & 0xff;
break;
case 18: /* BASEPRI_MAX */
val &= 0xff;
if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
env->v7m.basepri = val;
break;
case 19: /* FAULTMASK */
if (val & 1) {
env->daif |= PSTATE_F;
} else {
env->daif &= ~PSTATE_F;
}
break;
case 20: /* CONTROL */
env->v7m.control = val & 3;
switch_v7m_sp(env, (val & 2) != 0);
break;
default:
/* ??? For debugging only. */
cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
return;
}
}
#endif
void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
{
/* Implement DC ZVA, which zeroes a fixed-length block of memory.
* Note that we do not implement the (architecturally mandated)
* alignment fault for attempts to use this on Device memory
* (which matches the usual QEMU behaviour of not implementing either
* alignment faults or any memory attribute handling).
*/
ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t blocklen = 4 << cpu->dcz_blocksize;
uint64_t vaddr = vaddr_in & ~(blocklen - 1);
#ifndef CONFIG_USER_ONLY
{
/* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
* the block size so we might have to do more than one TLB lookup.
* We know that in fact for any v8 CPU the page size is at least 4K
* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
* 1K as an artefact of legacy v5 subpage support being present in the
* same QEMU executable.
*/
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
import
2015-08-21 07:04:50 +00:00
int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
// msvc doesnt allow non-constant array sizes, so we work out the size it would be
// TARGET_PAGE_SIZE is 1024
// blocklen is 64
// maxidx = (blocklen+TARGET_PAGE_SIZE-1) / TARGET_PAGE_SIZE
// = (64+1024-1) / 1024
// = 1
#ifdef _MSC_VER
void *hostaddr[1];
#else
import
2015-08-21 07:04:50 +00:00
void *hostaddr[maxidx];
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
#endif
import
2015-08-21 07:04:50 +00:00
int try, i;
tcg: Push merged memop+mmu_idx parameter to softmmu routines The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu
2018-02-11 00:29:47 +00:00
unsigned mmu_idx = cpu_mmu_index(env);
TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
import
2015-08-21 07:04:50 +00:00
for (try = 0; try < 2; try++) {
for (i = 0; i < maxidx; i++) {
hostaddr[i] = tlb_vaddr_to_host(env,
vaddr + TARGET_PAGE_SIZE * i,
tcg: Push merged memop+mmu_idx parameter to softmmu routines The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu
2018-02-11 00:29:47 +00:00
1, mmu_idx);
import
2015-08-21 07:04:50 +00:00
if (!hostaddr[i]) {
break;
}
}
if (i == maxidx) {
/* If it's all in the TLB it's fair game for just writing to;
* we know we don't need to update dirty status, etc.
*/
for (i = 0; i < maxidx - 1; i++) {
memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
}
memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
return;
}
/* OK, try a store and see if we can populate the tlb. This
* might cause an exception if the memory isn't writable,
* in which case we will longjmp out of here. We must for
* this purpose use the actual register value passed to us
* so that we get the fault address right.
*/
tcg: Push merged memop+mmu_idx parameter to softmmu routines The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu
2018-02-11 00:29:47 +00:00
helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
import
2015-08-21 07:04:50 +00:00
/* Now we can populate the other TLB entries, if any */
for (i = 0; i < maxidx; i++) {
uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
if (va != (vaddr_in & TARGET_PAGE_MASK)) {
tcg: Push merged memop+mmu_idx parameter to softmmu routines The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu
2018-02-11 00:29:47 +00:00
helper_ret_stb_mmu(env, va, 0, oi, GETRA());
import
2015-08-21 07:04:50 +00:00
}
}
}
/* Slow path (probably attempt to do this to an I/O device or
* similar, or clearing of a block of code we have translations
* cached for). Just do a series of byte writes as the architecture
* demands. It's not worth trying to use a cpu_physical_memory_map(),
* memset(), unmap() sequence here because:
* + we'd need to account for the blocksize being larger than a page
* + the direct-RAM access case is almost always going to be dealt
* with in the fastpath code above, so there's no speed benefit
* + we would have to deal with the map returning NULL because the
* bounce buffer was in use
*/
for (i = 0; i < blocklen; i++) {
tcg: Push merged memop+mmu_idx parameter to softmmu routines The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu
2018-02-11 00:29:47 +00:00
helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
import
2015-08-21 07:04:50 +00:00
}
}
#else
memset(g2h(vaddr), 0, blocklen);
#endif
}
/* Note that signed overflow is undefined in C. The following routines are
careful to use unsigned types where modulo arithmetic is required.
Failure to do so _will_ break on newer gcc. */
/* Signed saturating arithmetic. */
/* Perform 16-bit signed saturating addition. */
static inline uint16_t add16_sat(uint16_t a, uint16_t b)
{
uint16_t res;
res = a + b;
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
if (a & 0x8000)
res = 0x8000;
else
res = 0x7fff;
}
return res;
}
/* Perform 8-bit signed saturating addition. */
static inline uint8_t add8_sat(uint8_t a, uint8_t b)
{
uint8_t res;
res = a + b;
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
if (a & 0x80)
res = 0x80;
else
res = 0x7f;
}
return res;
}
/* Perform 16-bit signed saturating subtraction. */
static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
{
uint16_t res;
res = a - b;
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
if (a & 0x8000)
res = 0x8000;
else
res = 0x7fff;
}
return res;
}
/* Perform 8-bit signed saturating subtraction. */
static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
{
uint8_t res;
res = a - b;
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
if (a & 0x80)
res = 0x80;
else
res = 0x7f;
}
return res;
}
#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
#define PFX q
#include "op_addsub.h"
/* Unsigned saturating arithmetic. */
static inline uint16_t add16_usat(uint16_t a, uint16_t b)
{
uint16_t res;
res = a + b;
if (res < a)
res = 0xffff;
return res;
}
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
{
if (a > b)
return a - b;
else
return 0;
}
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
{
uint8_t res;
res = a + b;
if (res < a)
res = 0xff;
return res;
}
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
{
if (a > b)
return a - b;
else
return 0;
}
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
#define PFX uq
#include "op_addsub.h"
/* Signed modulo arithmetic. */
#define SARITH16(a, b, n, op) do { \
int32_t sum; \
sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
RESULT(sum, n, 16); \
if (sum >= 0) \
ge |= 3 << (n * 2); \
} while(0)
#define SARITH8(a, b, n, op) do { \
int32_t sum; \
sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
RESULT(sum, n, 8); \
if (sum >= 0) \
ge |= 1 << n; \
} while(0)
#define ADD16(a, b, n) SARITH16(a, b, n, +)
#define SUB16(a, b, n) SARITH16(a, b, n, -)
#define ADD8(a, b, n) SARITH8(a, b, n, +)
#define SUB8(a, b, n) SARITH8(a, b, n, -)
#define PFX s
#define ARITH_GE
#include "op_addsub.h"
/* Unsigned modulo arithmetic. */
#define ADD16(a, b, n) do { \
uint32_t sum; \
sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
RESULT(sum, n, 16); \
if ((sum >> 16) == 1) \
ge |= 3 << (n * 2); \
} while(0)
#define ADD8(a, b, n) do { \
uint32_t sum; \
sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
RESULT(sum, n, 8); \
if ((sum >> 8) == 1) \
ge |= 1 << n; \
} while(0)
#define SUB16(a, b, n) do { \
uint32_t sum; \
sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
RESULT(sum, n, 16); \
if ((sum >> 16) == 0) \
ge |= 3 << (n * 2); \
} while(0)
#define SUB8(a, b, n) do { \
uint32_t sum; \
sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
RESULT(sum, n, 8); \
if ((sum >> 8) == 0) \
ge |= 1 << n; \
} while(0)
#define PFX u
#define ARITH_GE
#include "op_addsub.h"
/* Halved signed arithmetic. */
#define ADD16(a, b, n) \
RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
#define SUB16(a, b, n) \
RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
#define ADD8(a, b, n) \
RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
#define SUB8(a, b, n) \
RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
#define PFX sh
#include "op_addsub.h"
/* Halved unsigned arithmetic. */
#define ADD16(a, b, n) \
RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
#define SUB16(a, b, n) \
RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
#define ADD8(a, b, n) \
RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
#define SUB8(a, b, n) \
RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
#define PFX uh
#include "op_addsub.h"
static inline uint8_t do_usad(uint8_t a, uint8_t b)
{
if (a > b)
return a - b;
else
return b - a;
}
/* Unsigned sum of absolute byte differences. */
uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
{
uint32_t sum;
sum = do_usad(a, b);
sum += do_usad(a >> 8, b >> 8);
sum += do_usad(a >> 16, b >>16);
sum += do_usad(a >> 24, b >> 24);
return sum;
}
/* For ARMv6 SEL instruction. */
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
{
uint32_t mask;
mask = 0;
if (flags & 1)
mask |= 0xff;
if (flags & 2)
mask |= 0xff00;
if (flags & 4)
mask |= 0xff0000;
if (flags & 8)
mask |= 0xff000000;
return (a & mask) | (b & ~mask);
}
/* VFP support. We follow the convention used for VFP instructions:
Single precision routines have a "s" suffix, double precision a
"d" suffix. */
/* Convert host exception flags to vfp form. */
static inline int vfp_exceptbits_from_host(int host_bits)
{
int target_bits = 0;
if (host_bits & float_flag_invalid)
target_bits |= 1;
if (host_bits & float_flag_divbyzero)
target_bits |= 2;
if (host_bits & float_flag_overflow)
target_bits |= 4;
if (host_bits & (float_flag_underflow | float_flag_output_denormal))
target_bits |= 8;
if (host_bits & float_flag_inexact)
target_bits |= 0x10;
if (host_bits & float_flag_input_denormal)
target_bits |= 0x80;
return target_bits;
}
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
{
int i;
uint32_t fpscr;
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
i = get_float_exception_flags(&env->vfp.fp_status);
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
fpscr |= vfp_exceptbits_from_host(i);
return fpscr;
}
uint32_t vfp_get_fpscr(CPUARMState *env)
{
return HELPER(vfp_get_fpscr)(env);
}
/* Convert vfp exception flags to target form. */
static inline int vfp_exceptbits_to_host(int target_bits)
{
int host_bits = 0;
if (target_bits & 1)
host_bits |= float_flag_invalid;
if (target_bits & 2)
host_bits |= float_flag_divbyzero;
if (target_bits & 4)
host_bits |= float_flag_overflow;
if (target_bits & 8)
host_bits |= float_flag_underflow;
if (target_bits & 0x10)
host_bits |= float_flag_inexact;
if (target_bits & 0x80)
host_bits |= float_flag_input_denormal;
return host_bits;
}
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
int i;
uint32_t changed;
changed = env->vfp.xregs[ARM_VFP_FPSCR];
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
env->vfp.vec_len = (val >> 16) & 7;
env->vfp.vec_stride = (val >> 20) & 3;
changed ^= val;
if (changed & (3 << 22)) {
i = (val >> 22) & 3;
switch (i) {
case FPROUNDING_TIEEVEN:
i = float_round_nearest_even;
break;
case FPROUNDING_POSINF:
i = float_round_up;
break;
case FPROUNDING_NEGINF:
i = float_round_down;
break;
case FPROUNDING_ZERO:
i = float_round_to_zero;
break;
}
set_float_rounding_mode(i, &env->vfp.fp_status);
}
if (changed & (1 << 24)) {
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
}
if (changed & (1 << 25))
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
i = vfp_exceptbits_to_host(val);
set_float_exception_flags(i, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.standard_fp_status);
}
void vfp_set_fpscr(CPUARMState *env, uint32_t val)
{
HELPER(vfp_set_fpscr)(env, val);
}
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
#define VFP_BINOP(name) \
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
{ \
float_status *fpst = fpstp; \
return float32_ ## name(a, b, fpst); \
} \
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
{ \
float_status *fpst = fpstp; \
return float64_ ## name(a, b, fpst); \
}
VFP_BINOP(add)
VFP_BINOP(sub)
VFP_BINOP(mul)
VFP_BINOP(div)
VFP_BINOP(min)
VFP_BINOP(max)
VFP_BINOP(minnum)
VFP_BINOP(maxnum)
#undef VFP_BINOP
float32 VFP_HELPER(neg, s)(float32 a)
{
return float32_chs(a);
}
float64 VFP_HELPER(neg, d)(float64 a)
{
return float64_chs(a);
}
float32 VFP_HELPER(abs, s)(float32 a)
{
return float32_abs(a);
}
float64 VFP_HELPER(abs, d)(float64 a)
{
return float64_abs(a);
}
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
{
return float32_sqrt(a, &env->vfp.fp_status);
}
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
{
return float64_sqrt(a, &env->vfp.fp_status);
}
/* XXX: check quiet/signaling case */
#define DO_VFP_cmp(p, type) \
void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
{ \
uint32_t flags; \
switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
case 0: flags = 0x6; break; \
case -1: flags = 0x8; break; \
case 1: flags = 0x2; break; \
default: case 2: flags = 0x3; break; \
} \
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
} \
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
{ \
uint32_t flags; \
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
case 0: flags = 0x6; break; \
case -1: flags = 0x8; break; \
case 1: flags = 0x2; break; \
default: case 2: flags = 0x3; break; \
} \
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
}
DO_VFP_cmp(s, float32)
DO_VFP_cmp(d, float64)
#undef DO_VFP_cmp
/* Integer to float and float to integer conversions */
#define CONV_ITOF(name, fsz, sign) \
float##fsz HELPER(name)(uint32_t x, void *fpstp) \
{ \
float_status *fpst = fpstp; \
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
}
#define CONV_FTOI(name, fsz, sign, round) \
uint32_t HELPER(name)(float##fsz x, void *fpstp) \
{ \
float_status *fpst = fpstp; \
if (float##fsz##_is_any_nan(x)) { \
float_raise(float_flag_invalid, fpst); \
return 0; \
} \
return float##fsz##_to_##sign##int32##round(x, fpst); \
}
#define FLOAT_CONVS(name, p, fsz, sign) \
CONV_ITOF(vfp_##name##to##p, fsz, sign) \
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
FLOAT_CONVS(si, s, 32, )
FLOAT_CONVS(si, d, 64, )
FLOAT_CONVS(ui, s, 32, u)
FLOAT_CONVS(ui, d, 64, u)
#undef CONV_ITOF
#undef CONV_FTOI
#undef FLOAT_CONVS
/* floating point conversion */
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
{
float64 r = float32_to_float64(x, &env->vfp.fp_status);
/* ARM requires that S<->D conversion of any kind of NaN generates
* a quiet NaN by forcing the most significant frac bit to 1.
*/
return float64_maybe_silence_nan(r);
}
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
{
float32 r = float64_to_float32(x, &env->vfp.fp_status);
/* ARM requires that S<->D conversion of any kind of NaN generates
* a quiet NaN by forcing the most significant frac bit to 1.
*/
return float32_maybe_silence_nan(r);
}
/* VFP3 fixed point conversion. */
#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
void *fpstp) \
{ \
float_status *fpst = fpstp; \
float##fsz tmp; \
tmp = itype##_to_##float##fsz(x, fpst); \
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
}
/* Notice that we want only input-denormal exception flags from the
* scalbn operation: the other possible flags (overflow+inexact if
* we overflow to infinity, output-denormal) aren't correct for the
* complete scale-and-convert operation.
*/
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
uint32_t shift, \
void *fpstp) \
{ \
float_status *fpst = fpstp; \
int old_exc_flags = get_float_exception_flags(fpst); \
float##fsz tmp; \
if (float##fsz##_is_any_nan(x)) { \
float_raise(float_flag_invalid, fpst); \
return 0; \
} \
tmp = float##fsz##_scalbn(x, shift, fpst); \
old_exc_flags |= get_float_exception_flags(fpst) \
& float_flag_input_denormal; \
set_float_exception_flags(old_exc_flags, fpst); \
return float##fsz##_to_##itype##round(tmp, fpst); \
}
#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
#define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
VFP_CONV_FIX(sh, d, 64, 64, int16)
VFP_CONV_FIX(sl, d, 64, 64, int32)
VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
VFP_CONV_FIX(uh, d, 64, 64, uint16)
VFP_CONV_FIX(ul, d, 64, 64, uint32)
VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
VFP_CONV_FIX(sh, s, 32, 32, int16)
VFP_CONV_FIX(sl, s, 32, 32, int32)
VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
VFP_CONV_FIX(uh, s, 32, 32, uint16)
VFP_CONV_FIX(ul, s, 32, 32, uint32)
VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
#undef VFP_CONV_FIX
#undef VFP_CONV_FIX_FLOAT
#undef VFP_CONV_FLOAT_FIX_ROUND
/* Set the current fp rounding mode and return the old one.
* The argument is a softfloat float_round_ value.
*/
uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
{
float_status *fp_status = &env->vfp.fp_status;
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
set_float_rounding_mode(rmode, fp_status);
return prev_rmode;
}
/* Set the current fp rounding mode in the standard fp status and return
* the old one. This is for NEON instructions that need to change the
* rounding mode but wish to use the standard FPSCR values for everything
* else. Always set the rounding mode back to the correct value after
* modifying it.
* The argument is a softfloat float_round_ value.
*/
uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
{
float_status *fp_status = &env->vfp.standard_fp_status;
uint32_t prev_rmode = get_float_rounding_mode(fp_status);
set_float_rounding_mode(rmode, fp_status);
return prev_rmode;
}
/* Half precision conversions. */
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
{
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float32 r = float16_to_float32(make_float16(a), ieee, s);
if (ieee) {
return float32_maybe_silence_nan(r);
}
return r;
}
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
{
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float16 r = float32_to_float16(a, ieee, s);
if (ieee) {
r = float16_maybe_silence_nan(r);
}
return float16_val(r);
}
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
{
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
}
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
{
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
}
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
{
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
}
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
{
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
}
float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
{
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
if (ieee) {
return float64_maybe_silence_nan(r);
}
return r;
}
uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
{
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
if (ieee) {
r = float16_maybe_silence_nan(r);
}
return float16_val(r);
}
#define float32_two make_float32(0x40000000)
#define float32_three make_float32(0x40400000)
#define float32_one_point_five make_float32(0x3fc00000)
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
{
float_status *s = &env->vfp.standard_fp_status;
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
if (!(float32_is_zero(a) || float32_is_zero(b))) {
float_raise(float_flag_input_denormal, s);
}
return float32_two;
}
return float32_sub(float32_two, float32_mul(a, b, s), s);
}
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
{
float_status *s = &env->vfp.standard_fp_status;
float32 product;
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
(float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
if (!(float32_is_zero(a) || float32_is_zero(b))) {
float_raise(float_flag_input_denormal, s);
}
return float32_one_point_five;
}
product = float32_mul(a, b, s);
return float32_div(float32_sub(float32_three, product, s), float32_two, s);
}
/* NEON helpers. */
/* Constants 256 and 512 are used in some helpers; we avoid relying on
* int->float conversions at run-time. */
#define float64_256 make_float64(0x4070000000000000LL)
#define float64_512 make_float64(0x4080000000000000LL)
#define float32_maxnorm make_float32(0x7f7fffff)
#define float64_maxnorm make_float64(0x7fefffffffffffffLL)
/* Reciprocal functions
*
* The algorithm that must be used to calculate the estimate
* is specified by the ARM ARM, see FPRecipEstimate()
*/
static float64 recip_estimate(float64 a, float_status *real_fp_status)
{
/* These calculations mustn't set any fp exception flags,
* so we use a local copy of the fp_status.
*/
float_status dummy_status = *real_fp_status;
float_status *s = &dummy_status;
/* q = (int)(a * 512.0) */
float64 q = float64_mul(float64_512, a, s);
int64_t q_int = float64_to_int64_round_to_zero(q, s);
/* r = 1.0 / (((double)q + 0.5) / 512.0) */
q = int64_to_float64(q_int, s);
q = float64_add(q, float64_half, s);
q = float64_div(q, float64_512, s);
q = float64_div(float64_one, q, s);
/* s = (int)(256.0 * r + 0.5) */
q = float64_mul(q, float64_256, s);
q = float64_add(q, float64_half, s);
q_int = float64_to_int64_round_to_zero(q, s);
/* return (double)s / 256.0 */
return float64_div(int64_to_float64(q_int, s), float64_256, s);
}
/* Common wrapper to call recip_estimate */
static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
{
uint64_t val64 = float64_val(num);
uint64_t frac = extract64(val64, 0, 52);
int64_t exp = extract64(val64, 52, 11);
uint64_t sbit;
float64 scaled, estimate;
/* Generate the scaled number for the estimate function */
if (exp == 0) {
if (extract64(frac, 51, 1) == 0) {
exp = -1;
frac = extract64(frac, 0, 50) << 2;
} else {
frac = extract64(frac, 0, 51) << 1;
}
}
/* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
scaled = make_float64((0x3feULL << 52)
| extract64(frac, 44, 8) << 44);
estimate = recip_estimate(scaled, fpst);
/* Build new result */
val64 = float64_val(estimate);
sbit = 0x8000000000000000ULL & val64;
exp = off - exp;
frac = extract64(val64, 0, 52);
if (exp == 0) {
frac = 1ULL << 51 | extract64(frac, 1, 51);
} else if (exp == -1) {
frac = 1ULL << 50 | extract64(frac, 2, 50);
exp = 0;
}
return make_float64(sbit | (exp << 52) | frac);
}
static bool round_to_inf(float_status *fpst, bool sign_bit)
{
switch (fpst->float_rounding_mode) {
case float_round_nearest_even: /* Round to Nearest */
return true;
case float_round_up: /* Round to +Inf */
return !sign_bit;
case float_round_down: /* Round to -Inf */
return sign_bit;
case float_round_to_zero: /* Round to Zero */
return false;
arm: fix a warning
2017-02-23 12:32:09 +00:00
default:
break;
import
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}
g_assert_not_reached();
Fixes for MSVC native support to still work with GCC/GNU.
2017-01-20 14:07:10 +00:00
return false;
import
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}
float32 HELPER(recpe_f32)(float32 input, void *fpstp)
{
float_status *fpst = fpstp;
float32 f32 = float32_squash_input_denormal(input, fpst);
uint32_t f32_val = float32_val(f32);
uint32_t f32_sbit = 0x80000000ULL & f32_val;
int32_t f32_exp = extract32(f32_val, 23, 8);
uint32_t f32_frac = extract32(f32_val, 0, 23);
float64 f64, r64;
uint64_t r64_val;
int64_t r64_exp;
uint64_t r64_frac;
if (float32_is_any_nan(f32)) {
float32 nan = f32;
if (float32_is_signaling_nan(f32)) {
float_raise(float_flag_invalid, fpst);
nan = float32_maybe_silence_nan(f32);
}
if (fpst->default_nan_mode) {
nan = float32_default_nan;
}
return nan;
} else if (float32_is_infinity(f32)) {
return float32_set_sign(float32_zero, float32_is_neg(f32));
} else if (float32_is_zero(f32)) {
float_raise(float_flag_divbyzero, fpst);
return float32_set_sign(float32_infinity, float32_is_neg(f32));
} else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
/* Abs(value) < 2.0^-128 */
float_raise(float_flag_overflow | float_flag_inexact, fpst);
if (round_to_inf(fpst, f32_sbit)) {
return float32_set_sign(float32_infinity, float32_is_neg(f32));
} else {
return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
}
} else if (f32_exp >= 253 && fpst->flush_to_zero) {
float_raise(float_flag_underflow, fpst);
return float32_set_sign(float32_zero, float32_is_neg(f32));
}
f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
r64 = call_recip_estimate(f64, 253, fpst);
r64_val = float64_val(r64);
r64_exp = extract64(r64_val, 52, 11);
r64_frac = extract64(r64_val, 0, 52);
/* result = sign : result_exp<7:0> : fraction<51:29>; */
return make_float32(f32_sbit |
(r64_exp & 0xff) << 23 |
extract64(r64_frac, 29, 24));
}
float64 HELPER(recpe_f64)(float64 input, void *fpstp)
{
float_status *fpst = fpstp;
float64 f64 = float64_squash_input_denormal(input, fpst);
uint64_t f64_val = float64_val(f64);
uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
int64_t f64_exp = extract64(f64_val, 52, 11);
float64 r64;
uint64_t r64_val;
int64_t r64_exp;
uint64_t r64_frac;
/* Deal with any special cases */
if (float64_is_any_nan(f64)) {
float64 nan = f64;
if (float64_is_signaling_nan(f64)) {
float_raise(float_flag_invalid, fpst);
nan = float64_maybe_silence_nan(f64);
}
if (fpst->default_nan_mode) {
nan = float64_default_nan;
}
return nan;
} else if (float64_is_infinity(f64)) {
return float64_set_sign(float64_zero, float64_is_neg(f64));
} else if (float64_is_zero(f64)) {
float_raise(float_flag_divbyzero, fpst);
return float64_set_sign(float64_infinity, float64_is_neg(f64));
} else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
/* Abs(value) < 2.0^-1024 */
float_raise(float_flag_overflow | float_flag_inexact, fpst);
if (round_to_inf(fpst, f64_sbit)) {
return float64_set_sign(float64_infinity, float64_is_neg(f64));
} else {
return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
}
target-arm: fix for exponent comparison in recpe_f64 f64 exponent in HELPER(recpe_f64) should be compared to 2045 rather than 1023 (FPRecipEstimate in ARMV8 spec). This fixes incorrect underflow handling when flushing denormals to zero in the FRECPE instructions operating on 64-bit values. Backports commit fc1792e9aa36227ee9994757974f9397684e1a48 from qemu
2018-02-12 17:04:15 +00:00
} else if (f64_exp >= 2045 && fpst->flush_to_zero) {
import
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float_raise(float_flag_underflow, fpst);
return float64_set_sign(float64_zero, float64_is_neg(f64));
}
r64 = call_recip_estimate(f64, 2045, fpst);
r64_val = float64_val(r64);
r64_exp = extract64(r64_val, 52, 11);
r64_frac = extract64(r64_val, 0, 52);
/* result = sign : result_exp<10:0> : fraction<51:0> */
return make_float64(f64_sbit |
((r64_exp & 0x7ff) << 52) |
r64_frac);
}
/* The algorithm that must be used to calculate the estimate
* is specified by the ARM ARM.
*/
static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
{
/* These calculations mustn't set any fp exception flags,
* so we use a local copy of the fp_status.
*/
float_status dummy_status = *real_fp_status;
float_status *s = &dummy_status;
float64 q;
int64_t q_int;
if (float64_lt(a, float64_half, s)) {
/* range 0.25 <= a < 0.5 */
/* a in units of 1/512 rounded down */
/* q0 = (int)(a * 512.0); */
q = float64_mul(float64_512, a, s);
q_int = float64_to_int64_round_to_zero(q, s);
/* reciprocal root r */
/* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
q = int64_to_float64(q_int, s);
q = float64_add(q, float64_half, s);
q = float64_div(q, float64_512, s);
q = float64_sqrt(q, s);
q = float64_div(float64_one, q, s);
} else {
/* range 0.5 <= a < 1.0 */
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
int64_t q_int;
import
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/* a in units of 1/256 rounded down */
/* q1 = (int)(a * 256.0); */
q = float64_mul(float64_256, a, s);
Arm support ported. (#736) * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file
2017-01-23 15:30:57 +00:00
q_int = float64_to_int64_round_to_zero(q, s);
import
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/* reciprocal root r */
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
q = int64_to_float64(q_int, s);
q = float64_add(q, float64_half, s);
q = float64_div(q, float64_256, s);
q = float64_sqrt(q, s);
q = float64_div(float64_one, q, s);
}
/* r in units of 1/256 rounded to nearest */
/* s = (int)(256.0 * r + 0.5); */
q = float64_mul(q, float64_256,s );
q = float64_add(q, float64_half, s);
q_int = float64_to_int64_round_to_zero(q, s);
/* return (double)s / 256.0;*/
return float64_div(int64_to_float64(q_int, s), float64_256, s);
}
float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
{
float_status *s = fpstp;
float32 f32 = float32_squash_input_denormal(input, s);
uint32_t val = float32_val(f32);
uint32_t f32_sbit = 0x80000000 & val;
int32_t f32_exp = extract32(val, 23, 8);
uint32_t f32_frac = extract32(val, 0, 23);
uint64_t f64_frac;
uint64_t val64;
int result_exp;
float64 f64;
if (float32_is_any_nan(f32)) {
float32 nan = f32;
if (float32_is_signaling_nan(f32)) {
float_raise(float_flag_invalid, s);
nan = float32_maybe_silence_nan(f32);
}
if (s->default_nan_mode) {
nan = float32_default_nan;
}
return nan;
} else if (float32_is_zero(f32)) {
float_raise(float_flag_divbyzero, s);
return float32_set_sign(float32_infinity, float32_is_neg(f32));
} else if (float32_is_neg(f32)) {
float_raise(float_flag_invalid, s);
return float32_default_nan;
} else if (float32_is_infinity(f32)) {
return float32_zero;
}
/* Scale and normalize to a double-precision value between 0.25 and 1.0,
* preserving the parity of the exponent. */
f64_frac = ((uint64_t) f32_frac) << 29;
if (f32_exp == 0) {
while (extract64(f64_frac, 51, 1) == 0) {
f64_frac = f64_frac << 1;
f32_exp = f32_exp-1;
}
f64_frac = extract64(f64_frac, 0, 51) << 1;
}
if (extract64(f32_exp, 0, 1) == 0) {
f64 = make_float64(((uint64_t) f32_sbit) << 32
| (0x3feULL << 52)
| f64_frac);
} else {
f64 = make_float64(((uint64_t) f32_sbit) << 32
| (0x3fdULL << 52)
| f64_frac);
}
result_exp = (380 - f32_exp) / 2;
f64 = recip_sqrt_estimate(f64, s);
val64 = float64_val(f64);
val = ((result_exp & 0xff) << 23)
| ((val64 >> 29) & 0x7fffff);
return make_float32(val);
}
float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
{
float_status *s = fpstp;
float64 f64 = float64_squash_input_denormal(input, s);
uint64_t val = float64_val(f64);
uint64_t f64_sbit = 0x8000000000000000ULL & val;
int64_t f64_exp = extract64(val, 52, 11);
uint64_t f64_frac = extract64(val, 0, 52);
int64_t result_exp;
uint64_t result_frac;
if (float64_is_any_nan(f64)) {
float64 nan = f64;
if (float64_is_signaling_nan(f64)) {
float_raise(float_flag_invalid, s);
nan = float64_maybe_silence_nan(f64);
}
if (s->default_nan_mode) {
nan = float64_default_nan;
}
return nan;
} else if (float64_is_zero(f64)) {
float_raise(float_flag_divbyzero, s);
return float64_set_sign(float64_infinity, float64_is_neg(f64));
} else if (float64_is_neg(f64)) {
float_raise(float_flag_invalid, s);
return float64_default_nan;
} else if (float64_is_infinity(f64)) {
return float64_zero;
}
/* Scale and normalize to a double-precision value between 0.25 and 1.0,
* preserving the parity of the exponent. */
if (f64_exp == 0) {
while (extract64(f64_frac, 51, 1) == 0) {
f64_frac = f64_frac << 1;
f64_exp = f64_exp - 1;
}
f64_frac = extract64(f64_frac, 0, 51) << 1;
}
if (extract64(f64_exp, 0, 1) == 0) {
f64 = make_float64(f64_sbit
| (0x3feULL << 52)
| f64_frac);
} else {
f64 = make_float64(f64_sbit
| (0x3fdULL << 52)
| f64_frac);
}
result_exp = (3068 - f64_exp) / 2;
f64 = recip_sqrt_estimate(f64, s);
result_frac = extract64(float64_val(f64), 0, 52);
return make_float64(f64_sbit |
((result_exp & 0x7ff) << 52) |
result_frac);
}
uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
{
float_status *s = fpstp;
float64 f64;
if ((a & 0x80000000) == 0) {
return 0xffffffff;
}
f64 = make_float64((0x3feULL << 52)
| ((int64_t)(a & 0x7fffffff) << 21));
f64 = recip_estimate(f64, s);
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
}
uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
{
float_status *fpst = fpstp;
float64 f64;
if ((a & 0xc0000000) == 0) {
return 0xffffffff;
}
if (a & 0x80000000) {
f64 = make_float64((0x3feULL << 52)
| ((uint64_t)(a & 0x7fffffff) << 21));
} else { /* bits 31-30 == '01' */
f64 = make_float64((0x3fdULL << 52)
| ((uint64_t)(a & 0x3fffffff) << 22));
}
f64 = recip_sqrt_estimate(f64, fpst);
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
}
/* VFPv4 fused multiply-accumulate */
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
{
float_status *fpst = fpstp;
return float32_muladd(a, b, c, 0, fpst);
}
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
{
float_status *fpst = fpstp;
return float64_muladd(a, b, c, 0, fpst);
}
/* ARMv8 round to integral */
float32 HELPER(rints_exact)(float32 x, void *fp_status)
{
return float32_round_to_int(x, fp_status);
}
float64 HELPER(rintd_exact)(float64 x, void *fp_status)
{
return float64_round_to_int(x, fp_status);
}
float32 HELPER(rints)(float32 x, void *fp_status)
{
int old_flags = get_float_exception_flags(fp_status), new_flags;
float32 ret;
ret = float32_round_to_int(x, fp_status);
/* Suppress any inexact exceptions the conversion produced */
if (!(old_flags & float_flag_inexact)) {
new_flags = get_float_exception_flags(fp_status);
set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
}
return ret;
}
float64 HELPER(rintd)(float64 x, void *fp_status)
{
int old_flags = get_float_exception_flags(fp_status), new_flags;
float64 ret;
ret = float64_round_to_int(x, fp_status);
new_flags = get_float_exception_flags(fp_status);
/* Suppress any inexact exceptions the conversion produced */
if (!(old_flags & float_flag_inexact)) {
new_flags = get_float_exception_flags(fp_status);
set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
}
return ret;
}
/* Convert ARM rounding mode to softfloat */
int arm_rmode_to_sf(int rmode)
{
switch (rmode) {
case FPROUNDING_TIEAWAY:
rmode = float_round_ties_away;
break;
case FPROUNDING_ODD:
/* FIXME: add support for TIEAWAY and ODD */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
rmode);
case FPROUNDING_TIEEVEN:
default:
rmode = float_round_nearest_even;
break;
case FPROUNDING_POSINF:
rmode = float_round_up;
break;
case FPROUNDING_NEGINF:
rmode = float_round_down;
break;
case FPROUNDING_ZERO:
rmode = float_round_to_zero;
break;
}
return rmode;
}
/* CRC helpers.
* The upper bytes of val (above the number specified by 'bytes') must have
* been zeroed out by the caller.
*/
uint32_t HELPER(crc32_arm)(uint32_t acc, uint32_t val, uint32_t bytes)
{
#if 0 // FIXME
uint8_t buf[4];
stl_le_p(buf, val);
/* zlib crc32 converts the accumulator and output to one's complement. */
return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
#endif
return 0;
}
uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
{
uint8_t buf[4];
stl_le_p(buf, val);
/* Linux crc32c converts the output to one's complement. */
return crc32c(acc, buf, bytes) ^ 0xffffffff;
}
Reference in a new issue Copy permalink