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2249 commits

Author SHA1 Message Date
Alex Bennée 780ed8722e
qom/cpu: move tlb_flush to cpu_common_reset
It is a common thing amongst the various cpu reset functions want to
flush the SoftMMU's TLB entries. This is done either by calling
tlb_flush directly or by way of a general memset of the CPU
structure (sometimes both).

This moves the tlb_flush call to the common reset function and
additionally ensures it is only done for the CONFIG_SOFTMMU case and
when tcg is enabled.

In some target cases we add an empty end_of_reset_fields structure to the
target vCPU structure so have a clear end point for any memset which
is resetting value in the structure before CPU_COMMON (where the TLB
structures are).

While this is a nice clean-up in general it is also a precursor for
changes coming to cputlb for MTTCG where the clearing of entries
can't be done arbitrarily across vCPUs. Currently the cpu_reset
function is usually called from the context of another vCPU as the
architectural power up sequence is run. By using the cputlb API
functions we can ensure the right behaviour in the future.

Backports commit 1f5c00cfdb8114c1e3a13426588ceb64f82c9ddb from qemu
2018-03-01 19:21:07 -05:00
Laurent Vivier 770989f36f
target-m68k: increment/decrement with SP
On 680x0 family only.

Address Register indirect With postincrement:

When using the stack pointer (A7) with byte size data, the register
is incremented by two.

Address Register indirect With predecrement:

When using the stack pointer (A7) with byte size data, the register
is decremented by two.

Backports commit 727d937b59f1f722f983e20f9cd23b0e7ef60165 from qemu
2018-03-01 19:16:22 -05:00
Laurent Vivier 6ff83aadab
target-m68k: CAS doesn't need aligned access
Backports commit b19578f42872aefef891e5804359af8d935a5487 from qemu
2018-03-01 19:15:20 -05:00
Laurent Vivier 636bf36272
target-m68k: manage pre-dec et post-inc in CAS
In these cases we must update the address register after
the operation.

Backports commit 308feb935249ad745ef763707e1db69bc10ba789 from qemu
2018-03-01 19:14:35 -05:00
Laurent Vivier 1197d778cc
target-m68k: fix gen_flush_flags()
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.

We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)

FIX: https://github.com/vivier/qemu-m68k/issues/19

Backports commit 695576db2daaf2bdc63e7f6d36038b61caed622a from qemu
2018-03-01 19:13:35 -05:00
Laurent Vivier b3c3cf84a5
target-m68k: fix bit operation with immediate value
M680x0 bit operations with an immediate value use 9 bits of the 16bit
value, while coldfire ones use only 8 bits.

Backports commit fe53c2be8c12da345bd788b949e0b2360e4b3db3 from qemu
2018-03-01 19:12:20 -05:00
Richard Henderson 6f5081314b
target-m68k: Implement bfffo
Backports commit a45f1763cc501861ea4f5eed06e6f58aa681a082 from qemu
2018-03-01 19:10:59 -05:00
Richard Henderson 797e5d44e9
target-m68k: Implement bitfield ops for memory
Backports commit f2224f2c9a9ed63edaed77ae21ffb1e501d7f247 from qemu
2018-03-01 19:07:06 -05:00
Richard Henderson 4f481b2c5a
target-m68k: Implement bitfield ops for registers
Backports commit ac815f46a325b5dabe2ebd6561e4244767c0a603 from qemu
2018-03-01 18:58:47 -05:00
Doug Evans 7bd3170ea5
target/i386: Fix bad patch application to translate.c
In commit c52ab08aee6f7d4717fc6b517174043126bd302f,
the patch snippet for the "syscall" insn got applied to "iret".

Backports commit 410e98146ffde201ab4c778823ac8beaa74c4c3f from qemu
2018-03-01 18:52:10 -05:00
Richard Henderson 4bec129626
tcg/i386: Handle ctpop opcode
Backports commit 993508e43e6d180e9ba9b747a9657eac69aec5bb from qemu
2018-03-01 18:49:43 -05:00
Richard Henderson 3a0fba32f3
tcg/ppc: Handle ctpop opcode
Backports commit 33e75fb9c8cc44165c8dad9093762ba728cc7596 from qemu
2018-03-01 18:46:43 -05:00
Richard Henderson 6d4fc1319a
tcg/ppc: Handle ctz and clz opcodes
Backports commit d0b07481fabb4dc4ed05d56d09718758f5f7a136 from qemu
2018-03-01 18:44:54 -05:00
Richard Henderson ff3512a045
tcg: Use ctpop to generate ctz if needed
Particularly when andc is also available, this is two insns
shorter than using clz to compute ctz.

Backports commit 14e99210f6c6cede461a54b2e0f9b4cd55175f00 from qemu
2018-03-01 18:39:20 -05:00
Richard Henderson 5ca8ac1aeb
qemu/host-utils.h: Reduce the operation count in the fallback ctpop
Backports commit 7bdcecb7b2d79c292d1256f7d6cf0f1da50d381f from qemu
2018-03-01 18:35:51 -05:00
Richard Henderson 8a62878523
target-i386: Use ctpop helper
Backports commit 4885c3c49531995d67e54907d01d5aa1350faaaf from qemu
2018-03-01 18:34:10 -05:00
Richard Henderson d072ea48e7
target-sparc: Use ctpop helper
Backports commit 08da3180dca8d41881b321d43944d97a838792fa from qemu
2018-03-01 18:28:54 -05:00
Richard Henderson 5f6e7bbdbd
tcg: Add opcode for ctpop
The number of actual invocations of ctpop itself does not warrent
an opcode, but it is very helpful for POWER7 to use in generating
an expansion for ctz.

Backports commit a768e4e99247911f00c5c0267c12d4e207d5f6cc from qemu
2018-03-01 18:26:41 -05:00
Richard Henderson 01b3c6273a
target-arm: Use clrsb helper
Backports commit bc21dbcc1203ae6bb536f832c46a3b5e22a73451 from qemu
2018-03-01 18:16:56 -05:00
Richard Henderson fff7ca4617
tcg: Add helpers for clrsb
The number of actual invocations does not warrent an opcode,
and the backends generating it. But at least we can eliminate
redundant helpers.

Backports commit 086920c2c8008f125fd38781072fa25c3ad158ea from qemu
2018-03-01 18:14:11 -05:00
Richard Henderson 246d891668
tcg/i386: Handle ctz and clz opcodes
Backports commit bbf25f90ba802a286fd72be9175a860ae5fec726 from qemu
2018-03-01 16:56:08 -05:00
Richard Henderson 73ab332185
tcg/i386: Allow bmi2 shiftx to have non-matching operands
Previously we could not have different constraints for different ISA levels,
which prevented us from eliding the matching constraint for shifts.

We do now have to make sure that the operands match for constant shifts.
We can also handle some small left shifts via lea.

Backports commit 6a5aed4bdc7078838a8098336588d56c9ce09d1d from qemu
2018-03-01 16:45:04 -05:00
Richard Henderson 9e3feebbfb
tcg/i386: Hoist common arguments in tcg_out_op
Backports commit 42d5b514928a8a0d2f55a4c243d1333f9675815b from qemu
2018-03-01 16:42:30 -05:00
Richard Henderson 142ca07077
tcg/i386: Fuly convert tcg_target_op_def
Use a switch instead of searching a table. Share constraints between
32-bit and 64-bit, when at all possible.

Backports commit cd26449a505f808e479af4fdd539e05767e09c06 from qemu
2018-03-01 16:32:31 -05:00
Richard Henderson 54ca83b900
tcg/s390: Handle clz opcode
Backports commit ce411066f4886cf3a4981fc0a070042a221a5fc8 from qemu
2018-03-01 16:24:29 -05:00
Richard Henderson a90e026c18
tcg/mips: Handle clz opcode
Backports commit 2a1d9d41aedd722d674b2a94d9b7dbea61469cac from qemu
2018-03-01 16:22:52 -05:00
Richard Henderson 303fc987ed
tcg/arm: Handle ctz and clz opcodes
Backports commit cc0fec8a4d2a8546fe236a09bfd80150af9cbe6b from qemu
2018-03-01 16:20:46 -05:00
Richard Henderson 2b87ddda35
tcg/aarch64: Handle ctz and clz opcodes
Backports commit 53c76c19904983d2c81e4f5e77027c241918a479 from qemu
2018-03-01 16:19:34 -05:00
Richard Henderson 22ebc5fcee
target-i386: Use clz and ctz opcodes
Backports commit e5143c90883cd32a432eb793cdcce6bee747834a from qemu
2018-03-01 16:17:42 -05:00
Richard Henderson 9cde8bfc44
target-arm: Use clz opcode
Backports commit 7539a012f614b724426ac9360238f3281d928a3f from qemu
2018-03-01 16:13:26 -05:00
Richard Henderson 9b2752b0a9
target-mips: Use clz opcode
Backports commit 1a0196c5c7f197fad7b079074d587b3204bcfb0f from qemu
2018-03-01 16:08:19 -05:00
Richard Henderson 2cf34e1b55
tcg: Add clz and ctz opcodes
Backports commit 0e28d0063bbd9e59a981ea2d20f82f30c5d956a8 from qemu
2018-03-01 16:04:11 -05:00
Richard Henderson b4b173615c
tcg: Allow an operand to be matching or a constant
This allows an output operand to match an input operand
only when the input operand needs a register.

Backports commit 17280ff4a5f264e01e55ae514ee6d3586f9577b2 from qemu
2018-03-01 15:49:05 -05:00
Richard Henderson 3f38611159
tcg: Pass the opcode width to target_parse_constraint
This will let us choose how to interpret a given constraint
depending on whether the opcode is 32- or 64-bit. Which will
let us share more constraint combinations between opcodes.

At the same time, change the interface to return the advanced
pointer instead of passing it in/out by reference.

Backports commit 069ea736b50b75fdec99c9b8cc603b97bd98419e from qemu
2018-03-01 15:45:40 -05:00
Richard Henderson b8c93597b4
tcg: Transition flat op_defs array to a target callback
This will allow the target to tailor the constraints to the
auto-detected ISA extensions.

Backports commit f69d277ece43c42c7ab0144c2ff05ba740f6706b from qemu
2018-03-01 15:40:11 -05:00
Richard Henderson 551ef0a9f7
tcg: Add markup for output requires new register
This is the same concept as, and same markup as, the
early clobber markup in gcc.

Backports commit 82790a870992bd87d5fd9e607f40859dcf4f82ac from qemu
2018-03-01 15:24:58 -05:00
Richard Henderson 199b3859c4
tcg/optimize: Fold movcond 0/1 into setcond
Backports commit 333b21b809fc80ce67c8f6a7d1c7cc66437d9791 from qemu
2018-03-01 14:41:38 -05:00
Richard Henderson b62743947f
target-mips: Use the new extract op
Use extract for EXT and DEXT.

Backports commit 6eebb7a438236fcf3fdadb013921ac597aaea911 fromq qemu
2018-03-01 14:39:20 -05:00
Richard Henderson e5acbeb86e
target-i386: Use new deposit and extract ops
A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.

Backports commit 04fc2f1c8fc030a11e08e81bb926392c0991282a from qemu
2018-03-01 14:38:17 -05:00
Richard Henderson ce3c153bd8
target-arm: Use new deposit and extract ops
Use the new primitives for UBFX and SBFX.

Backports commits 59a71b4c5b4ef2ef6425b9e21c972dd5bf450275 and 86c9ab277615af4e0389eb80a83073873ff96c86 from qemu
2018-03-01 14:09:17 -05:00
Richard Henderson f0781470b4
tcg/s390: Support deposit into zero
Since we can no longer use matching constraints, this does
mean we must handle that data movement by hand.

Backports commit 752b1be94757de906b9c24ebc8f5e6aa54b96b23 from qemu
2018-03-01 13:47:20 -05:00
Richard Henderson a7462cc7bf
tcg/s390: Implement field extraction opcodes
Backports commit b0bf5fe82df93c180f69d439af59f1f546632f13 from qemu
2018-03-01 13:45:33 -05:00
Richard Henderson ab8871ea82
tcg/s390: Implement field extraction opcodes
Backports commit b0bf5fe82df93c180f69d439af59f1f546632f13 from qemu
2018-03-01 13:43:46 -05:00
Richard Henderson 348802286c
tcg/s390: Expose host facilities to tcg-target.h
This lets us expose facilities to TCG_TARGET_HAS_* defines
directly, rather than hiding behind function calls.

Backports commit b2c98d9d392c87c9b9e975d30f79924719d9cbbe from qemu
2018-03-01 13:43:00 -05:00
Richard Henderson db41c6f1d0
tcg/ppc: Implement field extraction opcodes
Backports commit c05021c3c8d6c976e4677d3010b9ef01488a4434 from qemu
2018-03-01 13:38:42 -05:00
Richard Henderson b10a4a9ee6
tcg/mips: Implement field extraction opcodes
Backports commit befbb3ced5869003ee2e806c4f36e306918d2374 from qemu
2018-03-01 13:37:24 -05:00
Richard Henderson 7a7a5c640d
tcg/i386: Implement field extraction opcodes
Backports commit 78fdbfb94616f0391834d2eccabd16ea29e37da5 from qemu
2018-03-01 13:35:41 -05:00
Richard Henderson cabb6f71a0
tcg/arm: Implement field extraction opcodes
Backports commit ec903af18418e0870af84f6036d7aca1e6a5dc0a from qemu
2018-03-01 13:33:55 -05:00
Richard Henderson c4f56ec541
tcg/arm: Move isa detection to tcg-target.h
This allows us to use this detection within the TCG_TARGET_HAS_*
macros, instead of requiring a function call into tcg-target.inc.c.

Backports commit 40b2ccb156534f5d5f1d110a6ce008d87ee10af1 from qemu
2018-03-01 13:32:39 -05:00
Richard Henderson fbea4130fc
tcg/aarch64: Implement field extraction opcodes
Backports commit e2179f94a17bf0933df29ce1b4f6bc93cbe7dbd3 from qemu
2018-03-01 13:30:55 -05:00
Richard Henderson 9f2fcaaf27
tcg: Add deposit_z expander
While we don't require a new opcode, it is handy to have an expander
that knows the first source is zero.

Backports commit 07cc68d52852bf47dea7c402b46ddd28248d4212 from qemu
2018-03-01 13:29:24 -05:00
Richard Henderson 8e0585dcb1
tcg: Add field extraction primitives
Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of
fixed position bitfields, much like we already have for deposit.

Backports commit 7ec8bab3deae643b1ce579c2d65a244f30708330 from qemu
2018-03-01 13:21:30 -05:00
Jason Wang 29932d0719
memory: handle alias in memory_region_is_iommu()
Backports commit 12d37882f0c0def5dee1c21be5d8fea9c21baada from qemu
2018-03-01 13:06:18 -05:00
Jason Wang fdca6292a1
exec: introduce address_space_get_iotlb_entry()
This patch introduces a helper to query the iotlb entry for a
possible iova. This will be used by later device IOTLB API to enable
the capability for a dataplane (e.g vhost) to query the IOTLB.

Backports commit 052c8fa9983f553fdfa0d61034774070dd639c2b from qemu
2018-03-01 13:05:08 -05:00
Richard Henderson efad2631d2
translate-all: Avoid -Werror=switch-bool
gcc 5.3.0 diagnoses

translate-all.c: In function ‘alloc_code_gen_buffer’:
translate-all.c:756:17: error: switch condition has boolean value
switch (buf2 != MAP_FAILED) {
^

Backports commit f68808c7494b38764e1895a9852b994638b86536 from qemu
2018-03-01 13:01:50 -05:00
Jin Guojie 4ed2a37f6d
tcg-mips: Adjust qemu_ld/st for mips64
Backports commit f0d703314ecb0415d51425727ed73ad2c6e3238a from qemu
2018-03-01 13:01:05 -05:00
Jin Guojie 25b4e11814
tcg-mips: Adjust calling conventions for mips64
Backports commit 999b941633cabf2487d9bc77ce382b3fde3cd66d from qemu
2018-03-01 12:53:42 -05:00
Jin Guojie 3de761976c
tcg-mips: Adjust prologue for mips64
Take stack frame parameters out from the function body.

Backports commit 0973b1cff8b66f3561befb1f467b2ab4d1a7d55a from qemu
2018-03-01 12:51:36 -05:00
Jin Guojie b55b7403a8
tcg-mips: Adjust load/store functions for mips64
tcg_out_ldst: using a generic ALIAS_PADD to avoid ifdefs
tcg_out_ld: generates LD or LW
tcg_out_st: generates SD or SW

Backports commit 32b69707df3365aadaad1d058044a7704397ec62 from qemu
2018-03-01 12:50:12 -05:00
Jin Guojie 022ff3580e
tcg-mips: Adjust move functions for mips64
tcg_out_mov: using OPC_OR as most mips assemblers do;
tcg_out_movi: extended to 64-bit immediate.

Backports commit 2294d05dab503d11664e73712c7f250fd0bf9e3b from qemu
2018-03-01 12:49:19 -05:00
Jin Guojie 00ccf9cec7
tcg-mips: Add bswap32u and bswap64
Without the mips32r2 instructions to perform swapping, bswap is quite large,
dominating the size of each reverse-endian qemu_ld/qemu_st operation.

Create two subroutines in the prologue block. The subroutines require extra
reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that
we need not place additional restrictions on the qemu_ld outputs.

Backports commit 7f54eaa3b78d71cb57e45a719980f9b5ff06d21c from qemu
2018-03-01 12:47:45 -05:00
Jin Guojie 397db1b046
tcg-mips: Support 64-bit opcodes
Bulk patch adding 64-bit opcodes into tcg_out_op. Note that
mips64 is as yet neither complete nor enabled.

Backports commit 0119b1927d531f3fac22b9b4da01dafc23644973 from qemu
2018-03-01 12:46:18 -05:00
Jin Guojie 286f3a9f70
tcg-mips: Add mips64 opcodes
Since the mips manual tables are in octal, reorg all of the opcodes
into that format for clarity. Note that the 64-bit opcodes are as
yet unused.

Backports commit 57a701fc2b34902310d4dbd1411088055616938a from qemu
2018-03-01 12:36:20 -05:00
Jin Guojie d2aa49e9d3
tcg-mips: Move bswap code to a subroutine
Without the mips32r2 instructions to perform swapping, bswap is quite large,
dominating the size of each reverse-endian qemu_ld/qemu_st operation.

Create a subroutine in the prologue block. The subroutine requires extra
reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that
we need not place additional restrictions on the qemu_ld outputs.

Backports commit bb08afe9f0aee1a3f5c23508e2511b882ca31e1b from qemu
2018-03-01 12:35:20 -05:00
Laurent Vivier 5d4a5e9ba7
target-m68k: free TCG variables that are not
This is a cleanup patch. It adds call to tcg_temp_free()
when it is missing.

Backports commit 2b5e2170678af36df48ab4b05dff81fe40b41a65 from qemu
2018-03-01 12:27:43 -05:00
Laurent Vivier 74beed5a4d
target-m68k: add rol/ror/roxl/roxr instructions
Backports commit 0194cf31cfc84516d10eca354146673150e10410 from qemu
2018-03-01 12:21:02 -05:00
Richard Henderson cf9424d60d
target-m68k: Inline shifts
Also manage word and byte operands and fix the computation of
overflow in the case of M68000 arithmetic shifts.

Backports commit 367790cce8e14131426f5190dfd7d1bdbf656e4d from qemu
2018-03-01 12:11:10 -05:00
Richard Henderson 0c00b036be
target-m68k: Do not cpu_abort on undefined insns
Report this properly via exception and, importantly, allow
the disassembler the chance to tell us what insn is not handled.

Backports commit 72d2e4b6a437f11f97d3138f6b2ec177b78210c7 from qemu
2018-03-01 12:02:39 -05:00
Laurent Vivier 90b0b6d867
target-m68k: Implement 680x0 movem
680x0 movem can load/store words and long words and can use more
addressing modes. Coldfire can only use long words with (Ax) and
(d16,Ax) addressing modes.

Backports commit 7b542eb96d7d5d9266a9c0425f05d49c8e6df2f9 from qemu
2018-03-01 12:01:46 -05:00
Laurent Vivier 2d318da080
target-m68k: add cas/cas2 ops
Implement CAS using cmpxchg.
Implement CAS2 using helper and either cmpxchg when
the 32bit addresses are consecutive, or with
parallel_cpus+cpu_loop_exit_atomic() otherwise.

Backports commit 14f944063affbcc7bd6df42b060793dbfee8a822 from qemu
2018-03-01 11:56:26 -05:00
Laurent Vivier f602f9d40c
target-m68k: add abcd/sbcd/nbcd
Backports commit fb5543d820018a46b713911e7653594be727ca98 from qemu
2018-03-01 11:51:49 -05:00
Laurent Vivier 90b87b3580
target-m68k: add 680x0 divu/divs variants
Update helper to set the throwing location in case of div-by-0.
Cleanup divX.w and add quad word variants of divX.l.

Backports commit 0ccb9c1d8128a020720d5c6abf99a470742a1b94 from qemu
2018-03-01 11:42:30 -05:00
Laurent Vivier 77b8b2f3b8
target-m68k: add 680x0 divu/divs variants
Update helper to set the throwing location in case of div-by-0.
Cleanup divX.w and add quad word variants of divX.l.

Backports commit 0ccb9c1d8128a020720d5c6abf99a470742a1b94 from qemu
2018-03-01 11:38:53 -05:00
Laurent Vivier f3990e8f87
target-m68k: add 64bit mull
Backports commit 8be95defd6ab10d2c9f986879a0afa82417cb8e5 from qemu
2018-03-01 11:32:59 -05:00
Laurent Vivier e1c7d37556
target-m68k: add cmpm
Backports commit 817af1c72d227fd5759ef882bef61acee40679b1 from qemu
2018-03-01 11:29:35 -05:00
Richard Henderson e6ca471dda
target-m68k: Split gen_lea and gen_ea
Provide gen_lea_mode and gen_ea_mode, where the mode can be
specified manually, rather than taken from the instruction.

Backports commit f84aab269ddab8509b77408b886e9071bf5c48fb from qemu
2018-03-01 11:27:43 -05:00
Richard Henderson 5541553e8d
target-m68k: Delay autoinc writeback
Backports commit 8a1e52b69d2cd1c633f3c473a213d575931bf46d from qemu
2018-03-01 11:18:36 -05:00
Cédric Le Goater c7ab1e782b
target-arm: Add VBAR support to ARM1176 CPUs
ARM1176 CPUs have TrustZone support and can use the Vector Base
Address Register, but currently, qemu only adds VBAR support to ARMv7
CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used
for ARMv7 and ARM1176 CPUs.

The VBAR feature is always set for ARMv7 because some legacy boards
require it even if this is not architecturally correct.

Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu
2018-03-01 11:12:29 -05:00
Peter Maydell 554ad1f34e
target-arm: Log AArch64 exception returns
We already log exception entry; add logging of the AArch64 exception
return path as well.

Backports commit c9b61d9aa1ad234b0961f8add023cdc999cda3da from qemu
2018-03-01 11:08:35 -05:00
Julian Brown 86670028f7
Correct value of ARM Cortex-A8 MVFR1 register.
The value of the MVFR1 (Media and VFP Feature Register 1) register for
the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K),
with the "full denormal arithmetic" and "propagation of NaN" fields
holding both 0 instead of both 1.

I had a go tracing the history of the use of this value, and it seems
it's always just been wrong in QEMU: maybe it was derived from early
documentation, or guessed based on the use of a "VFP Lite" implementation
in the Cortex-A8.

Depending on the startup/early-boot code in use, this can manifest as
failure to perform denormal arithmetic properly: in our case, selecting
a Cortex-A8 CPU when using QEMU as an instruction-set simulator for
bare-metal GCC testing caused tests using denormal arithmetic to
fail. Problems might be masked (or not occur) when using a full OS kernel
with suitable trap handlers (I'm not sure).

Backports commit 0f1944735b6bac810b067e8a7a5154744536fd59 from qemu
2018-03-01 11:07:08 -05:00
Richard Henderson fcc05dc1ce
tcg/s390: Remove 'R' constraint
Since R0 is reserved, we don't need a special case constraint.

Backports commit e45d4ef6e345831c8d67a5bffe0d057efc20f4ff from qemu
2018-03-01 11:05:57 -05:00
Richard Henderson 7852cc600d
tcg/s390: Fix setcond expansion
We can't use LOAD AND TEST for unsigned data and then expect to
extract the result with ADD LOGICAL WITH CARRY. Fall through to
using COMPARE LOGICAL IMMEDIATE instead.

Backports commit 65839b56b9a740e6b898b5d81afc160502bd2935 from qemu
2018-03-01 11:04:40 -05:00
Kirill A. Shutemov eb489625b5
x86: implement la57 paging mode
The new paging more is extension of IA32e mode with more additional page
table level.

It brings support of 57-bit vitrual address space (128PB) and 52-bit
physical address space (4PB).

The structure of new page table level is identical to pml4.

The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16].

CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level
paging mode.

Backports commit 6c7c3c21f95dd9af8a0691c0dd29b07247984122 from qemu
2018-03-01 11:02:07 -05:00
Doug Evans 7c874b1b2b
target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns
The syscall and sysret instructions behave a bit differently:
TF is checked after the instruction completes.
This allows the o/s to disable #DB at a syscall by adding TF to FMASK.
And then when the sysret is executed the #DB is taken "as if" the
syscall insn just completed.

Backports commit c52ab08aee6f7d4717fc6b517174043126bd302f from qemu
2018-03-01 10:56:22 -05:00
Yi Sun f6e624d97b
target-i386: Add Intel SHA_NI instruction support.
Add SHA_NI feature bit. Its spec can be found at:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf

Backports commit 638cbd452d3a92a2ab18caee73078483d90f64eb from qemu
2018-03-01 10:52:54 -05:00
Paolo Bonzini 81ad780e5e
exec: introduce MemoryRegionCache
Device models often have to perform multiple access to a single
memory region that is known in advance, but would to use "DMA-style"
functions instead of address_space_map/unmap. This can happen
for example when the data has to undergo endianness conversion.
Introduce a new data structure to cache the result of
address_space_translate without forcing usage of a host address
like address_space_map does.

Backports commit 1f4e496e1fc2eb6c8bf377a0f9695930c380bfd3 from qemu
2018-03-01 10:50:30 -05:00
Paolo Bonzini 03a9bbb3d3
exec: introduce address_space_extend_translation
This extracts the common part of address_space_map and
address_space_cache_init into a new function.

Backports commit 715c31ec8e12107f47ac74b464c97e813c76f898 from qemu
2018-03-01 10:06:43 -05:00
Paolo Bonzini 88ad0f4f6e
exec: introduce memory_ldst.inc.c
Templatize the address_space_* and *_phys functions, so that we can add
similar functions in the next patch that work with a lightweight,
cache-like version of address_space_map/unmap.

Backports commit 0ce265ffef87f19f4dd1ff0663e09a63d66ae408 from qemu
2018-03-01 09:59:34 -05:00
Paolo Bonzini f3cc489a72
exec: optimize remaining address_space_* cases
Do them right before the next patch generalizes them into a multi-included
file.

Backports commit 2651efe7f5f9d6dc89c8e54d7d63952b7b22597d from qemu
2018-03-01 09:40:29 -05:00
Richard Henderson 0f94929fa7
target-arm: Fix aarch64 vec_reg_offset
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended. Fix this by adding
in the vfp.regs offset after computing the inter-register offset.

Backports commit d437262fa8edd0d9fbe038a515dda3dbf7c5bb54 from qemu
2018-03-01 09:36:03 -05:00
Richard Henderson ce9dca9c5e
target-arm: Fix aarch64 disas_ldst_single_struct
We add s->be_data within do_vec_ld/st. Adding it here means that
we have the wrong bits set in SIZE for a big-endian host, leading
to g_assert_not_reached in write_vec_element and read_vec_element.

Backports commit 74b13f92c2428abae41a61c46a5cf47545da5fcb from qemu
2018-03-01 09:34:34 -05:00
Paolo Bonzini 560515941a
target-i386: correctly propagate retaddr into SVM helpers
Commit 2afbdf8 ("target-i386: exception handling for memory helpers",
2015-09-15) changed tlb_fill's cpu_restore_state+raise_exception_err
to raise_exception_err_ra. After this change, the cpu_restore_state
and raise_exception_err's cpu_loop_exit are merged into
raise_exception_err_ra's cpu_loop_exit_restore.

This actually fixed some bugs, but when SVM is enabled there is a
second path from raise_exception_err_ra to cpu_loop_exit. This is
the VMEXIT path, and now cpu_vmexit is called without a
cpu_restore_state before.

The fix is to pass the retaddr to cpu_vmexit (via
cpu_svm_check_intercept_param). All helpers can now use GETPC() to pass
the correct retaddr, too.

Backports commit 823fb688ebc52a7d79c1308acb28c92b56820167 from qemu
2018-03-01 09:31:16 -05:00
Richard Henderson f6a72d4dca
target/sparc: Restore ldstub of odd asis
Fixes the booting of ss20 roms.

Backports commit f61f76cb3ff9fea6ecbcb9696ed82b3e2c5b7364 from qemu
2018-03-01 09:21:44 -05:00
Paolo Bonzini 9404dbf74e
cpu-exec: fix icount out-of-bounds access
When icount is active, tb_add_jump is surprisingly called with an
out of bounds basic block index. I have no idea how that can work,
but it does not seem like a good idea. Clear *last_tb for all
TB_EXIT_ICOUNT_EXPIRED cases, even when all you have to do is
refill icount_extra.

Backports commit d8dea6fbcbed177ca5d23ab77b3834a9437f0e88 from qemu
2018-03-01 09:17:26 -05:00
Richard Henderson 6820964e2f
tcg/aarch64: Fix tcg_out_movi
There were some patterns, like 0x0000_ffff_ffff_00ff, for which we
would select to begin a multi-insn sequence with MOVN, but would
fail to set the 0x0000 lane back from 0xffff.

Backports commit 50b468d42107a2c646b1c566ed17d9ec362c51c4 from qemu
2018-03-01 09:15:34 -05:00
Richard Henderson a03666f2f2
tcg/aarch64: Fix addsub2 for 0+C
When al == xzr, we cannot use addi/subi because that encodes xsp.
Force a zero into the temp register for that (rare) case.

Backports commit 028fbea47713f909d6ea761a457779a82b276247 from qemu
2018-03-01 09:13:54 -05:00
Roman Kapl 337f57dd2c
exec: Add missing rcu_read_unlock
rcu_read_unlock was not called if the address_space_access_valid result is
negative.

This caused (at least) a problem when qemu on PPC/E500+TAP failed to terminate
properly and instead got stuck in a deadlock.

Backports commit 662a97d74f9b34cafe9aeb6d96620a97d768a1fa from qemu
2018-03-01 09:12:27 -05:00
Peter Maydell 488b6cc82b
exec.c: Fix breakpoint invalidation race
A bug (1647683) was reported showing a crash when removing
breakpoints. The reproducer was bisected to 3359baad when tb_flush
was finally made thread safe. While in MTTCG the locking in
breakpoint_invalidate would have prevented any problems, but
currently tb_lock() is a NOP for system emulation.

The race is between a tb_flush from the gdbstub and the
tb_invalidate_phys_addr() in breakpoint_invalidate().

Ideally we'd have actual locking here; for the moment the
simple fix is to do a full tb_flush() for a bp invalidate,
since that is thread-safe even if no lock is taken.

Backports commit a9353fe897ca2687e5b3385ed39e3db3927a90e0 from qemu
2018-03-01 09:10:59 -05:00
Alex Bennée f4c65739f3
target-arm/translate-a64: fix gen_load_exclusive
While testing rth's latest TCG patches with risu I found ldaxp was
broken. Investigating further I found it was broken by 1dd089d0 when
the cmpxchg atomic work was merged. As part of that change the code
attempted to be clever by doing a single 64 bit load and then shuffle
the data around to set the two 32 bit registers.

As I couldn't quite follow the endian magic I've simply partially
reverted the change to the original code gen_load_exclusive code. This
doesn't affect the cmpxchg functionality as that is all done on in
gen_store_exclusive part which is untouched.

I've also restored the comment that was removed (with a slight tweak
to mention cmpxchg).

Backports commit 5460da501a57cd72eda6fec736d76539122e2f99 from qemu
2018-03-01 09:09:16 -05:00
Marc-André Lureau b0e5d04813
qapi: add missing colon-ending for section name
The documentation parser we are going to add expects a section name to
end with ':', otherwise the comment is treated as free-form text body.

Backports commit 5072f7b38b1b9b26b8fbe1a89086386a420aded8 from qemu
2018-03-01 09:07:10 -05:00