Commit graph

46 commits

Author SHA1 Message Date
Richard Henderson 5790c1648d
target/mips: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace mips_env_get_cpu with env_archcpu. The combination
CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Backports commit 5a7330b35cabc9e2fd3a8577b7004b63af8c57f3 from qemu
2019-06-12 11:55:43 -04:00
Richard Henderson fbf91a6535
cpu: Replace ENV_GET_CPU with env_cpu
Now that we have both ArchCPU and CPUArchState, we can define
this generically instead of via macro in each target's cpu.h.

Backports commit 29a0af618ddd21f55df5753c3e16b0625f534b3c from qemu
2019-06-12 11:16:16 -04:00
Richard Henderson ae94fb5992
cpu: Define ArchCPU
For all targets, do this just before including exec/cpu-all.h.

Backports commit 2161a612b4e1d388046320bc464adefd6bba01a0 from qemu
2019-06-12 11:08:39 -04:00
Richard Henderson e3f1f25996
cpu: Define CPUArchState with typedef
For all targets, do this just before including exec/cpu-all.h.

Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu
2019-06-12 11:06:36 -04:00
Richard Henderson df2a890bd7
tcg: Split out target/arch/cpu-param.h
For all targets, into this new file move TARGET_LONG_BITS,
TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS,
TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.

Include this new file from exec/cpu-defs.h.

This now removes the somewhat odd requirement that target/arch/cpu.h
defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the
bulk of the includes within target/arch/cpu.h to the top.

Backports commit 74433bf083b0766aba81534f92de13194f23ff3e from qemu
2019-06-10 19:35:46 -04:00
Jules Irenge 9c7f2f2e78
target/mips: realign comments to fix checkpatch warnings
Realign comments to fix warnings issued by checkpatc.pl tool
"WARNING: Block comments use a leading /* on a separate line"
within "target/mips/cpu.h" file.

Backports commit 9e72f33d854b0a817c0d2fe4bca693b76f0fe776 from qemu
2019-05-28 19:49:59 -04:00
Jules Irenge cf39970750
target/mips: add or remove space to fix checkpatch errors
Add or remove space to fix errors issued by checkpatch.pl tool
"ERROR: spaces required around that..."
"ERROR: space required after that..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that..."
"ERROR: space prohibited between function name and open parenthesis"
"ERROR: code indent should never use tabs"
"ERROR: line over 90 characters"
within "target/mips/cpu.h" file.

Backports commit 8ebf2e1a68408068c0bcd0d02a783fd12f6a9cb5 from qemu
2019-05-28 19:48:11 -04:00
Leon Alrae 6099733fc5
target/mips: reimplement SC instruction emulation and use cmpxchg
Completely rewrite conditional stores handling. Use cmpxchg.

This eliminates need for separate implementations of SC instruction
emulation for user and system emulation.

Backports commit 33a07fa2db66376e6ee780d4a8b064dc5118cf34 from qemu
2019-02-15 17:10:16 -05:00
Leon Alrae df67716ed5
target/mips: compare virtual addresses in LL/SC sequence
Do only virtual addresses comaprisons in LL/SC sequence emulations.

Until this patch, physical addresses had been compared in SC part of
LL/SC sequence, even though such comparisons could be avoided. Getting
rid of them allows throwing away SC helpers and having common SC
implementations in user and system mode, avoiding the need for two
separate implementations selected by #ifdef CONFIG_USER_ONLY.

Correct guest software should not rely on LL/SC if they accesses the
same physical address via different virtual addresses or if page
mapping gets changed between LL/SC due to manipulating TLB entries.
MIPS Instruction Set Manual clearly says that an RMW sequence must
use the same address in the LL and SC (virtual address, physical
address, cacheability and coherency attributes must be identical).
Otherwise, the result of the SC is not predictable. This patch takes
advantage of this fact and removes the virtual->physical address
translation from SC helper.

lladdr served as Coprocessor 0 LLAddr register which captures physical
address of the most recent LL instruction, and also lladdr was used
for comparison with following SC physical address. This patch changes
the meaning of lladdr - now it will only keep the virtual address of
the most recent LL. Additionally, CP0_LLAddr field is introduced which
is the actual Coperocessor 0 LLAddr register that guest can access.

Backports commit c7c7e1e9a5e3f0a8a1dbff6e4ccfd21c2dc9f845 from qemu
2019-02-15 16:59:40 -05:00
Aleksandar Markovic 49e7e28ec9
target/mips: Correct the second argument type of cpu_supports_isa()
"insn_flags" bitfield was expanded from 32-bit to 64-bit in commit
f9c9cd63e3. However, this was not reflected on the second argument
of the function cpu_supports_isa(). By chance, this did not create
some wrong behavior, since the left-most halves of all instances of
the second argument are currently all zeros. However, this is still
a bug waiting to happen. Correct this by changing the type of the
second argument to be always 64-bit.

Backports commit 5b1e098128367d6ef7cb2d1e99a55fcf4fa9cdde from qemu
2019-01-25 12:45:21 -05:00
Lioncash 29d84a9296
target: Resolve repeated typedef warnings 2019-01-22 20:27:35 -05:00
Fredrik Noring baf2fe0fc1
target/mips: Introduce 32 R5900 multimedia registers
The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Backports commit a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd from qemu
2019-01-22 20:14:56 -05:00
Aleksandar Markovic 591ec2a44f
target/mips: Add CP0 register MemoryMapID
Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.

Backports commit 3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60 from qemu
2019-01-22 19:56:08 -05:00
Aleksandar Markovic 3a276522ac
target/mips: Amend preprocessor constants for CP0 registers
Correct existing CP0-related preprocessor constants (replace
"CPO" with "CP0" (form letter "O" to digit "0", when needed).
Besides, add preprocessor constants for CP0 subregisters.
The names of the subregisters were chosen to be in sync with
the table of corresponding assembler mnemonics found in the
documentation for I6500 and I6400 (release 1.0).

Backports commit 04992c8cd1c43ecdba39dd8c916db092db6ebae0 from qemu
2019-01-22 19:55:04 -05:00
Yongbok Kim 33e9ea3f10
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
Provide R/W access to SAARI and SAAR CP0 registers.

Backports commit 5fb2dcd17921be71b55fb62d59a12992707d2d3e from qemu
2019-01-22 19:51:38 -05:00
Yongbok Kim 6f850b88e4
target/mips: Add fields for SAARI and SAAR CP0 registers
Add fields for SAARI and SAAR CP0 registers.

Backports commit 167db30e981cd72bef15182178037e51afc8e40d from qemu
2019-01-22 19:40:31 -05:00
Aleksandar Markovic 0feca79dd5
target/mips: Add preprocessor constants for 32 major CP0 registers
Add preprocessor constants for 32 major CP0 registers.

Backports commit efd27d3f08655fc2bcf79a529566aee2cb2e81f8 from qemu
2019-01-22 19:22:39 -05:00
Aleksandar Markovic 9834762d2c
target/mips: Move comment containing summary of CP0 registers
Move comment containing summary of CP0 registers. Checkpatch
script reported some tabs in the resutling diff, so convert
these tabs to spaces too.

Backports commit ea9c5e836e205a87038c8153282d0b6d9234cda2 from qemu
2019-01-22 19:19:54 -05:00
Craig Janeczek 58dc377890
target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Backports commit eb5559f67dc8dc12335dd996877bb6daaea32eb2 from qemu.
2018-11-11 05:50:52 -05:00
Yongbok Kim a35a59bda6
target/mips: Add CP0 PWCtl register
Add PWCtl register (CP0 Register 5, Select 6).

The PWCtl register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

PWEn (31) - Hardware Page Table walker enable
PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only)
XK (28) - If 1, walker handles xkseg (MIPS64 only)
XS (27) - If 1, walker handles xsseg (MIPS64 only)
XU (26) - If 1, walker handles xuseg (MIPS64 only)
DPH (7) - Dual Page format of Huge Page support
HugePg (6) - Huge Page PTE supported in Directory levels
PSn (5..0) - Bit position of PTEvld in Huge Page PTE

Backports commit 103be64c26c166f12b3e1308edadef3443723ff1 from qemu
2018-10-23 14:23:04 -04:00
Yongbok Kim a5194f6dfc
target/mips: Add CP0 PWSize register
Add PWSize register (CP0 Register 5, Select 7).

The PWSize register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

BDW (37..32) Base Directory index width (MIPS64 only)
GDW (29..24) Global Directory index width
UDW (23..18) Upper Directory index width
MDW (17..12) Middle Directory index width
PTW (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index

Backports commit 20b28ebc49945583d7191b57755cfd92433de9ff from qemu
2018-10-23 14:08:55 -04:00
Yongbok Kim 0597704314
target/mips: Add CP0 PWField register
Add PWField register (CP0 Register 5, Select 6).

The PWField register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

MIPS64:
BDI (37..32) - Base Directory index
GDI (29..24) - Global Directory index
UDI (23..18) - Upper Directory index
MDI (17..12) - Middle Directory index
PTI (11..6 ) - Page Table index
PTEI ( 5..0 ) - Page Table Entry shift

MIPS32:
GDW (29..24) - Global Directory index
UDW (23..18) - Upper Directory index
MDW (17..12) - Middle Directory index
PTW (11..6 ) - Page Table index
PTEW ( 5..0 ) - Page Table Entry shift

Backports commit fa75ad1459f4f6abbeb6d375a812dfad61320f58 from qemu
2018-10-23 13:52:31 -04:00
Yongbok Kim 2414d1fe05
target/mips: Add CP0 PWBase register
Add PWBase register (CP0 Register 5, Select 5).

The PWBase register contains the Page Table Base virtual address.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.

Backports commit 5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6 from qemu
2018-10-23 13:47:49 -04:00
Stefan Markovic 64bec62433
target/mips: Improve DSP R2/R3-related naming
Do following replacements:

ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2
MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()

and several other similar minor replacements.

Backports commit 908f6be1b9cbc270470230f805d6f7474ab3178d from qemu
2018-10-23 13:42:01 -04:00
Stefan Markovic 6dd29739a9
target/mips: Add availability control for DSP R3 ASE
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.

Backports commit 59e781fbf13a2dede15437d055b09d7ea120dcac from qemu
2018-10-23 13:36:07 -04:00
Philippe Mathieu-Daudé 055b2e4bdc
target/mips: Increase 'supported ISAs/ASEs' flag holder size
Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.

Backports commit f9c9cd63e3dd84c5f052deec880ec92046bbe305 from qemu
2018-10-23 13:17:08 -04:00
Aleksandar Markovic 2cf0f05c27
target/mips: Add a comment before each CP0 register section in cpu.h
Add a comment before each CP0 register section in CPUMIPSState
definition, thus visually separating these sections.

Backports commit 50e7edc5ac25af2faaacd1f91e177c7de7d696c3 from qemu
2018-10-23 13:12:04 -04:00
Aleksandar Markovic d9ae47e2da
target/mips: Add a comment with an overview of CP0 registers
Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.

Backports commit a86d421e18d58b32d6eaba1e79160e2b4e5a0a6c from qemu
2018-10-23 13:06:39 -04:00
Aleksandar Rikalo 371bb5a134
target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside
adding core functionality of these instructions, this patch adds
support for availability control via configuration bit XNP.

Backports commit 0b16dcd180bdbe3add9edea42c2374d427882661 from qemu
2018-08-27 05:25:14 -04:00
Stefan Markovic 4b6a9ce61b
target/mips: Add CP0 BadInstrX register
Add CP0 BadInstrX register. This register will be used in nanoMIPS.

Backports commit 25beba9bf76a677747b779e997c6540677a38311 from qemu
2018-08-17 14:22:02 -04:00
Aleksandar Markovic d70a2c1df1
target/mips: Update some CP0 registers bit definitions
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.

Some of these bits will be utilized by upcoming nanoMIPS changes.

Backports commit 0413d7a55a8161ebd33541ba1df4285bf180c583 from qemu
2018-08-17 14:21:18 -04:00
Igor Mammedov cd27da0d88
cpu: get rid of unused cpu_init() defines
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so
no users are left, remove it.

Backports commit 3f71e724e283233753f1b5b3d6a30948d3084636 from qemu
2018-03-20 14:21:45 -04:00
Igor Mammedov f86355f82c
cpu: add CPU_RESOLVING_TYPE macro
it will be used for providing to cpu name resolving class for
parsing cpu model for system and user emulation code.

Along with change add target to null-machine tests, so
that when switch to CPU_RESOLVING_TYPE happens,
it would ensure that null-machine usecase still works.

Backports commit 0dacec874fa3b3fd34b0d0670fa257efdcbbebd0 from qemu
2018-03-20 11:28:13 -04:00
Eduardo Habkost 074865ff98
cpu: Generify CPU init functions
Backports commits 2994fd96d986578a342f2342501b4ad30f6d0a85,
701e3c78ce45fa630ffc6826c4b9a4218954bc7f, and
d1853231c60d16af78cf4d1608d043614bfbac0b from qemuu
2018-03-20 08:21:51 -04:00
Peter Crosthwaite ce1831bfb4
target-*: Don't redefine cpu_exec()
This function needs to be converted to QOM hook and virtualised for
multi-arch. This rename interferes, as cpu-qom will not have access
to the renaming causing name divergence. This rename doesn't really do
anything anyway so just delete it.

Backports commit 8642c1b81e0418df066a7960a7426d85a923a253 from qemu
2018-03-20 07:02:47 -04:00
Lioncash 95d50a02a1
target/mips/translate: Perform comparison pass with qemu
Keeps code and formatting in sync
2018-03-12 17:52:56 -04:00
Igor Mammedov 00d52414c1
mips: replace cpu_mips_init() with cpu_generic_init()
now cpu_mips_init() reimplements subset of cpu_generic_init()
tasks, so just drop it and use cpu_generic_init() directly.

Backports commit c4c8146cfd0fc3f95418fbc82a2eded594675022 from qemu
2018-03-05 00:49:10 -05:00
Philippe Mathieu-Daudé c4f351394f
mips: introduce internal.h and cleanup cpu.h
no logical change, only code movement (and fix a comment typo).

Backports commit 26aa3d9aecbb6fe9bce808a1d127191bdf3cc3d2 from qemu
Also backports commit 5502b66fc7d0bebd08b9b7017cb7e8b5261c3a2d
2018-03-05 00:25:56 -05:00
James Hogan ddbea9422c
target/mips: Add segmentation control registers
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
CP0_SegCtl2 control the behaviour and required privilege of the legacy
virtual memory segments.

Add them to the CP0 interface so they can be read and written when
CP0_Config3.SC=1, and initialise them to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.

Backports commit cec56a733dd2c3fa81dbedbecf03922258747f7d from qemu
2018-03-04 01:00:42 -05:00
James Hogan 7e9b84ca1a
target/mips: Add an MMU mode for ERL
The segmentation control feature allows a legacy memory segment to
become unmapped uncached at error level (according to CP0_Status.ERL),
and in fact the user segment is already treated in this way by QEMU.

Add a new MMU mode for this state so that QEMU's mappings don't persist
between ERL=0 and ERL=1.

Backports commit 42c86612d507c2a8789f2b8d920a244693c4ef7b from qemu
2018-03-04 00:47:19 -05:00
James Hogan f285157856
target/mips: Abstract mmu_idx from hflags
The MIPS mmu_idx is sometimes calculated from hflags without an env
pointer available as cpu_mmu_index() requires.

Create a common hflags_mmu_index() for the purpose of this calculation
which can operate on any hflags, not just with an env pointer, and
update cpu_mmu_index() itself and gen_intermediate_code() to use it.

Also update debug_post_eret() and helper_mtc0_status() to log the MMU
mode with the status change (SM, UM, or nothing for kernel mode) based
on cpu_mmu_index() rather than directly testing hflags.

This will also allow the logic to be more easily updated when a new MMU
mode is added.

Backports commit b0fc6003224543d2bdb172eca752656a6223e4a1 from qemu
2018-03-04 00:45:00 -05:00
Leon Alrae 8fadc55db3
target-mips: make ITC Configuration Tags accessible to the CPU
Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv
processors these bits are used to enable CACHE instruction access to
different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will
access ITC tag values.

Generally we do not model caches and we have been treating the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.

Backports commit 0d74a222c27e26fc40f4f6120c61c3f9ceaa3776 from qemu
2018-03-04 00:34:30 -05:00
James Hogan 152323fe35
target/mips: Add CP0_Ebase.WG (write gate) support
Add support for the CP0_EBase.WG bit, which allows upper bits to be
written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
CP0_Config5.CV bit to control whether the exception vector for Cache
Error exceptions is forced into KSeg1.

This is necessary on MIPS32 to support Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).

It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.

Backports commit 74dbf824a1313b6064bbebb981a7440951d70896 from qemu
2018-03-03 23:55:09 -05:00
Paul Burton 411ddd16cf
target-mips: Provide function to test if a CPU supports an ISA
Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.

An example use of this is to allow boards which generate bootloader code
to determine the properties of the CPU that will be used, for example
whether the CPU is 64 bit or which architecture revision it implements.

Backports commit bed9e5ceb158c886d548fe59675a6eba18baeaeb from qemu
2018-03-02 08:20:19 -05:00
Lioncash ebae552174
mips: Build fix 2018-03-01 22:56:23 -05:00
Thomas Huth b2f1326437
Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu
2018-03-01 22:50:58 -05:00
Renamed from qemu/target-mips/cpu.h (Browse further)