Commit graph

330 commits

Author SHA1 Message Date
Lioncash 704353c758 mips: Fix build 2021-03-05 08:51:51 -05:00
Claudio Fontana ddfed5f3a6 cpu: move do_unaligned_access to tcg_ops
make it consistently SOFTMMU-only.

Backports 8535dd702dd054a37a85e0c7971cfb43cc7b50e3
2021-03-04 17:20:02 -05:00
Claudio Fontana ec08ac4995 cpu: move cc->transaction_failed to tcg_ops
Backports cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c
2021-03-04 17:16:41 -05:00
Claudio Fontana ee73443c7d cpu: move cc->do_interrupt to tcg_ops
Backports 0545608056a6161e7020cd7b9368d9636fa80051
2021-03-04 17:10:14 -05:00
Eduardo Habkost 76a10fa8e0 cpu: Move tlb_fill to tcg_ops
Backports e124536f37377cff5d68925d4976ad604d0ebf3a
2021-03-04 17:01:55 -05:00
Eduardo Habkost 03cc62e39c cpu: Move cpu_exec_* to tcg_ops
Backports 48c1a3e303b5a2cca48679645ad3fbb914db741a
2021-03-04 16:56:55 -05:00
Eduardo Habkost eb38ac1809 cpu: Move synchronize_from_tb() to tcg_ops
Backports ec62595bab1873c48a34849de70011093177e769
2021-03-04 16:48:27 -05:00
Eduardo Habkost b9b711afe3 cpu: Introduce TCGCpuOperations struct
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().

The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.

Backports e9e51b7154404efc9af8735ab87c658a9c434cfd
2021-03-04 16:38:25 -05:00
Huacai Chen 504946fb79 target/mips: Support variable page size
Traditionally, MIPS use 4KB page size, but Loongson prefer 16KB page
size in system emulator. So, let's define TARGET_PAGE_BITS_VARY and
TARGET_PAGE_BITS_MIN to support variable page size.

Backports commit ee3863b9d414f0b4a59a88f2a79b496a99d4f6dd from qemu
2020-06-14 21:09:51 -04:00
Richard Henderson a417227674 softfloat: Replace flag with bool
We have had this on the to-do list for quite some time.

Backports commit c120391c0090d9c40425c92cdb00f38ea8588ff6 from qemu
2020-05-21 17:48:12 -04:00
Jiaxun Yang 5ca33a4aaa target/mips: Fix loongson multimedia condition instructions
Loongson multimedia condition instructions were previously implemented as
write 0 to rd due to lack of documentation. So I just confirmed with Loongson
about their encoding and implemented them correctly.

Backports commit 84878f4c00a7beca1d1460e2f77a6c833b8d0393 from qemu
2020-04-30 07:14:10 -04:00
Alex Bennée ced8834737 target/arm: fix TCG leak for fcvt half->double
When support for the AHP flag was added we inexplicably only freed the
new temps in one of the two legs. Move those tcg_temp_free to the same
level as the allocation to fix that leak.

Backports commit aeab8e5eb220cc5ff84b0b68b9afccc611bf0fcd from qemu
2020-03-21 13:14:47 -04:00
Yongbok Kim 7fbc373f59 target/mips: Add implementation of GINVT instruction
Implement emulation of GINVT instruction. As QEMU doesn't support
caches and virtualization, this implementation covers only one
instruction (GINVT - Global Invalidate TLB) among all TLB-related
MIPS instructions.

Backports commit 99029be1c2875cd857614397674bbf563ddb6f91 from qemu
2020-03-21 13:01:35 -04:00
Yongbok Kim f10de71e73 target/mips: Amend CP0 WatchHi register implementation
WatchHi is extended by the field MemoryMapID with the GINVT instruction.
The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/
DMFC0 in 64-bit architectures.

Backports commit feafe82cc2289a31b3e3f11dc76f3539ea22d670 from qemu
2020-03-21 12:39:00 -04:00
Tony Nguyen cb5688009e target/mips: Hard code size with MO_{8|16|32|64}
Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".

Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.

Backports commit 4574664677116dedb29b12150137f3888374a857 from qemu
2020-01-07 18:30:39 -05:00
Tony Nguyen 7e9a1641c2 target/mips: Access MemoryRegion with MemOp
The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Backports commit e501824b3f3b3650e7cb8a509064cac01bc27c82 from qemu
2020-01-07 18:21:31 -05:00
Tony Nguyen f75368cd0f
tcg: TCGMemOp is now accelerator independent MemOp
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Backports commit 14776ab5a12972ea439c7fb2203a4c15a09094b4 from qemu
2019-11-28 03:01:12 -05:00
Peter Maydell 2faffb5af1
target/mips: Switch to do_transaction_failed() hook
Switch the MIPS target from the old unassigned_access hook to the new
do_transaction_failed hook.

Unlike the old hook, do_transaction_failed is only ever called from
the TCG memory access paths, so there is no need for the "ignore this
if we're using KVM" hack that we were previously using to work around
the way unassigned_access was called for all kinds of memory accesses
to unassigned physical addresses.

The MIPS target does not ever do direct memory reads by physical
address (via either ldl_phys etc or address_space_ldl etc), so the
only memory accesses this affects are the 'normal' guest loads and
stores, which will be handled by the new hook; their behaviour is
unchanged.

Backports commit 4f02a06d50ef0081089ed8cb3ec7c7986e3c95f8 from qemu
2019-11-28 02:54:53 -05:00
Aleksandar Markovic 32457b2b37
target/mips: Fix emulation of ST.W in system mode
Order of arguments in helper_ret_stl_mmu() invocations was wrong,
apparently caused by a misplaced multiline copy-and-paste.

Fixes: 6decc57 ("target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host")

Backports commit abd4393d769d9fe2333b2e83e00f911a78475943 from qemu
2019-11-18 23:47:33 -05:00
Aleksandar Markovic 84ec43131c
target/mips: Clean up handling of CP0 register 31
Clean up handling of CP0 register 31.

Backports commit 14d92efd721755cc31df328261d301177980fa89 from qemu
2019-11-18 23:46:33 -05:00
Aleksandar Markovic d012faa9bf
target/mips: Clean up handling of CP0 register 30
Clean up handling of CP0 register 30.

Backports commit 4bcf121ebb009db8d135d8819b8d5837cfd6bb37 from qemu
2019-11-18 23:43:56 -05:00
Aleksandar Markovic 6fae1432ce
target/mips: Clean up handling of CP0 register 29
Clean up handling of CP0 register 29.

Backports commit af4bb6da80d3f6c733055bb4e2a1b99a30e81d24 from qemu
2019-11-18 23:43:11 -05:00
Aleksandar Markovic 7dc128c3ad
target/mips: Clean up handling of CP0 register 28
Clean up handling of CP0 register 28.

Backports commit a30e2f218034f6215757734c8107fd47f5385dfa from qemu
2019-11-18 23:40:48 -05:00
Aleksandar Markovic 9ed9ff06ab
target/mips: Clean up handling of CP0 register 27
Clean up handling of CP0 register 27.

Backports commit 5a10873d7ddd5d84c38c6f0dd69116b93219a7c1 from qemu
2019-11-18 23:38:00 -05:00
Aleksandar Markovic 9fe6520144
target/mips: Clean up handling of CP0 register 26
Clean up handling of CP0 register 26.

Backports commit dbbf08b2892a7cf93e47f84c512953234a452cec from qemu
2019-11-18 23:37:02 -05:00
Aleksandar Markovic 7f23faefa3
target/mips: Clean up handling of CP0 register 25
Clean up handling of CP0 register 25.

Backports commit 1176b328c310dbc71501f370fe128786edc7609c from qemu
2019-11-18 23:36:02 -05:00
Aleksandar Markovic d7b34101a0
target/mips: Clean up handling of CP0 register 24
Clean up handling of CP0 register 24.

Backports commit 8d7b4b6efbab8b5286aa9f5948d3e2ce9f98aea5 from qemu
2019-11-18 23:31:37 -05:00
Aleksandar Markovic 4626d0d314
target/mips: Clean up handling of CP0 register 23
Clean up handling of CP0 register 23.

Backports commit 4cbf4b6d00aa27176f1a19b3c739423875d702fe from qemu
2019-11-18 23:30:52 -05:00
Aleksandar Markovic 6d070f1346
target/mips: Clean up handling of CP0 register 20
Clean up handling of CP0 register 20.

Backports commit 14f92b0b9ca0abe48f9a23a73e8dc413d919eab9 from qemu
2019-11-18 23:22:56 -05:00
Aleksandar Markovic 462d062240
target/mips: Clean up handling of CP0 register 19
Clean up handling of CP0 register 19.

Backports commit be274dc18ee3682bb3a2ba7e5ccd3061b103cbec from qemu
2019-11-18 23:22:07 -05:00
Aleksandar Markovic e126751cdc
target/mips: Clean up handling of CP0 register 18
Clean up handling of CP0 register 18.

Backports commit e8dcfe825a51c5e963813343ec4112f06a0acf68 from qemu
2019-11-18 23:21:19 -05:00
Aleksandar Markovic 0424d7bd24
target/mips: Clean up handling of CP0 register 17
Clean up handling of CP0 register 17.

Backports commit 706ce142056b1304ea21db53b73d128295771a71 from qemu
2019-11-18 23:18:16 -05:00
Aleksandar Markovic 04de1c3a5e
target/mips: Clean up handling of CP0 register 16
Clean up handling of CP0 register 16.

Backports commit 433efb4cca1d942b6849be953ea166b492e9bb59 from qemu
2019-11-18 23:14:41 -05:00
Aleksandar Markovic e54d2617a1
target/mips: Clean up handling of CP0 register 15
Clean up handling of CP0 register 15.

Backports commit 4466cd49e53d3a4418a0f27ea9ff335fd9aed180 from qemu
2019-11-18 23:11:46 -05:00
Aleksandar Markovic 41133450de
target/mips: Clean up handling of CP0 register 14
Clean up handling of CP0 register 14.

Backports commit 35e4b54d90b07736d24d736c50f236231cde929f from qemu
2019-11-18 23:10:19 -05:00
Aleksandar Markovic dc1e7c4467
target/mips: Clean up handling of CP0 register 13
Clean up handling of CP0 register 13.

Backports commit e3c7559d8902fbb9857fb94fc5391f258cc3c4d1 from qemu
2019-11-18 23:08:20 -05:00
Aleksandar Markovic 3f76658fd8
target/mips: Clean up handling of CP0 register 12
Clean up handling of CP0 register 12.

Backports commit 2b0848674b4143bf5b2b6f7de6b8587dd52c31dd from qemu
2019-11-18 23:06:38 -05:00
Aleksandar Markovic 5812937c52
target/mips: Clean up handling of CP0 register 11
Clean up handling of CP0 register 11.

Backports commit f5f3834ff0f7d237fa9d5c67544ae5f5d49eaaf7 from qemu
2019-11-18 23:04:18 -05:00
Aleksandar Markovic 16e817b003
target/mips: Clean up handling of CP0 register 10
Clean up handling of CP0 register 10.

Backports commit 860ffef0477a92f1944f10528887fa5e74e6535d from qemu
2019-11-18 23:03:25 -05:00
Aleksandar Markovic 11d02fc0b7
target/mips: Clean up handling of CP0 register 9
Clean up handling of CP0 register 9.

Backports commit e5a98a7232e10632032be8f896ce0aaf171b6fd5 from qemu
2019-11-18 23:01:54 -05:00
Aleksandar Markovic f4015517ab
target/mips: Clean up handling of CP0 register 8
Clean up handling of CP0 register 8.

Backports commit 67d167d2d83d059932c99c077b402b94339c8cf0 from qemu
2019-11-18 22:59:32 -05:00
Aleksandar Markovic 38f0e31950
target/mips: Clean up handling of CP0 register 7
Clean up handling of CP0 register 7.

Backports commit 143a9875e51a358924154ffa76135ca29415dfb5 from qemu
2019-11-18 22:55:22 -05:00
Aleksandar Markovic 95fa7aae61
target/mips: Clean up handling of CP0 register 6
Clean up handling of CP0 register 6.

Backports commit 9023594b4081585518faf9b144bce62067381990 from qemu
2019-11-18 22:54:26 -05:00
Aleksandar Markovic 49eeba113e
target/mips: Clean up handling of CP0 register 5
Clean up handling of CP0 register 5.

Backports commit a1e76353e389f93e63bf1175c8422e5e7759662e from qemu
2019-11-18 22:51:19 -05:00
Aleksandar Markovic 11ac98331a
target/mips: Clean up handling of CP0 register 4
Clean up handling of CP0 register 4.

Backports commit 020fe379093deb116d72174268335d60133f0e26 from qemu
2019-11-18 22:46:46 -05:00
Aleksandar Markovic d96b3d06c4
target/mips: Clean up handling of CP0 register 3
Clean up handling of CP0 register 3.

Backports commit acd3731632c5737eaeb230d76fd55ce871a33439 from qemu
2019-11-18 22:42:17 -05:00
Aleksandar Markovic 8644845898
target/mips: Clean up handling of CP0 register 2
Clean up handling of CP0 register 2.

Backports commit 6d27d5bd73489a0560a6613e2b5633e221999db9 from qemu
2019-11-18 22:38:46 -05:00
Aleksandar Markovic 9450b71a13
target/mips: Clean up handling of CP0 register 1
Clean up handling of CP0 register 1

Backports commit 30deb4605bf0bb4cc0682216002dfed738bd5700 from qemu
2019-11-18 22:33:29 -05:00
Aleksandar Markovic 47adeabf87
target/mips: Clean up handling of CP0 register 0
Clean up handling of CP0 register 0.

Backports commit 1b142da5f82a8fcdc7783a418592de654d5c6052 from qemu
2019-11-18 22:25:31 -05:00
tony.nguyen@bt.com b4c2c94602
configure: Define target access alignment in configure
This patch moves the define of target access alignment earlier from
target/foo/cpu.h to configure.

Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now
accelerator independent MemOp"

Backports commit 52bf9771fdfce98e98cea36a17a18915be6f6b7f from qemu
2019-11-18 21:41:35 -05:00