1840 commits

Author	SHA1	Message	Date
Lioncash	f62664948e	target-mips: Make 'helper_float_cvtw_s' consistent with the remaining helpers ... Move the call to `update_fcr31' in `helper_float_cvtw_s' after the exception flag check, for consistency with the remaining helpers that do it last too. Backports commit 2b09f94cdbf5c54e2278d7f3aed2eceff3494790 from qemu	2018-02-11 16:02:38 -05:00
Maciej W. Rozycki	0f82a7f89f	target-mips: assorted formatting fixes ... Backports commits d75de74967f631a7d0b538d4b88f96f9c426bfe2, 6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85, and d2bfa6e6222baa0218bd0658499d38bac56ac34c from qemu	2018-02-11 16:01:23 -05:00
Maciej W. Rozycki	ca496991ea	target-mips: Enable vectored interrupt support for the 74Kf CPU ... Enable vectored interrupt support for the 74Kf CPU, reflecting hardware. Backports commit 4386f08767240080334539ac0b07a8bfe30bffe9 from qemu	2018-02-11 15:57:17 -05:00
Maciej W. Rozycki	338e34290d	target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors ... Add the M14K and M14Kc processors from MIPS Technologies that are the original implementation of the microMIPS ISA. They are dual instruction set processors, implementing both the microMIPS and the standard MIPSr32 ISA. These processors correspond to the M4K and 4KEc CPUs respectively, except with support for the microMIPS instruction set added, support for the MCU ASE added and two extra interrupt lines, making a total of 8 hardware interrupts plus 2 software interrupts. The remaining parts of the microarchitecture, in particular the pipeline, stayed unchanged. The presence of the microMIPS ASE is is reflected in the configuration added. We currently have no support for the MCU ASE, including in particular the ACLR, ASET and IRET instructions in either encoding, and we have no support for the extra interrupt lines, including bits in CP0.Status and CP0.Cause registers, so these features are not marked, making our support diverge from real hardware. Backports commit 11f5ea105c06bec72e9bc9a700fa65d60afb5ec3 from qemu	2018-02-11 15:56:28 -05:00
Lioncash	833b0ff964	target-mips: Make CP0.Config4 and CP0.Config5 registers signed ... Make the data type used for the CP0.Config4 and CP0.Config5 registers and their mask signed, for consistency with the remaining 32-bit CP0 registers, like CP0.Config0, etc. Backports commit 8280b12c0e4b515d707509dde4ddde05d9bda4ef from qemu	2018-02-11 15:48:10 -05:00
Maciej W. Rozycki	5eea73c534	target-mips: Add 5KEc and 5KEf MIPS64r2 processors ... Add the 5KEc and 5KEf processors from MIPS Technologies that are the original implementation of the MIPS64r2 ISA. Silicon for these processors has never been taped out and no soft cores were released even. They do exist though, a CP0.PRId value has been assigned and experimental RTLs produced at the time the MIPS64r2 ISA has been finalized. The settings introduced here faithfully reproduce that hardware. As far the implementation goes these processors are the same as the 5Kc and the 5Kf CPUs respectively, except implementing the MIPS64r2 rather than the original MIPS64 instruction set. There must have been some updates to the CP0 architecture as mandated by the ISA, such as the addition of the EBase register, although I am not sure about the exact details, no documentation has ever been produced for these processors. The remaining parts of the microarchitecture, in particular the pipeline, stayed unchanged. Or to put it another way, the difference between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE CPU, except for the 64-bit rather than 32-bit ISA. Backports commit 36b86e0dc2be93fc538fe7e11e0fda1a198f0135 from qemu	2018-02-11 15:47:13 -05:00
Richard Henderson	2c091e5fb8	target-arm: Add condexec state to insn_start ... Backports commit 52e971d9ff67e340ac2a86bd67e14bd31c7991e0 from qemu	2018-02-11 15:13:40 -05:00
Richard Henderson	3f9502dc8b	tcg: Allow extra data to be attached to insn_start ... With an eye toward having this data replace the gen_opc_* arrays that each target collects in order to enable restore_state_from_tb. Backports commit 9aef40ed1f6e2bd794bbb3ba8c8b773e506334c9 from qemu	2018-02-11 13:03:51 -05:00
Richard Henderson	dd1ec408e5	target-*: Increment num_insns immediately after tcg_gen_insn_start ... This does tidy the icount test common to all targets. Backports commit 959082fc4a93a016a6b697e1e0c2b373d8a3a373 from qemu	2018-02-11 12:46:30 -05:00
Richard Henderson	a64d0ff657	target-*: Unconditionally emit tcg_gen_insn_start ... While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Backports commit 667b8e29c5b1d8c5b4e6ad5f780ca60914eb6e96 from qemu	2018-02-11 12:41:20 -05:00
Lioncash	b3f9ff667b	tcg: Rename debug_insn_start to insn_start ... With an eye toward making it mandatory. Backports commit 765b842adec4c5a359e69ca08785553599f71496 from qemu	2018-02-11 12:34:01 -05:00
Richard Henderson	77b03e0973	target-i386: Make check_hw_breakpoints static ... The function is now only used from within a single file. Backports commit dd941cdcfec536aad6a310a153778142ed9f3e92 from qemu	2018-02-11 12:28:08 -05:00
Richard Henderson	10e0920fa0	target-i386: Move breakpoint related functions to new file ... Backports commit ba4b5c65a98ea91dc3b13e42dd9404808c999dda from qemu	2018-02-11 12:25:24 -05:00
Lioncash	fb2fe4580f	optimize: Add missing extrh/extrl case	2018-02-11 02:57:55 -05:00
Lioncash	3791fc69fd	target-arm: Use new revbit functions ... Backports commit 42fedbca8f5b54324ed89be3484d4a3dc9946387 from qemu	2018-02-11 02:57:55 -05:00
Richard Henderson	a5d6a31d69	host-utils: Add revbit functions ... Backports commit 652a4b7e736f432a6809d1d2b52d169ab0b9aa3b from qemu.	2018-02-11 02:57:55 -05:00
Richard Henderson	eb5ed2a844	target-arm: Use tcg_gen_extrh_i64_i32 ... Usually, eliminate an operation from the translator by combining a shift with an extract. In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF, merely a non-zero value. Given that we can extract both halves of a 64-bit input in one call, this simplifies the code. Backports commit 7cb36e18b2f1c1f971ebdc2121de22a8c2e94fd6 from qemu	2018-02-11 02:57:54 -05:00
Richard Henderson	b94da3fc13	target-arm: Recognize ROR ... Backports commit 8fb0ad8e16ab3d03433244a1a03e1df757342ad8 from qemu	2018-02-11 02:57:33 -05:00
Richard Henderson	3173269986	target-arm: Eliminate unnecessary zero-extend in disas_bitfield ... For !SF, this initial ext32u can't be optimized away by the current TCG code generator. (It would require backward bit liveness propagation.) Backports commit d3a77b42decd0cbfa62a5526e67d1d6d380c83a9 from qemu	2018-02-11 01:35:58 -05:00
Richard Henderson	c637a97270	target-arm: Recognize UXTB, UXTH, LSR, LSL ... These are all special case aliases of UBFM. Backports commit 9924e85829fe21b5f38a5d267c9aea44c5d478ac from qemu	2018-02-11 01:34:11 -05:00
Richard Henderson	d9e4e70636	target-arm: Recognize SXTB, SXTH, SXTW, ASR ... These are all special case aliases of SBFM. Backports commit ef60151bee9a95e3a5cc98b345a19ed7eb435ddb from qemu	2018-02-11 01:31:54 -05:00
Richard Henderson	5ee72ff9f5	target-arm: Implement fcsel with movcond ... Backports commit 6e061029d74455d83f6fa070ac33de7a356cf60d from qemu	2018-02-11 01:29:14 -05:00
Richard Henderson	53bd2b1d5c	target-arm: Implement ccmp branchless ... This can allow much of a ccmp to be elided when particular flags are subsequently dead. Backports commit 7dd03d773e0dafae9271318fc8d6b2b14de74403 from qemu	2018-02-11 01:25:51 -05:00
Richard Henderson	2c71ddefb1	target-arm: Use setcond and movcond for csel ... Backports commit 259cb68491ab36427e7e5d820fe543d53b006ec6 from qemu	2018-02-10 23:57:11 -05:00
Richard Henderson	70dd48b855	target-arm: Handle always condition codes within arm_test_cc ... Handling this with TCG_COND_ALWAYS will allow these unlikely cases to be handled without special cases in the rest of the translator. The TCG optimizer ought to be able to reduce these ALWAYS conditions completely. Backports commit 9305eac09e61d857c9cc11e20db754dfc25a82db from qemu	2018-02-10 23:48:10 -05:00
Lioncash	94f1227f7a	target-arm: Introduce DisasCompare ... Split arm_gen_test_cc into 3 functions, so that it can be reused for non-branch TCG comparisons. Backports commit 6c2c63d3a02c79e9035ca0370cc549d0f938a4dd from qemu	2018-02-10 23:45:47 -05:00
Richard Henderson	352f93a119	tcg/aarch64: Fix tcg_out_qemu_{ld, st} for guest_base == 0 ... In ffc6372851d8631a9f9fa56ec613b3244dc635b9, we swapped the guest base to the address base register from the address index register. Except that 31 in the base slot is SP not XZR, so we need to be more intelligent about which reg gets placed in which slot. Backports commit 352bcb0a2b816ff9ab9d75d0f2384650d9e9ab19 from qemu	2018-02-10 23:33:24 -05:00
Richard Henderson	7d57c2e4ce	tcg/aarch64: Use softmmu fast path for unaligned accesses ... Backports commit 9ee14902bf107e37fb2c8119fa7bca424396237c from qemu	2018-02-10 23:25:34 -05:00
Lioncash	f8388a6c03	header_gen: Fix mips platform	2018-02-10 23:21:41 -05:00
Richard Henderson	aaf89ed84d	tcg/s390: Use softmmu fast path for unaligned accesses ... Backports commit a5e39810b9088b5d20fac8e0293f281e1c8b608f from qemu	2018-02-10 23:14:14 -05:00
Richard Henderson	a3aaf5a864	tcg: Remove tcg_gen_trunc_i64_i32 ... Replacing it with tcg_gen_extrl_i64_i32. Backports commit ecc7b3aa71f5fdcf9ee87e74ca811d988282641d from qemu	2018-02-10 23:11:02 -05:00
Richard Henderson	58e939b91f	tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32 ... Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Backports commit 609ad70562793937257c89d07bf7c1370b9fc9aa from qemu	2018-02-10 23:00:45 -05:00
Aurelien Jarno	a05256b206	tcg: update README about size changing ops ... Backports commit 870ad1547ac53bc79c21d86cf453b3b20cc660a2 from qemu	2018-02-10 22:49:36 -05:00
Aurelien Jarno	4bd3d5005e	tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops ... They behave the same as ext32s_i64 and ext32u_i64 from the constant folding and zero propagation point of view, except that they can't be replaced by a mov, so we don't compute the affected value. Backports commit 8bcb5c8f34f9215d4f88f388c7ff14c9bd5cecd3 from qemu	2018-02-10 22:47:26 -05:00
Aurelien Jarno	f279c93768	tcg: implement real ext_i32_i64 and extu_i32_i64 ops ... Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a 32-bit value is always converted to a 64-bit value and not propagated through the register allocator or the optimizer. Backports commit 4f2331e5b67af8172419eb1c8db510b497b30a7b from qemu	2018-02-10 22:45:13 -05:00
Aurelien Jarno	80223e7ad5	tcg: rename trunc_shr_i32 into trunc_shr_i64_i32 ... The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends. Always use the long name to make it clear it is a size changing op. Backports commit 0632e555fc4d281d69cb08d98d500d96185b041f from qemu	2018-02-10 22:29:30 -05:00
Aurelien Jarno	5f0920ad0f	tcg/optimize: allow constant to have copies ... Now that copies and constants are tracked separately, we can allow constant to have copies, deferring the choice to use a register or a constant to the register allocation pass. This prevent this kind of regular constant reloading: -OUT: [size=338] +OUT: [size=298] mov -0x4(%r14),%ebp test %ebp,%ebp jne 0x7ffbe9cb0ed6 mov $0x40002219f8,%rbp mov %rbp,(%r14) - mov $0x40002219f8,%rbp mov $0x4000221a20,%rbx mov %rbp,(%rbx) mov $0x4000000000,%rbp mov %rbp,(%r14) - mov $0x4000000000,%rbp mov $0x4000221d38,%rbx mov %rbp,(%rbx) mov $0x40002221a8,%rbp mov %rbp,(%r14) - mov $0x40002221a8,%rbp mov $0x4000221d40,%rbx mov %rbp,(%rbx) mov $0x4000019170,%rbp mov %rbp,(%r14) - mov $0x4000019170,%rbp mov $0x4000221d48,%rbx mov %rbp,(%rbx) mov $0x40000049ee,%rbp mov %rbp,0x80(%r14) mov %r14,%rdi callq 0x7ffbe99924d0 mov $0x4000001680,%rbp mov %rbp,0x30(%r14) mov 0x10(%r14),%rbp mov $0x4000001680,%rbp mov %rbp,0x30(%r14) mov 0x10(%r14),%rbp shl $0x20,%rbp mov (%r14),%rbx mov %ebx,%ebx mov %rbx,(%r14) or %rbx,%rbp mov %rbp,0x10(%r14) mov %rbp,0x90(%r14) mov 0x60(%r14),%rbx mov %rbx,0x38(%r14) mov 0x28(%r14),%rbx mov $0x4000220e60,%r12 mov %rbx,(%r12) mov $0x40002219c8,%rbx mov %rbp,(%rbx) mov 0x20(%r14),%rbp sub $0x8,%rbp mov $0x4000004a16,%rbx mov %rbx,0x0(%rbp) mov %rbp,0x20(%r14) mov $0x19,%ebp mov %ebp,0xa8(%r14) mov $0x4000015110,%rbp mov %rbp,0x80(%r14) xor %eax,%eax jmpq 0x7ffbebcae426 lea -0x5f6d72a(%rip),%rax # 0x7ffbe3d437b3 jmpq 0x7ffbebcae426 Backports commit 299f80130401153af1a6ddb3cc011781bcd47600 from qemu	2018-02-10 22:18:03 -05:00
Aurelien Jarno	59909fe549	tcg/optimize: track const/copy status separately ... Instead of using an enum which could be either a copy or a const, track them separately. This will be used in the next patch. Constants are tracked through a bool. Copies are tracked by initializing temp's next_copy and prev_copy to itself, allowing to simplify the code a bit. Backports commit b41059dd9deec367a4ccd296659f0bc5de2dc705 from qemu	2018-02-10 22:15:43 -05:00
Aurelien Jarno	134a7dfe82	tcg/optimize: add temp_is_const and temp_is_copy functions ... Add two accessor functions temp_is_const and temp_is_copy, to make the code more readable and make code change easier. Backports commit d9c769c60948815ee03b2684b1c1c68ee4375149 from qemu	2018-02-10 22:07:02 -05:00
Aurelien Jarno	b450b79622	tcg/optimize: optimize temps tracking ... The tcg_temp_info structure uses 24 bytes per temp. Now that we emulate vector registers on most guests, it's not uncommon to have more than 100 used temps. This means we have initialize more than 2kB at least twice per TB, often more when there is a few goto_tb. Instead used a TCGTempSet bit array to track which temps are in used in the current basic block. This means there are only around 16 bytes to initialize. This improves the boot time of a MIPS guest on an x86-64 host by around 7% and moves out tcg_optimize from the the top of the profiler list. Backports commit 1208d7dd5fddc1fbd98de800d17429b4e5578848 from qemu	2018-02-10 21:51:46 -05:00
Aurelien Jarno	5f67ab74e7	tcg/optimize: fix constant signedness ... By convention, on a 64-bit host TCG internally stores 32-bit constants as sign-extended. This is not the case in the optimizer when a 32-bit constant is folded. This doesn't seem to have more consequences than suboptimal code generation. For instance the x86 backend assumes sign-extended constants, and in some rare cases uses a 32-bit unsigned immediate 0xffffffff instead of a 8-bit signed immediate 0xff for the constant -1. This is with a ppc guest: before ------ ---- 0x9f29cc movi_i32 tmp1,$0xffffffff movi_i32 tmp2,$0x0 add2_i32 tmp0,CA,CA,tmp2,r6,tmp2 add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2 mov_i32 r10,tmp0 0x7fd8c7dfe90c: xor %ebp,%ebp 0x7fd8c7dfe90e: mov %ebp,%r11d 0x7fd8c7dfe911: mov 0x18(%r14),%r9d 0x7fd8c7dfe915: add %r9d,%r10d 0x7fd8c7dfe918: adc %ebp,%r11d 0x7fd8c7dfe91b: add $0xffffffff,%r10d 0x7fd8c7dfe922: adc %ebp,%r11d 0x7fd8c7dfe925: mov %r11d,0x134(%r14) 0x7fd8c7dfe92c: mov %r10d,0x28(%r14) after ----- ---- 0x9f29cc movi_i32 tmp1,$0xffffffffffffffff movi_i32 tmp2,$0x0 add2_i32 tmp0,CA,CA,tmp2,r6,tmp2 add2_i32 tmp0,CA,tmp0,CA,tmp1,tmp2 mov_i32 r10,tmp0 0x7f37010d490c: xor %ebp,%ebp 0x7f37010d490e: mov %ebp,%r11d 0x7f37010d4911: mov 0x18(%r14),%r9d 0x7f37010d4915: add %r9d,%r10d 0x7f37010d4918: adc %ebp,%r11d 0x7f37010d491b: add $0xffffffffffffffff,%r10d 0x7f37010d491f: adc %ebp,%r11d 0x7f37010d4922: mov %r11d,0x134(%r14) 0x7f37010d4929: mov %r10d,0x28(%r14) Backports commit 29f3ff8d6cbc28f79933aeaa25805408d0984a8f from qemu	2018-02-10 21:40:20 -05:00
Aurelien Jarno	e273acf87a	tcg/optimize: fix tcg_opt_gen_movi ... Due to a copy&paste, the new op value is tested against mov_i32 instead of movi_i32. The test is therefore always false. Fix that. Backports commit 961521261a3d600b0695b2e6d2b0f490076f7e90 from qemu	2018-02-10 21:38:09 -05:00
Aurelien Jarno	42dd2addbe	tcg/optimize: rename tcg_constant_folding ... The tcg_constant_folding folding ends up doing all the optimizations (which is a good thing to avoid looping on all ops multiple time), so make it clear and just rename it tcg_optimize. Backports commit 36e60ef6ac5d8a262d0fbeedfdb2b588514cb1ea from qemu	2018-02-10 21:36:34 -05:00
Aurelien Jarno	7b0055d742	tcg/optimize: fold constant test in tcg_opt_gen_mov ... Most of the calls to tcg_opt_gen_mov are preceeded by a test to check if the source temp is a constant. Fold that into the tcg_opt_gen_mov function. Backports commit 97a79eb70dd35a24fda87d86196afba5e6f21c5d from qemu	2018-02-10 21:34:00 -05:00
Aurelien Jarno	517fac57c3	tcg/optimize: fold temp copies test in tcg_opt_gen_mov ... Each call to tcg_opt_gen_mov is preceeded by a test to check if the source and destination temps are copies. Fold that into the tcg_opt_gen_mov function. Backports commit 5365718a9afeeabde3784d82a542f8ad909b18cf from qemu	2018-02-10 21:27:06 -05:00
Aurelien Jarno	d21f474c39	tcg/optimize: remove opc argument from tcg_opt_gen_mov ... We can get the opcode using the TCGOp pointer. It needs to be dereferenced, but it's anyway done a few lines below to write the new value. Backports commit 8d6a91602ea824ef4435ea38fd475387eecc098c from qemu	2018-02-10 21:23:34 -05:00
Aurelien Jarno	0fd0afad13	tcg/optimize: remove opc argument from tcg_opt_gen_movi ... We can get the opcode using the TCGOp pointer. It needs to be dereferenced, but it's anyway done a few lines below to write the new value. Backports commit ebd27391b00cdafc81e0541a940686137b3b48df from qemu	2018-02-10 21:21:13 -05:00
Richard Henderson	dafc44c0a5	target-mips: Use CPU_LOG_INT for logging related to interrupts ... There are now no unconditional uses of qemu_log in the subdirectory. Backports commit c85570163bdf1ba29cb52a63f22ff1c48f1b9398 from qemu	2018-02-10 21:12:41 -05:00
Richard Henderson	6f66fb4bd5	target-mips: Copy restrictions from ext/ins to dext/dins ... The checks in dins is required to avoid triggering an assertion in tcg_gen_deposit_tl. The check in dext is just for completeness. Fold the other D cases in via fallthru. Backports commit b7f26e523914b982a1c1bfa8295f77ff9787c33c from qemu	2018-02-10 21:09:26 -05:00
Richard Henderson	f5e38ea71e	tcg/aarch64: use 32-bit offset for 32-bit softmmu emulation ... Similar to the same fix for user-mode, except this instance occurs on the softmmu path. Again, the tlb addend must be the base register, while the guest address is the index. Backports commit 80adb8fcad4778376a11d394a9e01516819e2327 from qemu	2018-02-10 20:59:13 -05:00
Paolo Bonzini	cfc9356a8e	tcg/aarch64: use 32-bit offset for 32-bit user-mode emulation ... Thanks to the previous patch, it is now easy for tcg_out_qemu_ld and tcg_out_qemu_st to use a 32-bit zero extended offset. However, the guest base register x28 must be the base and addr_reg must be the index. Backports commit ffc6372851d8631a9f9fa56ec613b3244dc635b9 from qemu	2018-02-10 20:55:51 -05:00
Paolo Bonzini	85bac3c96d	tcg/aarch64: add ext argument to tcg_out_insn_3310 ... The new argument lets you pick uxtw or uxtx mode for the offset register. For now, all callers pass TCG_TYPE_I64 so that uxtx is generated. The bits for uxtx are removed from I3312_TO_I3310. Backports commit 6c0f0c0f124718650a8d682ba275044fc02f6fe2 from qemu	2018-02-10 20:51:37 -05:00
Richard Henderson	95e666c547	tcg/i386: Extend addresses for 32-bit guests ... Removing the ??? comment explaining why it (mostly) worked. Backports commit ee8ba9e4d8458b8bba5455a7ae704620c4f2ef4b from qemu	2018-02-10 20:42:33 -05:00
Richard Henderson	17c1f027c1	tcg: Handle MO_AMASK in tcg_dump_ops ... Backports commit 59c4b7e8dfab0cdc41434fedbf2686222f541e57 from qemu	2018-02-10 20:32:52 -05:00
Richard Henderson	c5a2a50c06	tcg: Mask TCGMemOp appropriately for indexing ... The addition of MO_AMASK means that places that used inverted masks need to be changed to use positive masks, and places that failed to mask the intended bits need updating. Backports commit 2b7ec66f025263a5331f37d5ad78a625496fd7bd from qemu	2018-02-10 20:29:36 -05:00
Richard Henderson	336833c11e	tcg: Add MO_ALIGN, MO_UNALN ... These modifiers control, on a per-memory-op basis, whether unaligned memory accesses are allowed. The default setting reflects the target's definition of ALIGNED_ONLY. Backports commit dfb36305626636e2e07e0c5acd3a002a5419399e from qemu	2018-02-10 20:18:53 -05:00
Richard Henderson	ac713c7034	tcg: Push merged memop+mmu_idx parameter to softmmu routines ... The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu	2018-02-10 20:03:22 -05:00
Richard Henderson	6234d07489	tcg: Merge memop and mmu_idx parameters to qemu_ld/st ... At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Backports commit 59227d5d45bb3c31dc2118011691c35b3c00879c from qemu	2018-02-10 19:01:49 -05:00
Richard Henderson	7532c92358	tcg/optimize: Handle or r,a,a with constant a ... Backports commit 2374c4b8375072da1f401c6daccc68ae76c73e63 from qemu	2018-02-09 14:56:12 -05:00
Richard Henderson	e0d99a1a06	tcg: Complete handling of ALWAYS and NEVER ... Missing from movcond, and brcondi_i32 (but not brcondi_i64). Backports commit 37ed3bf1ee07bb1a26adca0df8718f601f231c0b from qemu	2018-02-09 14:52:21 -05:00
Richard Henderson	6bd102ba86	tcg: Use tcg_malloc to allocate TCGLabel ... Pre-allocating 512 of them per TB is a waste. Backports commit 51e3972c41598adc91fe3f4767057f5198dcc15c from qemu	2018-02-09 14:48:20 -05:00
Richard Henderson	00b0a50f47	tcg: Change generator-side labels to a pointer ... This is less about improved type checking than enabling a subsequent change to the representation of labels. Backports commit bec1631100323fac0900aea71043d5c4e22fc2fa from qemu	2018-02-09 14:40:59 -05:00
Richard Henderson	232632e76c	tcg: Change translator-side labels to a pointer ... This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Backports commit 42a268c241183877192c376d03bd9b6d527407c7 from qemu	2018-02-09 14:17:56 -05:00
Richard Henderson	255a160c66	tcg: Remove unused opcodes ... We no longer need INDEX_op_end to terminate the list, nor do we need 5 forms of nop, since we just remove the TCGOp instead. Backports commit 15fc7daa770764cc795158cbb525569f156f3659 from qemu	2018-02-09 13:20:41 -05:00
Richard Henderson	70f28c8bd5	tcg: Implement insert_op_before ... Rather reserving space in the op stream for optimization, let the optimizer add ops as necessary. Backports commit a4ce099a7a4b4734c372f6bf28f3362e370f23c1 from qemu	2018-02-09 13:11:50 -05:00
Richard Henderson	4fcaabf38c	tcg: Remove opcodes instead of noping them out ... With the linked list scheme we need not leave nops in the stream that we need to process later. Backports commit 0c627cdca20155753a536c51385abb73941a59a0 from qemu	2018-02-09 13:03:58 -05:00
Lioncash	0273e6ae18	tcg: Put opcodes in a linked list ... The previous setup required ops and args to be completely sequential, and was error prone when it came to both iteration and optimization.	2018-02-09 12:54:05 -05:00
Richard Henderson	a41b9acc0c	tcg: Introduce tcg_op_buf_count and tcg_op_buf_full ... The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Backports commit fe700adb3db5b028b504423b946d4ee5200a8f2f from qemu.	2018-02-09 09:31:17 -05:00
Richard Henderson	78378289e3	tcg: Move emit of INDEX_op_end into gen_tb_end ... Backports commit 0a7df5da986bd7ee0789f2d7b8611f2e8eee5046 from qemu	2018-02-09 08:51:01 -05:00
Richard Henderson	4d46959c3b	tcg: Reduce ifdefs in tcg-op.c ... Almost completely eliminates the ifdefs in this file, improving confidence in the lesser used 32-bit builds. Backports commit 3a13c3f34ce2058e0c2decc3b0f9f56be24c9400 from qemu	2018-02-09 08:35:52 -05:00
Richard Henderson	500c546444	tcg: Move some opcode generation functions out of line ... Some of these functions are really quite large. We have a number of things that ought to be circularly dependent, but we duplicated code to break that chain for the inlines. This saved 25% of the code size of one of the translators I examined.	2018-02-09 08:10:00 -05:00
Richard Henderson	cb7b19ad26	tcg: Change ts->mem_reg to ts->mem_base ... Chain the temporaries together via pointers intstead of indices. The mem_reg value is now mem_base->reg. This will be important later. This does require that the frame pointer have a global temporary allocated for it. This is simple bar the existing reserved_regs check. Backports commit b3a62939561e07bc34493444fa926b6137cba4e8 from qemu	2018-02-08 13:04:48 -05:00
Richard Henderson	6b4b493dae	tcg: Change tcg_global_mem_new_* to take a TCGv_ptr ... Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Backports commit e1ccc05444676b92c63708096e36582be27fbee1 from qemu	2018-02-08 12:33:33 -05:00
Richard Henderson	afb67fc002	target/arm: Fix aa64 ldp register writeback ... Backports commit 3e4d91b94ce400326fae0850578d9e9f30a71adb from qemu	2018-02-08 08:29:51 -05:00
Eric Blake	37cdcbf771	maint: Fix macros with broken 'do/while(0); ' usage	2018-02-07 20:27:37 -05:00
Lioncash	0f453b0595	target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers ... Backports commit 9a2b5256ea1f68c89d5da4b54f180f576c2c82d6 from qemu	2018-02-07 10:09:26 -05:00
Lioncash	dd577f5ea5	target/arm: Change the type of vfp.regs ... Backports commit 3f68b8a5a6862f856524bb347bf348ae364dd43c from qemu	2018-02-07 09:57:43 -05:00
Lioncash	ef07c136b6	target/arm: Add fp16 support to vfp_expand_imm ... Backports commit 8081796a75414f9ed5ec3d97158e543ed45908ec from qemu.	2018-02-07 09:47:04 -05:00
Lioncash	b55f35ba92	target/arm: Split out vfp_expand_imm ... Backports commit e90a99fe6bde9b85bff8c052ade51520f20d9bce from qemu.	2018-02-07 09:44:52 -05:00
Lioncash	4c165ed788	translate-a64: Silence unused variable warning	2018-02-06 08:38:01 -05:00
Merry	29d38d7c22	Merge pull request #10 from lioncash/el-busto-ldst-exclusive ... translate-a64: Backport fix for incorrect load/store exclusive unallocated checks	2018-02-05 20:59:25 +00:00
Merry	b7bb608197	Merge pull request #9 from lioncash/ia64 ... tcg: Drop ia64 host support	2018-02-05 20:59:18 +00:00
Merry	82c4212ce3	Merge pull request #8 from lioncash/optimize ... Backport REV16 optimizations from qemu	2018-02-05 20:58:58 +00:00
Lioncash	1e451b386a	translate-a64: Backport fix for incorrect load/store exclusive unallocated checks ... Backports commit e14f0eb12f920fd96b9f79d15cedd437648e8667 from qemu	2018-02-04 23:17:45 -05:00
Lioncash	7f665d8c1e	tcg: Drop ia64 host support ... Backports commit a46c1244a0d65d5f37fc12e4d42f2479eac87b52 from qemu	2018-02-04 18:33:02 -05:00
Lioncash	5a37b8c28e	Backport optimizations to AArch32's REV16 handling ... Backports commit 68cedf733ae32363ccf54f0b52c8a424d5ec98ed from qemu	2018-02-04 14:53:28 -05:00
Lioncash	4a8a92bad2	Backport optimizations to AArch64's REV16 handling ... Backports commits abb1066df313602ef0ca631126bd342d399d5359 and e4256c3cbf7eefebc0bc6e1f472c47c6dd20b996 from qemu.	2018-02-04 14:45:39 -05:00
Lioncash	122d54e23e	Backport the SVE feature flag ... Backports commit 0d0a16c647650d476219a5e1313dec434f9fbebb in qemu to unicorn	2018-02-02 08:52:15 -05:00
Lioncash	4fb2fbfacf	Backport the JAZELLE feature flag ... Backports commit c99a55d38dd5b5131f3fcbbaf41828a09ee62544 in qemu to unicorn	2018-02-02 08:50:18 -05:00
Lioncash	84319130cd	Backport the M_SECURITY feature flag ... Backports relevant parts from commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f in qemu to unicorn	2018-02-02 08:44:46 -05:00
Lioncash	20038fb801	Backport the PMU feature flag ... Backports the applicable code from commit 929e754d5a621cd53f30e69b766ccf381b58d124 to unicorn	2018-02-02 08:28:27 -05:00
Lioncash	35100ce4e0	Backport the VBAR feature flag ... Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn	2018-02-02 08:24:12 -05:00
Lioncash	291b5753eb	Backport the THUMB_DSP feature flag ... Backports commit 62b44f059a84d1ac580a653fc4110dfabaef6b83 in qemu to unicorn.	2018-02-02 07:59:26 -05:00
Lioncash	438e2836e0	helper_a64: Fix CRC32's implementation	2018-01-29 09:24:36 -05:00
Lioncash	d41b200fd4	A64: Add EOR3 and BCAX support ... Backported to unicorn from: https://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg05003.html	2018-01-25 21:18:36 -05:00
MerryMage	4128f3b259	aarch64: Add FPCR and FPSR registers	2018-01-16 17:37:47 +00:00
MerryMage	f90c819a33	aarch64: Add pstate pseudoregister	2018-01-16 17:37:17 +00:00
bunnei	73f4573535	aarch64: Add exception syndrome pseudo register.	2018-01-03 19:41:12 -05:00
Nguyen Anh Quynh	d5f83a9c2e	arm: cleanup for ARM_CPU	2017-12-21 09:43:33 +08:00
Nguyen Anh Quynh	e67be36c88	arm: remove unused variable in arm_cpu_get_phys_page_debug()	2017-12-20 22:12:35 +08:00
Nguyen Anh Quynh	3e0d0cfab7	i386: fix signed int overflow in #923 & #924	2017-12-16 10:28:45 +08:00
Andrew Dutcher	d7735487f7	Use the qemu helpers to get/set the x86 eflags (#878)	2017-09-15 22:18:38 +07:00
Andrew Dutcher	363cbacee4	Only set eip to the instruction pointer after an interrupt if the interrupt was user-generated (#875)	2017-08-29 17:14:36 +07:00
darkf	42d0632108	Fix typo in ARM tcg-target.c (#859)	2017-07-22 23:36:38 +08:00
vardyh	ad767abda8	x86::trans: handle illegal case for opc c6/c7 ... Reference Intel software developer manual vol2 Appendix A Table A-6 for detailed decoding information. Signed-off-by: vardyh <vardyh.dev@gmail.com>	2017-05-25 15:22:45 +08:00
misson20000	014ccfb94a	Aarch64 add thread registers (#834) ... * add thread registers to AArch64 * update bindings to add AArch64 thread registers * fix indentation for register read/write switch-case in unicorn_aarch64.c	2017-05-14 14:42:49 +07:00
bulaza	4b9efdc986	Adding INSN hook checks for x86 (#833) ... * adding INSN hook checking for x86 * tabs to spaces * need to return bool not uc_err * fixed conditional after switching to bool	2017-05-14 00:16:17 +07:00
Ryan Hileman	ae6ea3b91d	fix arm64 hang (fix #827) (#828)	2017-05-09 20:19:32 +08:00
Samuel Groß	5385baba39	Implemented read and write access to the YMM registers (#819)	2017-05-05 09:02:58 +08:00
zhangwm	4a62409949	arm64eb: arm64 big endian also using little endian instructions. (#816) ... * arm64eb: arm64 big endian also using little endian instructions. * arm64: using another example that depends on endians. example: 1. store a word: 0x12345678 2. load a byte: * little endian : 0x78 * big endian : 0x12	2017-05-04 20:00:48 +08:00
Ryan Hileman	1b00d3f89a	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
Ryan Hileman	187b470245	add arm64 CPACR_EL1 register support (#814)	2017-05-02 14:51:19 +08:00
zhangwm	2e973a13f0	arm64eb: add support for ARM64 big endian.	2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh	513075e061	arm: fix an warning reported by GCC	2017-04-21 21:12:57 +08:00
Nguyen Anh Quynh	e917c9de10	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
0xSeb	605400e10e	determine correct Thumb/Thumb2 instruction size (16/32-bit) for code … (#796) ... * determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook * determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook * determine correct Thumb/Thumb2 instruction size (16/32-bit) for code hook	2017-04-15 00:39:56 +08:00
Nguyen Anh Quynh	f915f14e74	Merge branch 'master' of https://github.com/unicorn-engine/unicorn	2017-04-12 22:06:40 +08:00
Nguyen Anh Quynh	cb44f77ac3	mips: fix uc_reg_read() for MIPS64	2017-04-12 22:06:26 +08:00
Nguyen Anh Quynh	3315f288d3	fix an warning in glib_compat.c	2017-04-12 14:01:58 +08:00
bunnei	4eca426fb6	unicorn_aarch64: Expose UC_ARM64_REG_NZCV register. (#791)	2017-03-31 10:21:45 +08:00
Nguyen Anh Quynh	094ca80092	fix conflicts	2017-03-30 12:23:24 +08:00
zhangwm	ccdb0ff523	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00
Nguyen Anh Quynh	a267af7d95	add arm_release to qemu/header_gen.py, and regenerate qemu/armeb.h	2017-03-14 23:41:31 +08:00
zhangwm	d8fe34a2e8	armeb: Add support for ARM big endian.	2017-03-13 22:32:44 +08:00
Nguyen Anh Quynh	c01dcf0a14	fix merge conflicts	2017-03-10 21:04:33 +08:00
feliam	0150ca24b1	Add support for ARM application flags - APSR register (#776)	2017-03-09 22:28:03 +08:00
Matt Thomas	2749b8412e	fix register widths for MIPS64 reg_read/write (#775) ... * fix register widths for MIPS64 reg_read/write * fix preprocessor typedef error for qemu/target-mips	2017-03-08 08:40:30 +08:00
stevielavern	b3a5eae81c	uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) ... * uc_reg_read & uc_reg_write now support ARM64 Neon registers * Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.	2017-03-07 21:29:34 +08:00
Nguyen Anh Quynh	c3808179e1	another attempt to fix #766	2017-02-26 15:22:24 +08:00
Nguyen Anh Quynh	e65fef70dc	add missing TCG context arg to few functions in tcg.c. see #766	2017-02-26 09:47:40 +08:00
Nguyen Anh Quynh	d52f85d16e	add back missing ELF symbols reported in #766	2017-02-26 09:39:11 +08:00
Ahmed Samy	02e6c14e12	x86: add MSR API via reg API (#755) ... Writing / reading to model specific registers should be as easy as calling a function, it's a bit stupid to write shell code and run them just to write/read to a MSR, and even worse, you need more than just a shellcode to read... So, add a special register ID called UC_X86_REG_MSR, which should be passed to uc_reg_write()/uc_reg_read() as the register ID, and then a data structure which is uc_x86_msr (12 bytes), as the value (always), where: Byte Value Size 0 MSR ID 4 4 MSR val 8	2017-02-24 21:37:19 +08:00
Nguyen Anh Quynh	f3ada41b99	fix the last fix that crashes samples	2017-02-24 20:34:52 +08:00
Nguyen Anh Quynh	7c29558a95	msvc: fix a warning in qemu/exec.c when merging master to msvc	2017-02-24 19:29:55 +08:00
Nguyen Anh Quynh	6ea39f7d5a	merge msvc with master	2017-02-24 10:39:36 +08:00
Nguyen Anh Quynh	e7ecbf7889	m68k: fix a compilation warning	2017-02-23 20:34:17 +08:00
Nguyen Anh Quynh	714cf2c609	arm: fix a warning	2017-02-23 20:32:09 +08:00
Nguyen Anh Quynh	736d9857d2	recover some ELF symbols for building on Arm, PPC, Sparc & S390. issue #752	2017-02-20 15:16:50 +08:00
Chris Eagle	a03e908611	Fix initial state of segment registers (#751) ... * Remove glib from samples makefile * changes to 16 bit segment registers needs to update segment base as well as segment selector * change how x86 segment registers are set in 16-bit mode * more appropriate solution to initial state of x86 segment registers in 16-bit mode * remove commented lines	2017-02-09 23:49:54 +08:00
Chris Eagle	f05984961b	Fix 16-bit address computations (#747) ... * Remove glib from samples makefile * changes to 16 bit segment registers needs to update segment base as well as segment selector * change how x86 segment registers are set in 16-bit mode	2017-02-08 09:37:41 +08:00
vardyh	7f9251511e	MSVC port (vardyh) (#746) ... * unicorn: use waitable timer to implement usleep() on Windows Signed-off-by: vardyh <vardyh.dev@gmail.com> * atomic: implement barrier() for msvc Signed-off-by: vardyh <vardyh.dev@gmail.com>	2017-02-07 21:31:35 +08:00
Parker Thompson	053ecd7bf4	Added ARM coproc registers (#684) ... * Added ARM coproc registers * Added regression test for vfp	2017-01-25 11:56:19 +08:00
Nguyen Anh Quynh	ef52d9a9d1	cleanup qemu/include/qemu/module.h	2017-01-25 00:20:08 +08:00
xorstream	e08d1bf7c6	Arm issue fix. (#738) ... * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file * Arm issue fix.	2017-01-24 17:45:01 +08:00
xorstream	8e45102b43	Arm support ported. (#736) ... * Fix for MIPS issue. * Sparc support added. * M68K support added. * Arm support ported. * Fix issue with VS2015 shlobj.h file	2017-01-23 23:30:57 +08:00
xorstream	2695a0ffe8	M68K support added. (#735) ... * Fix for MIPS issue. * Sparc support added. * M68K support added.	2017-01-23 14:40:02 +08:00
xorstream	a40921ce32	Sparc support added. (#734) ... * Fix for MIPS issue. * Sparc support added.	2017-01-23 13:29:41 +08:00
xorstream	69ae8f7987	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
Nguyen Anh Quynh	2ecbe89cc1	cleanup Sparc unused code	2017-01-23 12:34:00 +08:00
Nguyen Anh Quynh	e4c7c3dbe4	cleanup Sparc unused code	2017-01-23 12:33:39 +08:00
Nguyen Anh Quynh	0680b85920	cleanup Monitor related code	2017-01-23 10:07:01 +08:00
Nguyen Anh Quynh	81b8a685be	cleanup	2017-01-23 10:06:49 +08:00
Nguyen Anh Quynh	55d472c62c	cleanup Monitor related code	2017-01-23 00:53:31 +08:00
Nguyen Anh Quynh	b3faed1df9	cleanup	2017-01-23 00:30:13 +08:00
Nguyen Anh Quynh	a95fdbc5aa	cleanup qemu/include/exec/memory.h	2017-01-22 23:21:47 +08:00
Nguyen Anh Quynh	5de0785a1b	cleanup qemu/memory.c	2017-01-22 23:07:17 +08:00
xorstream	e46f86c80b	Merging with current msvc.	2017-01-23 01:07:06 +11:00
xorstream	72a497bc14	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
Nguyen Anh Quynh	206819bd98	cleanup after msvc port	2017-01-22 21:27:17 +08:00
xorstream	1a9ebbecde	isnan() fix for msvc2013 onwards (#729) ... * Changed some MSVC compatibility defines based on MSVC version. * Added prebuild_script.bat to remove leftover configure generated files before building. Also added project files and MSVC copies of configure generated files for all supported CPUs. * Moved ./bindings/msvc_native into ./msvc * Remove old project dir. * isnan() fix for msvc2013 onwards	2017-01-22 16:14:05 +08:00
xorstream	03dcce40b2	isnan() fix for msvc2013 onwards	2017-01-22 18:13:28 +11:00
Nguyen Anh Quynh	49c904a629	cleanup qemu/configure	2017-01-22 05:57:29 +08:00
Nguyen Anh Quynh	d04cc8671d	cleanup qemu/configure	2017-01-22 05:56:37 +08:00
Nguyen Anh Quynh	2a1b9d8e1b	cleanup qemu/Makefile.objs	2017-01-21 21:50:12 +08:00
xorstream	9fac29d154	Changed some MSVC compatibility defines based on MSVC version. (#724)	2017-01-21 20:21:27 +08:00
Nguyen Anh Quynh	0d51163abc	cleanup qemu/util/qemu-timer-common.c	2017-01-21 14:55:35 +08:00
Nguyen Anh Quynh	45717c61ba	cleanup qemu/util/qemu-timer-common.c	2017-01-21 14:53:33 +08:00
Nguyen Anh Quynh	647c97ddc3	ffs() is redundant	2017-01-21 11:11:22 +08:00
Nguyen Anh Quynh	5d0797afe7	ffs() is redundant	2017-01-21 11:10:48 +08:00
Nguyen Anh Quynh	c8550b86f0	fix conflicts	2017-01-21 11:06:05 +08:00
Nguyen Anh Quynh	fa12120d75	termios.h & strings.h are not needed	2017-01-21 11:02:17 +08:00
xorstream	770c5616e2	Automated leading tab to spaces conversion.	2017-01-21 12:28:22 +11:00
xorstream	df41c49e2d	Fixed warning about {} initialisers.	2017-01-21 11:41:11 +11:00
xorstream	429bfca48e	Fixes for MSVC native support to still work with GCC/GNU.	2017-01-21 01:07:10 +11:00
xorstream	8840d5b42b	Save copies of generated qapi files.	2017-01-21 00:30:50 +11:00
xorstream	fac6a66860	platform.h move #3	2017-01-21 00:13:21 +11:00
xorstream	1aaf57ca54	Some more little edits to prepare for pull request.	2017-01-20 22:46:32 +11:00
xorstream	b0ae2138fb	Merge remote-tracking branch 'unicorn-engine/master' into msvc_native	2017-01-20 22:37:51 +11:00
Nguyen Anh Quynh	ac68745a9c	we dont need to handle VGA & Migration memories	2017-01-20 17:03:39 +08:00
Nguyen Anh Quynh	fff532fc20	timer is redundant	2017-01-20 16:46:58 +08:00
Nguyen Anh Quynh	6daa8581cd	win32_start_routine() looks broken. TODO	2017-01-20 16:12:49 +08:00
xorstream	ee294eebb0	Fixed double free in win32 threads and changed free() to g_free(). (#722)	2017-01-20 16:03:35 +08:00
Nguyen Anh Quynh	c6de7930c9	remove mutex code	2017-01-20 15:44:03 +08:00
xorstream	92392e0f57	Merge with current master.	2017-01-20 18:22:28 +11:00
Nguyen Anh Quynh	42771848d6	no more spinlock	2017-01-20 14:57:33 +08:00
Nguyen Anh Quynh	a7fca49f7a	delete qemu/include/qemu/notify.h	2017-01-20 14:47:41 +08:00
xorstream	002151874a	Unicorn interface working with test app in 32bit and 64bit builds.	2017-01-20 17:27:22 +11:00
Nguyen Anh Quynh	b887c3bb25	delete qemu/include/exec/poison.h	2017-01-20 13:58:50 +08:00
Nguyen Anh Quynh	94e55f45c1	del qemu/target-m68k/m68k-semi.c	2017-01-20 11:52:31 +08:00
Nguyen Anh Quynh	b678512fc1	remove kvm stuffs	2017-01-20 01:03:59 +08:00
Nguyen Anh Quynh	7e2234237c	del qemu/scripts/dump-guest-memory.py	2017-01-19 20:56:07 +08:00
xorstream	1aeaf5c40d	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh	b9b82591a1	cleanup	2017-01-19 18:07:30 +08:00
Nguyen Anh Quynh	8a5b12c6f9	more cleanup in qemu/include/hw/	2017-01-19 15:20:06 +08:00
Nguyen Anh Quynh	287e047fdb	delete sparc32_dma.h & arm-semi.c	2017-01-19 15:10:41 +08:00
Nguyen Anh Quynh	f4f756e6dd	cleanup qemu/include/qemu/module.h	2017-01-19 15:00:25 +08:00
Nguyen Anh Quynh	7789a06d2d	cleanup qemu/default-configs/	2017-01-19 14:52:30 +08:00
Nguyen Anh Quynh	86e5d29b74	more cleanup qemu/configure	2017-01-19 14:15:00 +08:00
Nguyen Anh Quynh	f2691b0107	more cleanup qemu/configure	2017-01-19 14:11:54 +08:00
Nguyen Anh Quynh	37410d02f1	cleanup qemu/configure	2017-01-19 14:02:50 +08:00
Nguyen Anh Quynh	9735c6e28e	cleanup qemu/include/elf.h	2017-01-19 13:46:17 +08:00
Nguyen Anh Quynh	a6fa35430a	del qemu/include/qapi/opts-visitor.h	2017-01-19 13:23:48 +08:00
Nguyen Anh Quynh	d836ec62fc	del qemu/include/hw/irq.h	2017-01-19 13:14:15 +08:00
Nguyen Anh Quynh	0640b35943	mips: remove qemu/hw/mips/mips_int.c	2017-01-19 13:07:28 +08:00
Nguyen Anh Quynh	a154b251e3	cleanup	2017-01-19 12:18:46 +08:00
Nguyen Anh Quynh	326a9a5fba	cleanup qemu docs	2017-01-18 15:23:40 +08:00
Elton G	47150b6df3	reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716) ... * reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton * Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30) Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write * Fixed WRITE_DWORD macro reg_write would zero out the high order bits when writing to 32 bit registers e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero	2017-01-15 20:13:35 +08:00
Nguyen Anh Quynh	7512ff57de	more cleanup	2017-01-10 16:29:47 +08:00
Nguyen Anh Quynh	c1f39c3db2	cleanup qemu/util code	2017-01-10 12:57:12 +08:00
Nguyen Anh Quynh	af165d254c	clean all qobject json code	2017-01-09 16:09:53 +08:00
Nguyen Anh Quynh	16894fdb6c	cleanup some qemu/util code	2017-01-09 15:48:21 +08:00
Nguyen Anh Quynh	52cb0ba78e	cleanup more synchronization code	2017-01-09 14:05:39 +08:00
Nguyen Anh Quynh	d7ead1135d	cleanup	2017-01-09 13:28:28 +08:00
Nguyen Anh Quynh	ffa97dc2a1	cleanup qemu/configure	2017-01-08 01:35:19 +08:00
Agustin Gianni	a63a34bfbc	Allow the client to write to CPSR	2017-01-05 00:00:15 +01:00
Nguyen Anh Quynh	2e8fa1dbf6	glib_compat: add guint64 type	2017-01-02 01:24:54 +08:00
Nguyen Anh Quynh	3fa50fc06a	macro GPOINTER_TO_UINT	2017-01-02 01:00:11 +08:00
Nguyen Anh Quynh	d5f513cbfe	Merge branch 'master' into noglib2	2016-12-27 22:49:59 +08:00
cojocar	428cb83060	Support for MCLASS ARM cpu (Cortex-M3) (#700) ... Support for Cortex-M ARM CPU already exists in Qemu. This patch just exposes a "cortex-m3" CPU. "uc_open(UC_ARCH_ARM, UC_MODE_THUMB | UC_MODE_MCLASS, &uc);" Instantiates a CPU with this feature on. Signed-off-by: Lucian Cojocar <lucian@cojocar.com>	2016-12-27 22:49:06 +08:00
Nguyen Anh Quynh	3fb078c555	glib_compat: add COPYING_GLIB	2016-12-27 10:15:08 +08:00
Nguyen Anh Quynh	9b809601ec	glib_compat: code style	2016-12-27 00:13:27 +08:00
Nguyen Anh Quynh	520f335a2a	glib_compat: lift string functions from glib. remove unused API g_win32_error_message()	2016-12-26 22:36:47 +08:00
Nguyen Anh Quynh	c5b8fbfbc6	glib_compat: FALSE = 0	2016-12-26 22:02:34 +08:00
Nguyen Anh Quynh	e4382c0467	glib_compat: lift hash functions from glib	2016-12-26 20:12:01 +08:00
Nguyen Anh Quynh	fba6046fd0	glib_compat: lift g_list_sort() & g_slist_sort() from glib code	2016-12-26 18:32:02 +08:00
Nguyen Anh Quynh	cb40e6a3f5	glib_compat: some minor fixes	2016-12-26 18:13:46 +08:00
Nguyen Anh Quynh	6b57da1fc2	glib_compat: make the API compatible with glib	2016-12-26 01:35:42 +08:00
Nguyen Anh Quynh	5777c4f3fd	Merge branch 'noglib' of https://github.com/unicorn-engine/unicorn into noglib	2016-12-22 12:13:53 +08:00
Nguyen Anh Quynh	9371ae7dd7	cleanup glib_compat	2016-12-22 12:13:31 +08:00
Chris Eagle	fccbcfd4c2	revert to use of g_free to make future qemu integrations easier (#695) ... * revert to use of g_free to make future qemu integrations easier * bracing	2016-12-21 22:28:36 +08:00
Nguyen Anh Quynh	6a2eb14ff3	Merge pull request #693 from cseagle/noglib ... add g_free to make future integration easier	2016-12-21 08:50:52 +08:00
Chris Eagle	bfaf8f3441	add g_free to make future integration easier	2016-12-20 12:27:15 -08:00
Nguyen Anh Quynh	14d04493f1	Merge branch 'noglib' of https://github.com/cseagle/unicorn into noglib	2016-12-20 11:33:46 +08:00
Nguyen Anh Quynh	6d747d1a13	remove pkg-config dependency	2016-12-20 11:30:26 +08:00
Chris Eagle	f8f9e993a8	merge upstream/noglib and update some glib related types	2016-12-19 12:32:06 -08:00
Chris Eagle	e07e57a862	battling git	2016-12-19 12:10:02 -08:00
Chris Eagle	e53c295f61	please the gods of brace	2016-12-19 12:02:01 -08:00
Chris Eagle	71bda8e012	stick to gint/guint rather than int32_t/uint32_t	2016-12-19 09:43:35 -08:00
Nguyen Anh Quynh	bd1632e60c	fix an warning 'control may reach end of non-void function'	2016-12-20 00:21:02 +08:00
Nguyen Anh Quynh	16bbe4fb88	do not redefine GHashTable	2016-12-20 00:19:13 +08:00
Nguyen Anh Quynh	04e2e7e845	glib_compat.c: code style	2016-12-19 22:18:33 +08:00
Nguyen Anh Quynh	b19f1607c6	Revert "remove qemu/util/qemu-timer-common.c" ... This reverts commit 934fa2c90f.	2016-12-19 20:31:38 +08:00
Nguyen Anh Quynh	b680ee11f8	Revert "remove qemu/util/qemu-timer-common.c" ... This reverts commit 934fa2c90f.	2016-12-19 20:30:46 +08:00
Nguyen Anh Quynh	5f81c00559	Merge branch 'noglib' of https://github.com/cseagle/unicorn into cseagle-noglib	2016-12-19 17:32:27 +08:00
Nguyen Anh Quynh	934fa2c90f	remove qemu/util/qemu-timer-common.c	2016-12-19 17:29:25 +08:00
Chris Eagle	5690b7b68f	annotate the hash functions	2016-12-18 19:45:09 -08:00
Chris Eagle	c7bd120650	imlpement key destroy and value destroy callbacks in hash tables	2016-12-18 15:28:11 -08:00
Chris Eagle	e46545f722	remove glib dependency by provide compatible replacements	2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh	e1b65a6edb	cleanup unused code	2016-11-19 23:48:23 +08:00
Nguyen Anh Quynh	1f65b76fbd	fix some compilation warnings regarding typcase of (CPUState *)	2016-10-26 17:05:26 +08:00
Nguyen Anh Quynh	c59e06d798	mips: fix some compilation warnings	2016-10-22 13:36:37 +08:00
Nguyen Anh Quynh	4083b87032	add new hook type UC_HOOK_MEM_READ_AFTER, adapted from PR #399 by @farmdve. updated all bindings, except Ruby & Haskell	2016-10-22 11:19:55 +08:00
Nguyen Anh Quynh	2a608c778e	sparc: fix an compilation warning	2016-10-21 22:32:02 +08:00
Fish	ad7ae63e92	Remove unmapped/freed memory regions from the object property list. ... This commit fixes the following issues: - Any unmapped/free'd memory regions (MemoryRegion instances) are not removed from the object property linked list of its owner (which is always qdev_get_machine(uc)). This issue makes adding new memory mapping by calling mem_map() or mem_map_ptr() slower as more and more memory pages are mapped and unmapped - yes, even if those memory pages are unmapped, they still impact the speed of future memory page mappings due to this issue. - FlatView is not reconstructed after a memory region is freed during unmapping, which leads to a use-after-free the next time a new memory region is mapped in address_space_update_topology().	2016-10-20 03:48:58 -07:00
Nguyen Anh Quynh	b7cdbe7a88	Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore	2016-10-07 09:57:07 +08:00
danghvu	fb9cd97504	memleak: Fix m68k memleak	2016-10-03 14:47:03 -05:00
danghvu	84d99412bc	memleak: Fix Sparc memory leak	2016-10-03 14:23:27 -05:00
Nguyen Anh Quynh	7d15a60b25	arm64: disable deadcode introduced by PR #643	2016-09-29 12:34:44 +08:00
Nguyen Anh Quynh	507d557aa5	arm: disable deadcode introduced by PR #643	2016-09-29 12:33:16 +08:00
Ryan Hileman	cb615fdba7	remove uc->cpus	2016-09-23 07:38:21 -07:00
Nguyen Anh Quynh	69d976375e	Merge branch 'fix/self_modifying' of https://github.com/rhelmot/unicorn into rhelmot-fix/self_modifying	2016-08-30 21:20:22 +08:00
Nguyen Anh Quynh	8b030ae51a	fix for issue #523	2016-08-27 21:49:11 +08:00
Nguyen Anh Quynh	89c9ea5f8f	Merge branch 'fix/eflags' of https://github.com/rhelmot/unicorn into rhelmot-fix/eflags	2016-08-24 16:13:31 +08:00
Nguyen Anh Quynh	40ea64af19	Merge branch 'feat/xmm_regs' of https://github.com/rhelmot/unicorn into rhelmot-feat/xmm_regs	2016-08-23 06:52:45 +08:00
Nguyen Anh Quynh	8e1102f741	Merge pull request #620 from rhelmot/feat/invalid_floatx80_check ... Port patch from upstream to check for invalid long double encodings	2016-08-21 09:48:26 +08:00
Andrew Dutcher	1f5d14df4d	Port patch from upstream to check for invalid long double encodings	2016-08-20 11:31:46 -07:00
Andrew Dutcher	0ef2b5fd71	New feature: registers can be bulk saved/restored in an opaque blob	2016-08-20 04:14:07 -07:00
Ryan Hileman	f99030179c	fix free() -> g_free()	2016-08-11 07:49:19 -07:00
Andrew Dutcher	3a1f231e8f	eflags patch	2016-08-09 19:38:44 -07:00
Andrew Dutcher	97b10da133	Undo the disaster that was the patch to unicorn github issue #266 and fix it correctly. makes normal self-modifying code work.	2016-08-09 19:35:20 -07:00
Andrew Dutcher	4a8f52ae7f	support xmm registers	2016-08-09 19:34:34 -07:00
Nguyen Anh Quynh	fd39ec465b	arm: sync env.uc->thumb with env.thumb in arm_reg_write()	2016-07-30 13:21:44 +08:00
Nguyen Anh Quynh	a59f54ca72	Merge branch 'master' of https://github.com/esanfelix/unicorn into esanfelix-master	2016-07-30 13:18:37 +08:00
Nguyen Anh Quynh	c61aff1dbe	mips: remove an unused variable	2016-07-15 15:12:15 +08:00
danghvu	bb8f894872	windows: Remove unnecessary mman inclusion (issue #587)	2016-07-11 13:35:49 -05:00
Hoang-Vu Dang	b9a10152f1	memleak: code_gen_buffer using g_free for non-linux	2016-07-11 10:13:13 -05:00
danghvu	27e0699ef5	mips: Fix memleak	2016-07-09 20:16:00 -05:00
danghvu	117a318188	memleak: missing from refactoring	2016-07-08 12:49:43 -05:00
danghvu	6b9f17f2f7	memleak: refactor unicorn_common.h, move stuff to uc_close	2016-07-08 11:16:23 -05:00
danghvu	ada1c13662	Fix memleak: do not re-initialize halt_cond	2016-07-06 01:49:10 -05:00
Hoang-Vu Dang	de5786f98d	Fix memleak: code_gen_buffer	2016-07-05 23:48:02 -05:00
Hoang-Vu Dang	9a2a5b15d8	Rename unhandled CPU exception	2016-07-05 11:10:39 -05:00
Hoang-Vu Dang	9cdca5a32b	Unhandled interrupt will halt execution	2016-07-04 17:07:57 -05:00
Eloi Sanfelix	3a1c13fda9	Set thumb mode based on PC value in ARM. Mask off last bit of PC.	2016-06-17 13:46:34 +02:00
Nguyen Anh Quynh	40ac55cf74	Merge branch 'drop-zlib' of https://github.com/radare/unicorn into radare-drop-zlib	2016-06-15 16:41:13 +07:00
pancake	fe96e8325b	Remove unused zlib dependency	2016-06-15 09:24:16 +02:00
mkravchik	4b45869437	Reading and writing NEON registers	2016-05-04 11:23:32 +03:00
Nguyen Anh Quynh	f4723916df	remove qemu_cond_destroy from qemu/header_gen.py	2016-04-23 10:23:09 +08:00
Nguyen Anh Quynh	72ba554738	qemu_thread_join() takes only 1 arg	2016-04-23 10:17:04 +08:00
Nguyen Anh Quynh	3a742fb6f6	fix conflicts when merging no-thread to master	2016-04-23 10:06:57 +08:00
Nguyen Anh Quynh	8932463f9d	arm: qutie emulation on EXCP_YIELD exception. this fixes testcase 004-segmentation_fault_1 in #520	2016-04-20 12:04:15 +08:00
Nguyen Anh Quynh	cc6cbc5cf7	Merge branch 'memleak' into m2	2016-04-18 12:48:13 +08:00
Nguyen Anh Quynh	ba31be79f4	update qemu/powerpc.h	2016-04-17 23:37:25 +08:00
Nguyen Anh Quynh	47a7bb3c9f	Merge branch 'smaller_nothreads' of https://github.com/cseagle/unicorn into cseagle-smaller_nothreads	2016-04-17 23:37:06 +08:00
Nguyen Anh Quynh	721f17eb74	Merge branch 'batch_reg' of https://github.com/lunixbochs/unicorn into lunixbochs-batch_reg	2016-04-06 09:39:22 +08:00
Nguyen Anh Quynh	70da2485fc	x86: comment out restore_eflags() because it breaks some executions. see #505	2016-04-06 09:36:06 +08:00
Ryan Hileman	acd88856e1	add batched reg access	2016-04-04 20:51:38 -07:00
Ryan Hileman	66619fc6cd	remove call to restore_eflags (#496)	2016-04-03 23:08:17 -07:00
Chris Eagle	3add48feb5	Merge branch 'master' into smaller_nothreads	2016-03-25 19:47:52 -07:00
Chris Eagle	6991d69dad	merge from upstream	2016-03-25 19:46:44 -07:00
Ryan Hileman	977863401e	static -> dynamic code buffer, and shrink 32M->8M	2016-03-25 18:28:03 -07:00
Chris Eagle	9467254fc0	strip out per cpu thread code	2016-03-25 17:24:28 -07:00
Ryan Hileman	f0af8f8282	execute cpus in same thread as uc_emu_start() ... note: I'm sure this makes some dead code	2016-03-23 22:50:56 -07:00
Chris Eagle	4c4203cec8	fix x86 segment setup by updating cached segment registers on reg_write	2016-03-22 23:54:30 -07:00
Nguyen Anh Quynh	859111f8f5	x86: return immediately after handling FPSW/FPCW/FPTAG registers	2016-03-20 18:15:41 +08:00
Nguyen Anh Quynh	fb1ebac000	Merge branch 'master' into m1	2016-03-09 15:13:42 +08:00
Hiroyuki UEKAWA	c5888e5670	move macros in qemu/target-*/unicorn*.c to uc_priv.h	2016-03-02 12:43:02 +09:00
Hiroyuki UEKAWA	1cd3c3093b	fix WRITE_BYTE_H	2016-03-02 10:51:50 +09:00
Jonas Zaddach	5fa6705d7a	Fixed restoring of eflags after helper call	2016-02-29 22:57:41 +01:00
Nguyen Anh Quynh	b69feb8d0b	Merge branch 'master' into memleak2	2016-02-15 15:52:10 +08:00
Nguyen Anh Quynh	8962adc9c5	sparc: use power_down to terminate emulation, rather than using trap. this fix hangup issue of tests/regress/sparc_reg.py	2016-02-15 15:51:14 +08:00
Nguyen Anh Quynh	3bd7fa4bfe	chmod -x qemu/target-i386/unicorn.c	2016-02-12 13:48:58 +08:00
coco	95beec805c	fixed memcpy that should be memmove	2016-02-11 16:38:50 +01:00
Nguyen Anh Quynh	b6897e2015	fix a compilation warning	2016-02-11 09:19:08 +08:00
Nguyen Anh Quynh	6478a24404	Merge branch 'gdt_idt' of https://github.com/cseagle/unicorn into cseagle-gdt_idt	2016-02-06 17:31:42 +08:00
Nguyen Anh Quynh	e73cbf1c88	arm: UC_QUERY_MODE return hardware mode (see issue #397)	2016-02-06 09:47:57 +08:00
Chris Eagle	dec3615d12	ldtr and tr limit is 20 bits, not 16 bits	2016-02-04 19:26:47 -08:00
Chris Eagle	b49358524f	fix reg_read casting for x86 segment registers	2016-02-04 19:22:39 -08:00
Chris Eagle	4cb43be5bf	fix reg_read casting for x86 segment registers	2016-02-04 19:20:59 -08:00
Chris Eagle	49b9f4f8da	uc_x86_mmr type available in qemu/target-i386/unicorn.c	2016-02-04 19:09:41 -08:00
Chris Eagle	c339ced218	file perms	2016-02-04 17:18:24 -08:00
Chris Eagle	f3dc2522a0	read/write of x86 segment registers should modify selector field not base field	2016-02-04 17:17:40 -08:00
Chris Eagle	59f7bf3be7	file perms	2016-02-04 16:48:27 -08:00
Chris Eagle	e59382e030	updated gdtr/idtr/ldtr/tr read/write code	2016-02-04 16:44:52 -08:00
Chris Eagle	9977054a15	add support for setting gdtr, idtr, ldtr, and tr programatically	2016-02-03 09:22:29 -08:00
Nguyen Anh Quynh	20b01a6933	fix merge conflict	2016-02-01 12:08:38 +08:00
Nguyen Anh Quynh	cfaac6921b	c89	2016-02-01 12:05:46 +08:00
danghvu	36e53ad8a1	Fix arm & arm64 memleaks	2016-01-31 16:22:20 -06:00
Nguyen Anh Quynh	c8569d8128	arm: fix change PC feature. now tests/regress/callback-pc.py passes	2016-01-28 16:03:19 +08:00
Nguyen Anh Quynh	5a04bcb115	allow to change PC during callback. this solves issue #210	2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh	e750a4e97c	when uc_mem_exec() remove EXE permission, quit current TB & continue emulating with TB flushed. this fixes issue in PR #378	2016-01-28 00:56:55 +08:00
Nguyen Anh Quynh	48ab148d1c	Merge branch 'hook'	2016-01-26 22:52:29 +08:00
Nguyen Anh Quynh	2341f5dd1a	code style	2016-01-26 17:37:48 +08:00
Willi Ballenthin	a640b76b94	qemu-thread-posix: bail on mutex errors ... partially addresses #400	2016-01-24 22:46:13 -05:00
Nguyen Anh Quynh	6f3d48077e	rename UC_QUERY_ARM_MODE to a more generic name UC_QUERY_MODE. make all bindings support this new constant	2016-01-24 01:08:23 +08:00
Nguyen Anh Quynh	4dbad9aa9b	add new API uc_query() to query internal status of emulator at runtime	2016-01-23 17:14:44 +08:00
Nguyen Anh Quynh	38d1443504	Merge branch 'hook-refactor' of https://github.com/lunixbochs/unicorn into lunixbochs-hook-refactor	2016-01-23 13:24:12 +08:00
Ryan Hileman	2ac1281f82	rework code/block tracing	2016-01-22 19:07:50 -08:00
Nguyen Anh Quynh	249e2ac0a0	Merge branch 'hook-refactor' of https://github.com/lunixbochs/unicorn into lunixbochs-hook-refactor	2016-01-23 10:58:37 +08:00
Ryan Hileman	0886ae8ede	rework code/block tracing	2016-01-22 18:42:27 -08:00
Ryan Hileman	93052f6566	refactor to allow multiple hooks for one type	2016-01-22 18:41:43 -08:00
xorstream	b4b83ff207	moar fixes	2016-01-23 12:56:47 +11:00
xorstream	d8aaa2f44c	Fixes to runtime arm mask checks	2016-01-23 12:44:12 +11:00
xorstream	678d645b80	Fix uc_mode usage in source code	2016-01-23 12:29:22 +11:00
xorstream	8763d426c2	Fix uc_mode usage in source code	2016-01-23 12:08:49 +11:00
Nguyen Anh Quynh	6490b4f2a9	arm64: fix the issue of multiple definition of aarch64_tb_set_jmp_target (issue #387)	2016-01-22 22:44:18 +08:00
Nguyen Anh Quynh	309abbe453	remove qemu/config-all-disas.mak	2016-01-22 17:11:57 +08:00
Nguyen Anh Quynh	3eb51116b9	arm64: fix the access to tcg_op_defs[] in arm64 backend (issue #387)	2016-01-22 11:35:01 +08:00
Nguyen Anh Quynh	840eb54f05	Revert "arm64: fix the access to tcg_op_defs[] in arm64 backend (issue #387)" ... This reverts commit 3000ca6abf.	2016-01-22 11:33:36 +08:00
Nguyen Anh Quynh	3000ca6abf	arm64: fix the access to tcg_op_defs[] in arm64 backend (issue #387)	2016-01-22 11:33:28 +08:00
Nguyen Anh Quynh	07bd81bda6	do not redefine tb_set_jmp_target1. this partly fixes issue #387	2016-01-22 11:29:22 +08:00
Nguyen Anh Quynh	839ef672b0	only declare use_idiv_instructions_rt when __ARM_ARCH_EXT_IDIV__ is not defined	2016-01-19 00:19:28 +08:00
Nguyen Anh Quynh	3b52af4fbd	avoid confusion between macro & variable use_idiv_instructions (ARM backend)	2016-01-18 23:53:50 +08:00
Nguyen Anh Quynh	d9249b91c2	add some missing symbols for ARM backend	2016-01-18 20:42:45 +08:00
petevine	8db7f79daf	Finish adding getauxval	2016-01-18 12:48:49 +01:00
petevine	1bf85461c2	Add getauxval.c back	2016-01-18 12:47:32 +01:00
Nguyen Anh Quynh	7695fb1578	x86: no need to reset env->invalid_error in x86_reg_reset() as we always do that in cpu_exec()	2016-01-12 01:01:11 +08:00
farmdve	c9f4bd27cc	Reset env->invalid_error before executing a translation block.	2016-01-11 18:12:57 +02:00
Nguyen Anh Quynh	a0aa26d6ee	c89	2016-01-10 23:34:36 +08:00
Nguyen Anh Quynh	580bc7b56a	cleanup	2016-01-10 23:10:00 +08:00
farmdve	036763d6ae	Fix memory leaks as reported by DrMemory and Valgrind. ... ARM and probably the rest of the arches have significant memory leaks as they have no release interface. Additionally, DrMemory does not have 64-bit support and thus I can't test the 64-bit version under Windows. Under Linux valgrind supports both 32-bit and 64-bit but there are different macros and code for Linux and Windows.	2016-01-08 01:42:56 +02:00
Nguyen Anh Quynh	13726b3d40	Merge branch 'master' into cygwin	2016-01-07 23:17:32 +07:00
farmdve	2304bbfc96	Remove more instances of tcg_register_jit	2016-01-07 16:39:41 +02:00
Nguyen Anh Quynh	bfeb08d1ba	fix some compilation warning	2016-01-06 14:11:21 +08:00
Nguyen Anh Quynh	e8a295991f	update qemu/header_gen.py	2016-01-06 00:44:29 +07:00
Nguyen Anh Quynh	e0cb02569e	remove unused tcg_register_jit() and related code	2016-01-05 16:02:34 +07:00
Nguyen Anh Quynh	075ccadbe9	x86: set s->pc in disas_insn() early to fix uninitialized read issue. bug reported by @farmdve	2016-01-03 08:25:51 +07:00
Nguyen Anh Quynh	19930b0514	spaces	2016-01-01 14:15:01 +08:00
Nguyen Anh Quynh	b3ebd1b7cb	Merge branch 'master' of https://github.com/iroiro123/unicorn into iroiro123-master	2016-01-01 14:01:39 +08:00
Nguyen Anh Quynh	f935469658	mips: handle memory redirect for all APIs. this fixes issue #347	2015-12-28 15:19:30 +08:00
Nguyen Anh Quynh	f10d79e95f	x86: fix a compilation warning on unused variable	2015-12-28 13:06:25 +08:00
Nguyen Anh Quynh	b5feddbf1e	indentation	2015-12-28 13:04:59 +08:00
Nguyen Anh Quynh	99b401c609	Merge branch 'la-fixed' of https://github.com/JCYang/unicorn into JCYang-la-fixed	2015-12-28 12:21:31 +08:00
Spl3en	bb375e4fa9	Reset correctly the register CR0 in protected mode by calling cpu_x86_update_cr0 instead of setting it manually.	2015-12-25 04:55:15 +01:00
Spl3en	9ca993d8aa	Restore the protected mode check.	2015-12-24 18:39:19 +01:00
Spl3en	4c3ad139ea	(Fix #341) SYSENTER instruction is not properly hooked with uc_hook_add in x86 emulation. ... helper_sysenter in qemu/target-i386/seg_helper.c didn't check properly if a call interrupt callback was registred. It has been fixed by copying the helper_syscall behavior.	2015-12-24 16:00:22 +01:00
Nguyen Anh Quynh	ed319bda0b	x86: identity map guest address to host address. this fixes issue #300	2015-12-24 09:51:17 +08:00
Nguyen Anh Quynh	4117a111eb	mips: handle hook callback for blikely instruction properly. this fixes issue #330, #331	2015-12-23 01:40:03 +08:00
JC Yang	8ef018a2cb	Fix possible wrong conditional branch in generated host code by fixing ... the tcg_liveness_analysis(). Refer to https://github.com/unicorn-engine/unicorn/issues/287 for further info.	2015-12-21 18:01:01 +08:00
Hiroyuki Uekawa	6445c80b29	Build for Cygwin	2015-12-20 22:00:35 +09:00
Nguyen Anh Quynh	b72671c6d5	sparc, arm, m68k: check for exit request after every hooked instruction	2015-12-20 12:28:15 +08:00
Nguyen Anh Quynh	4f268febb4	mips: check for exit request after every hooked instruction. this fix issue #329	2015-12-20 12:23:36 +08:00
Nguyen Anh Quynh	771f9f7c3b	fix conflicts when merging map-ptr branch to master branch	2015-12-17 08:12:02 +08:00
Nguyen Anh Quynh	8d3265d9e1	mips: remove unused variable is_bc_slot	2015-12-16 23:06:17 +08:00
xorstream	395251d3e8	Fix codehook for MIPS instructions in delay slot	2015-12-15 17:02:56 +11:00
Nguyen Anh Quynh	74aeef217c	Merge branch 'master' of https://github.com/unicorn-engine/unicorn	2015-12-13 13:11:54 +08:00
Nguyen Anh Quynh	bc63102e50	mips: only patch instruction size when there is a callback on the instruction. this fixes issue #282	2015-12-13 13:11:40 +08:00
farmdve	8b79a872d0	Fix segfault introduced in my previous commits.	2015-12-11 22:35:25 +02:00
Nguyen Anh Quynh	f21fa3d966	do not flush TB when l1_map is uninitialized. this fixes issue #280, #284	2015-12-12 03:09:38 +08:00
Nguyen Anh Quynh	a142611f56	sparc: set compute functions for icc_table[] & xcc_table[]. this fixes issue #289	2015-12-12 00:41:09 +08:00
Nguyen Anh Quynh	74986cc59a	g_free() can handle NULL pointer	2015-12-11 11:25:35 +08:00
farmdve	3e57615c76	Fix uc_mem_unmap memory leak and in uc_close. ... It appears the problem is that we are not calling the memory region destructor. After modifying memory_unmap to include the destructor call for the memory region, the memory is freed. Furthermore in uc_close we must explicitly free any blocks that were not unmapped by the user to prevent leaks. This should fix issue 305.	2015-12-11 02:42:31 +02:00
Ryan Hileman	230cbd5330	add permissions to map_ptr api	2015-11-28 11:28:31 -08:00
Nguyen Anh Quynh	4a759cebb5	set permission for memory region allocated by memory_map_ptr(). this fixes the segfault in sample_x86.c, function test_x86_map_ptr()	2015-11-28 17:11:27 +08:00
Ryan Hileman	6d21ebabea	implement host-controlled memory mapping for #261	2015-11-27 23:30:36 -08:00
Nguyen Anh Quynh	42b8879bb2	Merge branch 'master' of https://github.com/farmdve/unicorn into farmdve-master	2015-11-18 00:45:55 +08:00
Nguyen Anh Quynh	3302b9798c	add some debug helper on generated machine code	2015-11-18 00:43:18 +08:00
farmdve	65a649dec0	Fix issue #269 ... Patch from here http://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg03848.html Also fix another potential issue with constants from bbeb82395e (diff-9e0011b4d4a5890b309421630e6d86c3)	2015-11-17 18:34:38 +02:00
Nguyen Anh Quynh	edaea7020b	x86: on self-modifying code, generate JIT code until end of block. this fixes issue #266	2015-11-16 21:55:42 +08:00
Nguyen Anh Quynh	9099755ca1	flush JIT cache before finishing emulation. this fixes issue #263. TODO: optimize this for better performance	2015-11-13 23:57:03 +08:00
farmdve	1ba39a582c	change tabs to whitespaces...	2015-11-13 16:53:01 +02:00
farmdve	661714d0c2	Potential fix for issue #262/#263	2015-11-13 16:51:59 +02:00
Nguyen Anh Quynh	d126644bb2	Merge pull request #259 from lunixbochs/multiarch ... improve multiarch support	2015-11-12 15:11:06 +08:00
Ryan Hileman	ad5cd37551	improve multiarch support	2015-11-11 22:48:21 -08:00
Nguyen Anh Quynh	2f297bdd3a	handle some errors properly so avoid exit() during initialization. this fixes issue #237	2015-11-12 01:43:41 +08:00
Nguyen Anh Quynh	272293556a	do not abort() when memory is insufficient. this fixes issue #244	2015-11-10 11:44:29 +08:00
Nguyen Anh Quynh	938d0b89eb	x86: check for exit request after every hooked instruction. this should fix issue #232	2015-11-07 01:02:45 +08:00
Nguyen Anh Quynh	51323c9c17	x86: properly calculate EFLAGS when UC_HOOK_CODE is used. this should fix issue #246	2015-11-05 20:26:39 +08:00
Nguyen Anh Quynh	b66a323b19	do not free MemoryRegion in memory_unmap() because it will be unref later in memory_region_unref(). this fixes issue #202	2015-10-28 01:26:59 +08:00
Nguyen Anh Quynh	3a36e327ab	support memory redirection, so the issue #217 is fixed	2015-10-27 14:37:03 +08:00
Ryan Hileman	8c60d0dca5	allow setting x86 segment base to host-sized value	2015-10-23 00:15:08 -07:00
Nguyen Anh Quynh	142d3a6f72	arm: allow to read CPSR register	2015-10-17 15:59:27 +08:00
feliam	b43f89566f	Bugfix	2016-03-15 12:17:40 -03:00
Nguyen Anh Quynh	75e5fb466c	x86: fix writing to UC_X86_REG_FPCW	2016-03-14 09:27:46 +08:00
feliam	23b3f651f9	Indentation	2016-03-10 07:45:36 -03:00
feliam	0a3799eada	FPU control word and tags	2016-03-09 19:14:33 -03:00
feliam	ff66a72d7b	GDT/LDT/IDT/FPU access from python bingings	2016-03-09 18:07:38 -03:00
Nguyen Anh Quynh	600a1af710	Merge branch 'master' of https://github.com/unicorn-engine/unicorn	2015-10-03 15:46:19 +08:00
Nguyen Anh Quynh	9e64cba6ec	Rename some hook related enums: ... - UC_ERR_READ_INVALID -> UC_ERR_READ_UNMAPPED - UC_ERR_WRITE_INVALID -> UC_ERR_WRITE_UNMAPPED - UC_ERR_FETCH_INVALID -> UC_ERR_FETCH_UNMAPPED - UC_MEM_READ_INVALID -> UC_MEM_READ_UNMAPPED - UC_MEM_WRITE_INVALID -> UC_MEM_WRITE_UNMAPPED - UC_MEM_FETCH_INVALID -> UC_MEM_FETCH_UNMAPPED - UC_HOOK_MEM_READ_INVALID -> UC_HOOK_MEM_READ_UNMAPPED - UC_HOOK_MEM_WRITE_INVALID -> UC_HOOK_MEM_WRITE_UNMAPPED - UC_HOOK_MEM_FETCH_INVALID -> UC_HOOK_MEM_FETCH_UNMAPPED - UC_HOOK_MEM_INVALID -> UC_HOOK_MEM_UNMAPPED This also renames some newly added macros to use _INVALID postfix: - UC_HOOK_MEM_READ_ERR -> UC_HOOK_MEM_READ_INVALID - UC_HOOK_MEM_WRITE_ERR -> UC_HOOK_MEM_WRITE_INVALID - UC_HOOK_MEM_FETCH_ERR -> UC_HOOK_MEM_FETCH_INVALID - UC_HOOK_MEM_ERR -> UC_HOOK_MEM_INVALID Fixed all the bindings Java, Go & Python.	2015-09-30 14:46:55 +08:00
Nguyen Anh Quynh	3ca8774f1a	arm: properly handle the case when first insn in block is until address	2015-09-30 14:42:08 +08:00
Nguyen Anh Quynh	4a42041a83	handle 'bad ram pointer' case. this fixes issue #159	2015-09-29 18:22:22 +08:00
Nguyen Anh Quynh	2b0b4169bc	mips: advance PC for SYSCALL instruction. this fixes issue #157	2015-09-28 10:58:43 +08:00
Nguyen Anh Quynh	53ce8f217d	mips: handle delay slot better for branch instructions. this should fix issue #155	2015-09-27 15:05:40 +08:00
Nguyen Anh Quynh	728fe750b9	Merge pull request #140 from cherepanov74/master ... Fixes crash on Windows 64bit	2015-09-27 11:10:02 +08:00
Nguyen Anh Quynh	886946dcf4	do not use syscall to quit emulation. this can fix issues #147 & #148	2015-09-26 16:49:00 +08:00
Nguyen Anh Quynh	15f087be74	Merge branch 'master' of https://github.com/unicorn-engine/unicorn	2015-09-26 10:44:15 +08:00
Nguyen Anh Quynh	90eb8f2e72	This commit continues the PR #111 ... - Allow to register handler separately for invalid memory access - Add new memory events for hooking: - UC_MEM_READ_INVALID, UC_MEM_WRITE_INVALID, UC_MEM_FETCH_INVALID - UC_HOOK_MEM_READ_PROT, UC_HOOK_MEM_WRITE_PROT, UC_HOOK_MEM_FETCH_PROT - Rename UC_ERR_EXEC_PROT to UC_ERR_FETCH_PROT - Change API uc_hook_add() so event type @type can be combined from hooking types	2015-09-24 14:18:02 +08:00
Sean Heelan	dfb4a9d9ad	Revert "Remove uc_cb_eventmem_t as it is identical to uc_cb_hookmem_t" ... As pointed out by aquynh the return types are actually different. A uc_cb_eventmem_t callback returns a bool, while uc_cb_hookmem_t has a void return type. This reverts commit cb2b97f26c.	2015-09-23 12:51:47 +07:00
Sean Heelan	cb2b97f26c	Remove uc_cb_eventmem_t as it is identical to uc_cb_hookmem_t, as per ... issue #111	2015-09-22 12:37:05 +07:00
Nguyen Anh Quynh	14a01b5186	mips: handle delay slot so do not duplicate calling instruction handler. this fixes issue #133	2015-09-22 11:59:53 +08:00
Nguyen Anh Quynh	a853eb6363	mips, m68k: early check to see if the address of BB is the until address	2015-09-22 10:24:26 +08:00
danghvu	0c67f41ed9	Fix issue #118	2015-09-21 20:30:05 -05:00
Nguyen Anh Quynh	d7d4be25b1	arm64: early check to see if the address of this block is the until address	2015-09-21 10:26:33 +08:00
Nguyen Anh Quynh	9aa04d9496	tb_gen_code(): only check to link next page if tb->size > 0 (so we skip empty block)	2015-09-20 00:05:17 +07:00
Nguyen Anh Quynh	5005b4a6e2	arm: early check to see if the address of this block is the until address	2015-09-17 09:16:57 +07:00
Nguyen Anh Quynh	d6b9c31dc9	sparc: more cleanup	2015-09-16 16:04:12 +07:00
mothran	893e6abcbd	first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV	2015-09-15 23:12:03 -07:00
mothran	f4894a1c77	removed unneed cases in the switch statement	2015-09-14 20:44:50 -07:00
mothran	6b521e9e9b	update the sparc reg read/write to include o/l/i registers	2015-09-14 20:03:32 -07:00
cherepanov74	2fc483ec47	Fixes crash on Windows 64bit	2015-09-14 20:42:29 +02:00
mothran	7dc41a8e4e	update the regwptr upon reset	2015-09-13 18:10:28 -07:00
mothran	657a6c3e25	modified the sparc reg get/set functions to use the current reg window ptr	2015-09-12 10:29:35 -07:00
Nguyen Anh Quynh	ab337ef65a	Merge branch 'master' of https://github.com/unicorn-engine/unicorn	2015-09-11 15:58:58 +08:00
mothran	afecfee565	added SPARC sp / fp registers, also updated uint32_t's to uint64_t's in SPARC64	2015-09-10 23:20:52 -07:00
Nguyen Anh Quynh	d7ef204398	rename error codes ERR_MEM_READ, ERR_MEM_WRITE, ERR_MEM_FETCH	2015-09-09 16:25:48 +08:00
Nguyen Anh Quynh	d3d38d3f21	handle read/write/fetch from unaligned addresses. this adds new error codes UC_ERR_READ_UNALIGNED, UC_ERR_WRITE_UNALIGNED & UC_ERR_FETCH_UNALIGNED	2015-09-09 15:52:15 +08:00
Nguyen Anh Quynh	18b6680e96	mips: disable debug output	2015-09-08 23:56:25 +08:00
Nguyen Anh Quynh	2929138c99	sparc: do not call INSN handler on until-address, and verify until-address early when translating block in JIT frontend.	2015-09-08 13:26:53 +08:00
Nguyen Anh Quynh	7a5d790ade	rename UC_MEM_EXE to UC_MEM_FETCH	2015-09-08 12:55:56 +08:00
Nguyen Anh Quynh	c1dd9fbfdf	arm64: handle SP register. this fixes issue #122	2015-09-08 08:40:42 +08:00
Nguyen Anh Quynh	6c132bc673	arm: fix #114 by enabling cortex-a15 model. FIXME: enable this on demand with an API	2015-09-08 01:08:37 +08:00
Nguyen Anh Quynh	3ac8615cbb	arm: handle invalid instruction. this fixes issue #114	2015-09-08 00:43:09 +08:00
Nguyen Anh Quynh	9e4ed32e8a	x86: handle SYSCALL even if there is no handler	2015-09-07 10:19:45 +08:00
Nguyen Anh Quynh	a166c24f8e	x86: correct EIP of INT instruction by updating it only after calling interrupt handler	2015-09-06 14:58:11 +08:00
Chris Eagle	e9c6b11506	add mem_api sample program and fix check for wrong NX related constant in cputlb.c	2015-09-04 10:27:03 -07:00
Chris Eagle	8cfd902e4b	Move mem_xxx samples to regress. Add check to only flush tlb when unmapping if there is a current cpu	2015-09-04 00:48:24 -07:00
Nguyen Anh Quynh	022f8d82d1	handle memory fetch as invalid memory access. now we can also report error if exec memory is unmapped (UC_ERR_MEM_FETCH)	2015-09-04 11:55:17 +08:00
Nguyen Anh Quynh	84e3b5c897	cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98	2015-09-04 11:17:08 +08:00
Jonathon Reinhart	da46071c7d	bring new code and samples up-to-date with API changes	2015-09-03 22:15:49 -04:00
Jonathon Reinhart	5e9d07a40a	Merge remote-tracking branch 'upstream/master' into change-handle-based-api	2015-09-03 22:01:52 -04:00
Chris Eagle	2da46caef7	smooth out split_region related code	2015-09-03 12:26:36 -07:00
Nguyen Anh Quynh	6ca85a72ed	simplify uc_mem_protect() & uc_mem_unmap()	2015-09-04 01:02:38 +08:00
Nguyen Anh Quynh	9f9d57e84f	cleaning & indentation	2015-09-03 18:16:49 +08:00
Nguyen Anh Quynh	b8d4240240	solve merging conflict	2015-09-03 18:05:21 +08:00
Jonathon Reinhart	bd0a6921cc	Merge remote-tracking branch 'upstream/master' into change-handle-based-api	2015-09-02 21:04:43 -04:00
Nguyen Anh Quynh	be659d201d	fix confusion betweet UC_MEM_xxx & UC_HOOK_MEM_xxx. fix issue #93	2015-09-03 01:13:57 +08:00
Nguyen Anh Quynh	2d9db36a2b	fix some errors introduced by the last commit on qemu-thread-win32.c	2015-09-02 01:34:23 -07:00
Nguyen Anh Quynh	8b39ec5b0c	initial support to remove a static variable in qemu-thread-win32.c	2015-09-02 16:13:12 +08:00
Nguyen Anh Quynh	a94e31165d	x86: fix issue #95	2015-09-02 12:00:43 +08:00
Ryan Hileman	db8f499fe9	fix crash on some SSE instructions	2015-09-01 19:12:51 -07:00
Chris Eagle	49d1fa7ebd	Merge branch 'master' into mem_map_ex_cse	2015-09-01 12:13:53 -07:00
Chris Eagle	2c4f3769d4	clean up mem_protect related constants and error codes	2015-09-01 12:10:09 -07:00
Jonathon Reinhart	2c802a3e4b	Merge remote-tracking branch 'upstream/master' into change-handle-based-api ... # Conflicts: # qemu/target-i386/unicorn.c	2015-09-01 13:17:03 -04:00
Nguyen Anh Quynh	90fc201f8d	x86: enable bunch of instructions via CPUID. this fixes issue #91	2015-09-02 00:16:45 +08:00
Chris Eagle	73027026ce	Merge branch 'master' into mem_map_ex_cse	2015-08-31 23:49:54 -07:00
Chris Eagle	658e399776	clean up mem_protect related constants	2015-08-31 19:08:48 -07:00
Nguyen Anh Quynh	bea73ef213	stop emulation when hitting invalid code address. this fixes issue #82	2015-09-01 00:17:55 +08:00
Chris Eagle	b27e987932	Add target_page_size member to uc_struct to track TARGET_PAGE_SIZE	2015-08-31 01:00:44 -07:00
Chris Eagle	410e317e92	dont use explicit page size, use TARGET_PAGE_SIZE	2015-08-30 21:24:14 -07:00
Chris Eagle	9e4e96ff47	final updates for uc_mem_unmap, uc_mem_protect, and support ro UC_PROT_EXEC permission	2015-08-30 19:50:18 -07:00
mothran	6aa2b73bea	removed ifdef for x64 in fpu saving	2015-08-30 19:39:46 -07:00
mothran	e1ab761e8a	fixed typo	2015-08-30 19:32:39 -07:00
mothran	2b6f806759	removed testing printf	2015-08-30 19:22:41 -07:00
mothran	4cd5fa3811	fpip x64 fxsave working with using hflags to check CPU mode	2015-08-30 18:56:55 -07:00
mothran	912faf2c3c	after closer review, in x64 the the op size is 32 so data32 is set, can removed the unicorn dependency and regress/fpu_ip64.py still works	2015-08-30 18:04:28 -07:00
mothran	2febbb6021	Merge branch 'master' of github.com:unicorn-engine/unicorn into fpip_update	2015-08-30 11:13:23 -07:00
Chris Eagle	0a60fa4c8a	fix perms	2015-08-30 00:22:49 -07:00
Chris Eagle	942de0f2ae	implemented basic block splitting, uc_mem_unmap should work for sub=blocks or across contiguous blocks	2015-08-30 00:22:18 -07:00
Jonathon Reinhart	3bd705a060	Merge remote-tracking branch 'upstream/master' into change-handle-based-api	2015-08-30 00:23:51 -04:00
Chris Eagle	4a680b9277	Merge branch 'master' into mem_map_ex_cse	2015-08-29 21:22:33 -07:00
Chris Eagle	6beb1b8a13	intermediate commit, working unmap of complete blocks, still need sub-blocks, and cross block	2015-08-29 21:17:30 -07:00
Nguyen Anh Quynh	c23d387e2f	remove redundant uc_struct.ram	2015-08-30 10:51:28 +08:00
mothran	b7d60313b5	added 64 bit mode to the fstenv helper function, also a fpu_ip64.py regress script	2015-08-29 01:56:36 -07:00
Chris Eagle	592cbc6eaf	conflict resolution with merge master	2015-08-28 23:51:56 -07:00
mothran	79184ff23d	Merge branch 'master' of github.com:unicorn-engine/unicorn into fpip_update	2015-08-28 23:40:25 -07:00
Chris Eagle	986096d443	fix file perms	2015-08-28 21:05:38 -07:00
Chris Eagle	94ac0f02e6	file permissions changes	2015-08-28 20:03:36 -07:00
Chris Eagle	eab6167241	Merge branch 'master' into mem_map_ex_cse	2015-08-28 19:00:39 -07:00
Chris Eagle	9ba59e4988	Step one towards uc_mem_protect, uc_mem_unmap, and support for UC_PROT_EXEC and NX regions	2015-08-28 18:59:45 -07:00
Nguyen Anh Quynh	6bd5e2efa7	chmod -x qemu/softmmu_template.h	2015-08-29 09:28:32 +08:00
mothran	feb8ced027	fixed the FPIP updates to correctly only work with non-control instructions and make sure the pc addr is correct	2015-08-28 10:39:11 -07:00
Nguyen Anh Quynh	b69180ad5a	Merge branch 'mem_map_ex' of https://github.com/cseagle/unicorn into cseagle-mem_map_ex	2015-08-28 18:47:18 +08:00
Chris Eagle	3452b47f7c	Add code to handle non-readable memory	2015-08-28 03:42:25 -07:00
mothran	933ef379b4	restricted fpip updates to only non-control instructions	2015-08-28 03:19:10 -07:00
Nguyen Anh Quynh	3b5df362d7	chmod -x <some source code>	2015-08-28 18:12:56 +08:00
Nguyen Anh Quynh	96a274c4aa	Merge branch 'mem_map_ex' of https://github.com/cseagle/unicorn into cseagle-mem_map_ex	2015-08-28 18:11:10 +08:00
Nguyen Anh Quynh	4a1c5ff071	x86: verify until address early when translating block in frontend. this should fix issue #63	2015-08-28 16:06:06 +08:00
Chris Eagle	9530b2daff	Remove MemoryBlock struct by consolidating in MemoryRegion. add new API uc_mem_protect. Add regress/mem_protect.c. Drop UC_PROT_EXEC for time being	2015-08-27 23:19:32 -07:00
mothran	59b09a71bf	first shot at getting FPIP working, need to remove all FP control instructions from being updated	2015-08-27 21:54:23 -07:00
Chris Eagle	bf32753c29	Merge branch 'master' into mem_map_ex	2015-08-27 19:17:06 -07:00
Chris Eagle	686acb7e6e	Detect all occurences of write to read only page. Add callback capability on write to read only. Add new error type UC_ERR_MEM_WRITE_RO and new access type UC_MEM_WRITE_RO for use in callback	2015-08-27 18:03:17 -07:00
Nguyen Anh Quynh	b335cf016c	do not generate basic-block callback when translation is broken in the middle due to full cache (all the remaining archs)	2015-08-27 21:09:00 +08:00
Chris Eagle	4b529bc56c	Free up all MemoryRegion* when uc is closed	2015-08-26 14:09:46 -07:00
Chris Eagle	00944b6cde	Add ability to mark memory are read only. Add new API uc_mem_map_ex to allow permissions to be passed. Change MemoryBlock to track created MemoryRegions. Add regress/ro_mem_test.c	2015-08-26 13:29:54 -07:00
Chris Eagle	b39f5d2a91	When checking for invalid memory always do the faster check of whether we are hooking env->uc->hook_mem_idx before doing the expensive check of scanning the memory map	2015-08-26 08:55:19 -07:00
Chris Eagle	095cdb5f9d	Merge remote-tracking branch 'upstream/master'	2015-08-26 08:25:37 -07:00
Jonathon Reinhart	8918deb1b2	change uch to uc_struct (target-m68k)	2015-08-26 09:02:16 -04:00
Jonathon Reinhart	fcb099805f	change uch to uc_struct (qemu)	2015-08-26 09:02:16 -04:00
Jonathon Reinhart	b57662e43d	change uch to uc_struct (target-i386)	2015-08-26 09:02:16 -04:00
Jonathon Reinhart	e7a8eb8976	change uch to uc_struct (target-sparc)	2015-08-26 09:02:16 -04:00
Jonathon Reinhart	15a774ac90	change uch to uc_struct (target-mips)	2015-08-26 09:02:16 -04:00
Jonathon Reinhart	622d5cd5f9	change uch to uc_struct (target-arm)	2015-08-26 09:02:16 -04:00
Jonathon Reinhart	6c4726c88e	change uch to uc_struct (ioport.c)	2015-08-26 09:02:16 -04:00
Nguyen Anh Quynh	192f07c503	reset invalid_error after callbacks decide to continue after invalid memory accesses	2015-08-26 16:15:38 +08:00
Chris Eagle	03e8b28d71	First cut at cleaning up uc_mem_map, eliminate map_begin and map_end, move tracking inside uc struct	2015-08-25 21:52:18 -07:00
Nguyen Anh Quynh	cc5d28e112	mips: fix issue #39	2015-08-26 09:39:09 +08:00
Nguyen Anh Quynh	2fac7fc2e4	x86: better support for 16bit mode	2015-08-26 00:39:46 +08:00
Nguyen Anh Quynh	39d3856871	when block size is unknown because the translation cache is full, assign it value 0	2015-08-25 16:10:05 +08:00
Nguyen Anh Quynh	c3e95ec34e	x86: do not generate basic-block callback when translation is broken in the middle due to full cache	2015-08-25 14:50:55 +08:00
Jonathon Reinhart	9163bba812	restore mode of .[ch] files ... These were marked as executable in 5c3b6819, likely due to a Windows filesystem being involved. This can be avoided: http://stackoverflow.com/q/1580596/119527	2015-08-24 21:19:12 -04:00
Chris Eagle	5c3b681945	Add const to uc_reg_write and derivitives	2015-08-24 09:42:50 -07:00
Nguyen Anh Quynh	9d9c0d1a25	uc_emu_start() report error on illegal instruction at the output	2015-08-25 00:02:31 +08:00
pancake	c5d99777f4	Use const in uc_mem_write and derivates	2015-08-24 17:02:14 +02:00
mothran	2516de7ed8	renamed m68k enum constants	2015-08-23 21:56:24 -07:00
mothran	a167f7c456	renames the register constants so unicorn and capstone can compile together	2015-08-23 21:36:33 -07:00
Nguyen Anh Quynh	7ca9a07e1b	x86: enable SSE. this fixes issue #3	2015-08-23 10:41:14 +08:00
Nguyen Anh Quynh	4701fb80b4	code style: convert tabs to spaces	2015-08-23 09:06:31 +08:00
Nguyen Anh Quynh	e1baf2f36b	x86: support hooking SYSCALL/SYSENTER instructions. we no longer share the SYSCALL callback with interrupt instructions	2015-08-23 01:19:40 +08:00
Ryan Hileman	0ac3cf99d4	call int80 callback from x86_64 syscall helper	2015-08-21 16:26:02 -07:00
Nguyen Anh Quynh	344d016104	import	2015-08-21 15:04:50 +08:00