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3957 commits

Author SHA1 Message Date
Peter Maydell 1301becdab
tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE
Add support for MMU protection regions that are smaller than
TARGET_PAGE_SIZE. We do this by marking the TLB entry for those
pages with a flag TLB_RECHECK. This flag causes us to always
take the slow-path for accesses. In the slow path we can then
special case them to always call tlb_fill() again, so we have
the correct information for the exact address being accessed.

This change allows us to handle reading and writing from small
regions; we cannot deal with execution from the small region.

Backports commit 55df6fcf5476b44bc1b95554e686ab3e91d725c5 from qemu
2018-11-16 21:35:54 -05:00
Lioncash 3a0ab1a64a
Partial backport of: exec.c: Handle IOMMUs in address_space_translate_for_iotlb()
We just want the parameter changes here.

Partial backport of commit 1f871c5e6b0f30644a60a81a6a7aadb3afb030ac from
qemu
2018-11-16 21:24:55 -05:00
Lioncash 1c0e09c467
m68k: Silence compiler warnings 2018-11-16 21:23:55 -05:00
Peter Maydell f694264212
target/arm: Remove antique TODO comment
Remove a TODO comment about implementing the vectored interrupt
controller. We have had an implementation of that for a decade;
it's in hw/intc/pl190.c.

Backports commit e24ad484909e7a00ca4f6332f3698facf0ba3394 from qemu
2018-11-16 18:24:49 -05:00
Peter Maydell 78906db067
tcg/tcg-op.h: Add multiple include guard
The tcg-op.h header was missing the usual guard against multiple
inclusion; add it.

(Spotted by lgtm.com's static analyzer.)

Backports commit a7ce790a029bd94eb320d8c69f38900f5233997e from qemu
2018-11-11 08:51:51 -05:00
Marc-André Lureau fc354aa464
memory: learn about non-volatile memory region
Add a new flag to mark memory region that are used as non-volatile, by
NVDIMM for example. That bit is propagated down to the flat view, and
reflected in HMP info mtree with a "nv-" prefix on the memory type.

This way, guest_phys_blocks_region_add() can skip the NV memory
regions for dumps and TCG memory clear in a following patch.

Backports commit c26763f8ec70b1011098cab0da9178666d8256a5 from qemu
2018-11-11 08:50:39 -05:00
Rudolf Marek fd56d45e19
target/i386: Clear RF on SYSCALL instruction
Fix the SYSCALL instruction in 64-bit (long mode). The RF flag
should be cleared in R11 as well as in the RFLAGS. Intel
and AMD CPUs behave same. AMD has this documented in the
APM vol 3.

Backports commit 1a1435dd61e28c1e3b70971107d72a7d05b28d03 from qemu
2018-11-11 08:41:09 -05:00
Peter Maydell 38a286ee9b
Update version for v3.1.0-rc0 release
Backports commit 4de6bb0c02ad3f0ec48f0f84ba1a65ab06e81b86 from qemu
2018-11-11 08:40:14 -05:00
Peter Maydell 84d5a60c15
target/arm: Fix ATS1Hx instructions
ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
on the EL2 translation regime) were implemented in commit 14db7fe09a2c8.
However, we got them wrong: these should do stage 1 address translations
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
making them perform stage 2 translations.

A few years later in commit 1313e2d7e2cd we forgot entirely that
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
"not supported yet". Remove the comment; there is no extra code
needed to handle these operations in do_ats_write(), because
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
which forces 64-bit PAR format.

Backports commit 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512 from qemu
2018-11-11 08:39:19 -05:00
Peter Maydell a445db5c02
target/arm: Set S and PTW in 64-bit PAR format
In do_ats_write() we construct a PAR value based on the result
of the translation. A comment says "S2WLK and FSTAGE are always
zero, because we don't implement virtualization".
Since we do in fact now implement virtualization, add the missing
code that sets these bits based on the reported ARMMMUFaultInfo.

(These bits are named PTW and S in ARMv8, so we follow that
convention in the new comments in this patch.)

Backports commit 0f7b791b35f24cb1333f779705a3f6472e6935de from qemu
2018-11-11 08:38:23 -05:00
Peter Maydell 5aa5ebbcc9
target/arm: Remove can't-happen if() from handle_vec_simd_shli()
In handle_vec_simd_shli() we have a check:

if (size > 3 && !is_q) {
    unallocated_encoding(s);
    return;
}

However this can never be true, because we calculate
int size = 32 - clz32(immh) - 1;
where immh is a 4 bit field which we know cannot be all-zeroes.
So the clz32() return must be in {28,29,30,31} and the resulting
size is in {0,1,2,3}, and "size > 3" is never true.

This unnecessary code confuses Coverity's analysis:
in CID 1396476 it thinks we might later index off the
end of an array because the condition implies that we
might have a size > 3.

Remove the code, and instead assert that the size is in [0..3],
since the decode that enforces that is somewhat distant from
this function.

Backports commit f6c98f91f56031141a47f86225fdc30f0f9f84fb from qemu
2018-11-11 08:37:16 -05:00
Richard Henderson 834514c676
softfloat: Don't execute divdeu without power7
The divdeu instruction was added to ISA 2.06 (Power7).
Exclude this block from older cpus.

Fixes: 27ae5109a2ba (softfloat: Specialize udiv_qrnnd for ppc64)

Backports commit 7370981bd1ef58b3c20ba8b83cc342d1c61bc773 from qemu
2018-11-11 08:33:46 -05:00
Richard Henderson 0557899c8e
target/arm: Conditionalize some asserts on aarch32 support
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.

Backports commit 0f8d06f16c9d1041d728d09d464462ebe713c662 from qemu
2018-11-11 08:32:46 -05:00
Laurent Vivier 26d8891d1b
target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED
Coldfire defines an "Unsupported instruction" exception if execution
of a valid instruction is attempted but the required hardware is not
present in the processor.

We use it with instructions that are in fact undefined or illegal,
and the exception expected in this case by the kernel is the
illegal exception, so this patch fixes that.

Backports commit b9f8e55bf7e994e192ab7360830731580384b813 from qemu
2018-11-11 08:30:57 -05:00
Richard Henderson 800c9db9c9
decodetree: Allow multiple input files
While it would be possible to concatenate input files with make,
passing the original input files to decodetree.py allows us to
generate error messages which allows compilation environments
(read: emacs) to next-error to the correct input file.

Backports commit 6699ae6a8e74381583622502db8bd47fac381c9e from qemu
2018-11-11 08:28:55 -05:00
Richard Henderson 4d49c004e4
decodetree: Remove insn argument from trans_* expanders
This allows trans_* expanders to be shared between decoders
for 32 and 16-bit insns, by not tying the expander to the
size of the insn that produced it.

This change requires adjusting the two existing users to match.

Backports commit 3a7be5546506be62d5c6c4b804119cedf9e367d6 from qemu
2018-11-11 08:27:01 -05:00
Richard Henderson 36a718c062
decodetree: Add !extern flag to argument sets
Allow argument sets to be shared between two decoders by avoiding
a re-declaration error. Make sure that anonymous argument sets
and anonymous formats have unique names.

Backports commit abd04f9290094f4eb7f3c07335766bbac3de22bb from qemu
2018-11-11 08:21:20 -05:00
Tao Xu 0aaa7f7ce9
i386: Add PKU on Skylake-Server CPU model
As the release document ref below link (page 13):
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

PKU is supported in Skylake Server (Only Server) and later, and
on Intel(R) Xeon(R) Processor Scalable Family. So PKU is supposed
to be in Skylake-Server CPU model. And PKU's CPUID has been
exposed to QEMU. But PKU can't be find in Skylake-Server CPU
model in the code. So this patch will fix this issue in
Skylake-Server CPU model.

Backports commit 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f from qemu
2018-11-11 08:09:47 -05:00
Tao Xu b004139ea1
i386: Add new model of Cascadelake-Server
New CPU models mostly inherit features from ancestor Skylake-Server,
while addin new features: AVX512_VNNI, Intel PT.
SSBD support for speculative execution
side channel mitigations.

Note:

On Cascadelake, some capabilities (RDCL_NO, IBRS_ALL, RSBA,
SKIP_L1DFL_VMENTRY and SSB_NO) are enumerated by MSR.
These features rely on MSR based feature support patch.
Will be added later after that patch's in.
http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00074.html

Backports commit c7a88b52f62b30c04158eeb07f73e3f72221b6a8 from qemu
2018-11-11 08:08:39 -05:00
Robert Hoo 24733280b2
x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.

Backports commit d86f963694df27f11b3681ffd225c9362de1b634 from qemu
2018-11-11 08:07:33 -05:00
Robert Hoo 947b021266
x86: Data structure changes to support MSR based features
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.

Backports commit 07585923485952bf4cb7da563c9f91fecc85d09c from qemu
2018-11-11 08:06:18 -05:00
Sebastian Andrzej Siewior a09a074255
i386: correct cpu_x86_cpuid(0xd)
Intel SDM says for CPUID function 0DH, sub-function 0:

| • ECX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components supported by this
| processor.
| • EBX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components corresponding to bits
| currently set in XCR0.

Backports commit de2e68c902f7b6e438b0fa3cfedd74a06a20704f from qemu
2018-11-11 07:52:43 -05:00
Cleber Rosa 7c94b86d31
scripts/decodetree.py: remove unused imports
Backports commit b25ab557c666ad666c8acbb27fd1b57244505fed from qemu
2018-11-11 07:34:19 -05:00
Cleber Rosa 40a33d2542
scripts/decodetree.py: fix reference to attributes
Backports commit cbcdf1a951aa605c43dc80a98a8cc366299e378c from qemu
2018-11-11 07:33:30 -05:00
Li Qiang 33422a04bc
cpu.h: fix a typo in comment
Found by reading the code.

Backports commit 7e63bc38adfcc5bd9e20e3dd8a170f0e8d830b60 from qemu
2018-11-11 07:32:05 -05:00
Li Qiang b79f16c331
memory.h: fix typos in comments
Backports commit 847b31f0d608bfcbc9ea11d5013ae62e956f32cd from qemu
2018-11-11 07:31:35 -05:00
Aleksandar Markovic 9137e4c201
target/mips: Amend MXU ASE overview note
Add prefix, suffix, operation descriptions, and other corrections
and amendments to the comment that describes MXU ASE.

Backports commit 093ade12179b6a3f679c100c0fe2a0a7d72068ba from qemu
2018-11-11 07:30:31 -05:00
Aleksandar Markovic 702abac53f
target/mips: Move MXU_EN check one level higher
Move MXU_EN check to the main MXU decoding function, to avoid code
repetition.

Backports commit e5bf8a08293a1c576f8b6094f4deae7bdafceade from qemu
2018-11-11 07:29:11 -05:00
Craig Janeczek f2c3e173ad
target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Backports commit 4ca837218c92139cb85d214a25d1d1bc3f7e044c from qemu
2018-11-11 07:24:27 -05:00
Craig Janeczek bd75529f43
target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU
Backports commit a9a4181bdbf9eea81d718894bda607bd01b00f5b from qemu
2018-11-11 07:21:44 -05:00
Craig Janeczek 97b7155db1
target/mips: Add emulation of MXU instruction D16MAC
Backports commit e67915b4277932def37b15cf8434323d096edeaa from qemu
2018-11-11 07:18:12 -05:00
Craig Janeczek db2e8c1761
target/mips: Add emulation of MXU instruction D16MUL
Backports commit 72c9bcf89c59ee1a8e4545069de3efcbeb4d4833 from qemu
2018-11-11 07:00:00 -05:00
Craig Janeczek cad0283888
target/mips: Add emulation of MXU instruction S8LDD
Backports commit be57bcdb2ed8a4b41be05c8dc42bdec5174f43d6 from qemu
2018-11-11 06:15:57 -05:00
Aleksandar Markovic 914c0cea7c
target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Backports commit 87860df5511b972f0234a6b2cfaad5227c79b6b4 from qemu
2018-11-11 06:12:44 -05:00
Craig Janeczek 3862cd205d
target/mips: Add emulation of MXU instructions S32I2M and S32M2I
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.

Backports commit 96992d1aa1b250c0fffc1ff2dad5e6e4f0b9815b from qemu
2018-11-11 06:11:09 -05:00
Craig Janeczek 8a03757fb0
target/mips: Add emulation of non-MXU MULL within MXU decoding engine
Backports commit 11d56f61036091206f085e58cff72b6872911d3a from qemu
2018-11-11 06:05:45 -05:00
Craig Janeczek 839f5babde
target/mips: Add bit encoding for MXU operand getting pattern 'optn3'
Backports commit 53f1131fde02ae49e1f794f811a60fda32c72dca from qemu
2018-11-11 06:04:47 -05:00
Craig Janeczek bc98daa7c5
target/mips: Add bit encoding for MXU operand getting pattern 'optn2'
Backports commit a35723f4ce026ebad0c34f18ea874813799058f0 from qemu
2018-11-11 06:04:18 -05:00
Aleksandar Markovic 9cf4a32b0d
target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
Backports commit 5bb29992397217ae7d09d2192c5b56aefaf6cd11 from qemu
2018-11-11 06:03:47 -05:00
Craig Janeczek bbb2a1e62b
target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'
Backports commit b70bb918e2f5063975ba845fb9456ada25e3db91 from qemu
2018-11-11 06:03:08 -05:00
Aleksandar Markovic 5e92fd655f
target/mips: Add MXU decoding engine
Add MXU decoding engine: add handlers for all instruction pools,
and main decode handler. The handlers, for now, for the purpose
of this patch, contain only sceleton in the form of a single
switch statement.

Backports commit 03f400883a1dd92fac5b0d9127b38e34c9a722d7 from qemu
2018-11-11 06:01:58 -05:00
Aleksandar Markovic 1029b4151d
target/mips: Add and integrate MXU decoding engine placeholder
Provide the placeholder and add the invocation logic for MXU
decoding engine.

Backports commit 0a348b9a4e115deb28856e650b8fe5277e291c23 from qemu
2018-11-11 05:59:20 -05:00
Aleksandar Markovic ed037799c7
target/mips: Amend MXU instruction opcodes
Amend MXU instruction opcodes. Pool04 is actually only instruction
OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
subfield 'aptn1'.

Backports commit eab0bdb07cbed1131be2d1f541059c7b96b05e32 from qemu
2018-11-11 05:58:35 -05:00
Craig Janeczek 8429d98b40
target/mips: Define a bit for MXU in insn_flags
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Backports commit a031ac61619294ae473a78d1834e757fad8b59e5 from qemu
2018-11-11 05:52:18 -05:00
Craig Janeczek 58dc377890
target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Backports commit eb5559f67dc8dc12335dd996877bb6daaea32eb2 from qemu.
2018-11-11 05:50:52 -05:00
Aleksandar Markovic a1ba04ae44
target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
Coverity found two fallthroughs that miss break statement. Fix them.

Backports commit 2431a422d325c1832d77dd64fa3135ec303b00de from qemu
2018-11-11 05:44:23 -05:00
Dimitrije Nikolic 948d49db81
target/mips: Implement emulation of nanoMIPS EVA instructions
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.

Backports commit d046a9ea1b8877a570a8b12a2d0125ec59fe5b22 from qemu
2018-11-10 12:18:11 -05:00
Aleksandar Markovic 006f0a5873
target/mips: Add nanoMIPS CRC32 instruction pool
Backports commit ba1e81171fb761aea9a9a4ccadedf808e34eaae2 from qemu
2018-11-10 12:15:01 -05:00
Aleksandar Markovic 9f728678ec
target/mips: Fix decoding of ALIGN and DALIGN instructions
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.

Backports commit 373ecd3823f949fd550ec49685299e287af5753e from qemu
2018-11-10 12:14:01 -05:00
Aleksandar Markovic caa67a9d17
target/mips: Fix the title of translate.c
Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.

Backports commit ab99e0e44bc7b0e2e52d9083a673866b18470536 from qemu
2018-11-10 12:12:27 -05:00
Fredrik Noring a93e15aad1
target/mips: Define the R5900 CPU
The primary purpose of this change is to support programs compiled by
GCC for the R5900 target and thereby run R5900 Linux distributions, for
example Gentoo.

GCC in version 7.3, by itself, by inspection of the GCC source code
and inspection of the generated machine code, for the R5900 target,
only emits two instructions that are specific to the R5900: the three-
operand MULT and MULTU. GCC and libc also emit certain MIPS III
instructions that are not part of the R5900 ISA. They are normally
trapped and emulated by the Linux kernel, and therefore need to be
treated accordingly by QEMU.

A program compiled by GCC is taken to mean source code compiled by GCC
under the restrictions above. One can, with the apparent limitations,
with a bit of effort obtain a fully functioning operating system such
as R5900 Gentoo. Strictly speaking, programs need not be compiled by
GCC to make use of this change.

Instructions and other facilities of the R5900 not implemented by this
change are intended to signal provisional exceptions. One such example
is the FPU that is not compliant with IEEE 754-1985 in system mode. It
is therefore provisionally disabled. In user space the FPU is trapped
and emulated by IEEE 754-1985 compliant software in the kernel, and
this is handled accordingly by QEMU. Another example is the 93
multimedia instructions specific to the R5900 that generate provisional
reserved instruction exception signals.

One of the benefits of running a Linux distribution under QEMU is that
programs can be compiled with a native compiler, where the host and
target are the same, as opposed to a cross-compiler, where they are
not the same. This is especially important in cases where the target
hardware does not have the resources to run a native compiler.

Problems with cross-compilation are often related to host and target
differences in integer sizes, pointer sizes, endianness, machine code,
ABI, etc. Sometimes cross-compilation is not even supported by the
build script for a given package. One effective way to avoid those
problems is to replace the cross-compiler with a native compiler. This
change of compilation methods does not resolve the inherent problems
with cross-compilation.

The native compiler naturally replaces the cross-compiler, because one
typically uses one or the other, and preferably the native compiler
when the circumstances admit this. The native compiler is also a good
test case for the R5900 QEMU user mode. Additionally, Gentoo is well-
known for compiling and installing its packages from sources.

This change has been tested with Gentoo compiled for R5900, including
native compilation of several packages under QEMU.

Backports commit ed4f49ba9bb56ebca6987b1083255daf6c89b5de from qemu.
2018-11-10 12:11:11 -05:00
Fredrik Noring e9a4475a35
target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU plays the role of the
kernel in user mode, so those traps are emulated by accepting the
instructions.

This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception for flagged CPUs in QEMU system mode.

The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.

Backports commit 96631327be14c4f54cc31f873c278d9ffedd1e00 from qemu
2018-11-10 12:10:01 -05:00
Fredrik Noring cb7b097204
target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.

Backports commit 5601e6217d90ed322b4b9a6d68e8db607db91842 from qemu
2018-11-10 12:08:14 -05:00
Fredrik Noring 296d8bd729
target/mips: Support R5900 DIV1 and DIVU1 instructions
Backports commit be9c42c90d162100a63111ddeb8bfe50be897873 from qemu
2018-11-10 12:07:24 -05:00
Fredrik Noring b42c8e80b8
target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions
Backports commit 8d927f7cb4b3ec06d6a7cf71221fd6a48e9a8fb5 from qemu
2018-11-10 12:06:20 -05:00
Fredrik Noring 3914d65fb9
target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions
Add support for MULT1 and MULTU1 instructions.

Backports commit 06de726b2d4da185dfec9d06b5f1032059ad3554 from qemu
2018-11-10 12:04:28 -05:00
Fredrik Noring 91cd7c20e5
target/mips: Support R5900 three-operand MULT and MULTU instructions
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.

Likewise, the R5900-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.

Backports commit 21e8e8b230af38b6bd8c953fa5f31e4a5a128e1c from qemu
2018-11-10 11:57:54 -05:00
Fredrik Noring 7da9860cf5
target/mips: Add a placeholder for R5900 MMI3 instruction subclass
Add a placeholder for MMI3 subclass.

Backports commit ec1944fc8eb862d48a0c74671105ce13acbc9c9e from qemu
2018-11-10 11:54:48 -05:00
Fredrik Noring 13d02e9aad
target/mips: Add a placeholder for R5900 MMI2 instruction subclass
Backports commit 6c1e48d38a2d26cca2d2b00f331a4ac7dbfae3ca from qemu
2018-11-10 11:52:47 -05:00
Fredrik Noring 63d9f0c6b7
target/mips: Add a placeholder for R5900 MMI1 instruction subclass
Backports commit 7a803ca23a6d6ac0d1d34469cd3f010a66cd381a from qemu
2018-11-10 11:51:47 -05:00
Fredrik Noring 685ccc52e7
target/mips: Add a placeholder for R5900 MMI0 instruction subclass
Add a placeholder for MMI0 subclass.

Backports commit 88eafe0b28c8e88ed6d38eb27dbf482f9c885745 from qemu
2018-11-10 11:50:48 -05:00
Fredrik Noring e71d43fd8d
target/mips: Add a placeholder for R5900 MMI instruction class
Add a placeholder for MMI class. This is the main palceholder for
MMI ASE.

backports commit 71b8a6b3f3d89283b094e04962c077aa01401438 from qemu
2018-11-10 11:49:19 -05:00
Fredrik Noring 496fe3ba14
target/mips: Add a placeholder for R5900 LQ
Add a placeholder for LQ instruction.

Backports commit f08099ad7a4dd32e12a3f9d4b4b04c32d7522b03 from qemu
2018-11-10 11:41:10 -05:00
Fredrik Noring cfc33249ce
target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR
Add placeholder for SQ instruction, handle RDHWR.

Backports commit bb41e74b66a8879ba5c23db145039faa27df5766 from qemu
2018-11-10 11:40:18 -05:00
Fredrik Noring 32a644a4a1
target/mips: Bunch of opcodes
Globs a bunch of MIPS commits together from qemu.
2018-11-10 11:39:20 -05:00
Fredrik Noring 5a6b86a346
target/mips: Define R5900 MMI class, and LQ and SQ opcode constants
Define MMI class, LQ, and SQ R5900 opdoces.

Backports commit f99c0d6da3424dd48ad1f0345464f63515949be6 from qemu
2018-11-10 11:32:27 -05:00
Fredrik Noring fa90149289
target/mips: Add R5900 Multimedia Instruction overview note
Add a comment on R5900 MMI ASE (short overview).

Backports commit 497f072b159effc4b19d9629e4818e6185be5776 from qemu
2018-11-10 11:30:57 -05:00
Fredrik Noring 93fb8273c8
target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants
The R5900 implements the 64-bit MIPS III instruction set except
DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV
instructions MOVN, MOVZ and PREF are implemented. It has the
R5900-specific three-operand instructions MADD, MADDU, MULT and
MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1,
MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit
multimedia instructions specific to the R5900 is also implemented.

The Toshiba TX System RISC TX79 Core Architecture manual:

https://wiki.qemu.org/File:C790.pdf

describes the C790 processor that is a follow-up to the R5900. There
are a few notable differences in that the R5900 FPU

- is not IEEE 754-1985 compliant,
- does not implement double format, and
- its machine code is nonstandard.

Backports commit 6f692818a7b53630702d25a709cd61282fd139ad from qemu
2018-11-10 11:29:25 -05:00
Richard Henderson e9fe7d3c8d
target/arm: Only flush tlb if ASID changes
Since QEMU does not implement ASIDs, changes to the ASID must flush the
tlb. However, if the ASID does not change there is no reason to flush.

In testing a boot of the Ubuntu installer to the first menu, this reduces
the number of flushes by 30%, or nearly 600k instances.

Backports commit 93f379b0c43617b1361f742f261479eaed4959cb from qemu
2018-11-10 11:26:24 -05:00
Richard Henderson 15a6b3f771
target/arm: Remove writefn from TTBR0_EL3
The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.

Backports commit f478847f1ee0df9397f561025ab2f687fd923571 from qemu
2018-11-10 11:25:39 -05:00
Richard Henderson 1bcba0737e
target/arm: Reorg NEON VLD/VST single element to one lane
Instead of shifts and masks, use direct loads and stores from
the neon register file.

Backports commit 2d6ac920837f558be214ad2ddd28cad7f3b15e5c from qemu
2018-11-10 11:24:37 -05:00
Richard Henderson 37103f1bc4
target/arm: Promote consecutive memory ops for aa32
For a sequence of loads or stores from a single register,
little-endian operations can be promoted to an 8-byte op.
This can reduce the number of operations by a factor of 8.

Backports commit e23f12b3a252352b575908ca7b94587acd004641 from qemu
2018-11-10 11:19:15 -05:00
Richard Henderson 1cab7a41ac
target/arm: Reorg NEON VLD/VST all elements
Instead of shifts and masks, use direct loads and stores from the neon
register file. Mirror the iteration structure of the ARM pseudocode
more closely. Correct the parameters of the VLD2 A2 insn.

Note that this includes a bugfix for handling of the insn
"VLD2 (multiple 2-element structures)" -- we were using an
incorrect stride value.

Backports commit ac55d00709e78cd39dfa298dcaac7aecb58762e8 from qemu
2018-11-10 11:18:45 -05:00
Richard Henderson a2239b9f5b
target/arm: Use gvec for NEON VLD all lanes
Backports commit 7377c2c97e20e64ed9b481eb2d9b9084bfd5b7e9 from qemu
2018-11-10 11:08:29 -05:00
Richard Henderson 985acb9cde
target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
Move cmtst_op expanders from translate-a64.c.

Backports commit ea580fa312674c1ba82a8b137caf42b0609ce3e3 from qemu
2018-11-10 11:03:42 -05:00
Richard Henderson 5d9c0e52bf
target/arm: Use gvec for NEON_3R_VML
Move mla_op and mls_op expanders from translate-a64.c.

Backports commit 4a7832b095b9ce97a815749a13516f5cfb3c5dd4 from qemu
2018-11-10 10:58:44 -05:00
Richard Henderson 79bbb7c730
target/arm: Use gvec for VSRI, VSLI
Move shi_op and sli_op expanders from translate-a64.c.

Backports commit f3cd8218d1d3e534877ce3f3cb61c6757d10f9df from qemu
2018-11-10 10:53:28 -05:00
Lioncash edb36c7505
target/arm: Use gvec for VSRA 2018-11-10 10:32:29 -05:00
Richard Henderson b5877f1dfb
target/arm: Use gvec for VSHR, VSHL
Backports commit 1dc8425e551be1371d657e94367f37130cd7aede from qemu
2018-11-10 10:14:31 -05:00
Lioncash 7790ca1ccb
target/arm: Use gvec for NEON_3R_VMUL 2018-11-10 10:11:10 -05:00
Richard Henderson dfdc6bc05c
target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
Backports commit 4bf940bebad273e4b3534ae3f83f2c9d1191d3a2 from qemu
2018-11-10 10:09:38 -05:00
Richard Henderson 7b4b5ac249
target/arm: Use gvec for NEON_3R_VADD_VSUB insns
Backports commit e4717ae02dd0c2e544a07302c1ed473775209aba from qemu
2018-11-10 10:08:23 -05:00
Richard Henderson 0965b9513a
target/arm: Use gvec for NEON_3R_LOGIC insns
Move expanders for VBSL, VBIT, and VBIF from translate-a64.c.

Backports commit eabcd6faa90461e0b7463f4ebe75b8d050487c9c from qemu
2018-11-10 10:06:13 -05:00
Richard Henderson 9f767248a2
target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
Backports commit 246fa4aca95e213fba10c8222dbc6bd0a9a2a8d4 from qemu
2018-11-10 09:56:30 -05:00
Richard Henderson c1251a19e1
target/arm: Use gvec for NEON VDUP
Also introduces neon_element_offset to find the env offset
of a specific element within a neon register.

Backports commit 32f91fb71f4c32113ec8c2af5f74f14abe6c7162 from qemu
2018-11-10 09:51:40 -05:00
Richard Henderson 3d5f040608
target/arm: Mark some arrays const
Backports commit 308e5636152594daa4c5597b1188d44d7266db04 from qemu
2018-11-10 09:49:25 -05:00
Richard Henderson 931b49fb06
target/arm: Promote consecutive memory ops for aa64
For a sequence of loads or stores from a single register,
little-endian operations can be promoted to an 8-byte op.
This can reduce the number of operations by a factor of 8.

Backports commit 87f9a7f0c8d5122c36743885158782c2348a6d21 from qemu
2018-11-10 09:46:04 -05:00
Richard Henderson e6707b900c
target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
Backports commit 10e0b33c676b4e8ac80d5929980f4fa6be617c5a from qemu
2018-11-10 09:41:14 -05:00
Richard Henderson 74aba4ba51
target/arm: Don't call tcg_clear_temp_count
This is done generically in translator_loop.

Backports commit 7108e255c2d95b44c9dfee8075d0d6fb391281a8 from qemu
2018-11-10 09:40:06 -05:00
Richard Henderson 9bbc412c66
target/arm: Hoist address increment for vector memory ops
This can reduce the number of opcodes required for certain
complex forms of load-multiple (e.g. ld4.16b).

Backports commit a7d8143aed2268f147cc1abfebc848ed6282a313 from qemu
2018-11-10 09:39:20 -05:00
Peter Maydell d60fe610bb
target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
For traps of FP/SIMD instructions to AArch32 Hyp mode, the syndrome
provided in HSR has more information than is reported to AArch64.
Specifically, there are extra fields TA and coproc which indicate
whether the trapped instruction was FP or SIMD. Add this extra
information to the syndromes we construct, and mask it out when
taking the exception to AArch64.

Backports commit 4be42f4013fa1a9df47b48aae5148767bed8e80c from qemu
2018-11-10 09:36:41 -05:00
Peter Maydell 075bac4d57
target/arm: Get IL bit correct for v7 syndrome values
For the v7 version of the Arm architecture, the IL bit in
syndrome register values where the field is not valid was
defined to be UNK/SBZP. In v8 this is RES1, which is what
QEMU currently implements. Handle the desired v7 behaviour
by squashing the IL bit for the affected cases:
* EC == EC_UNCATEGORIZED
* prefetch aborts
* data aborts where ISV is 0

(The fourth case listed in the v8 Arm ARM DDI 0487C.a in
section G7.2.70, "illegal state exception", can't happen
on a v7 CPU.)

This deals with a corner case noted in a comment.

Backports commit 2ed08180db096ea5e44573529b85e09b1ed10b08 from qemu
2018-11-10 09:29:13 -05:00
Peter Maydell 99516b43a3
target/arm: New utility function to extract EC from syndrome
Create and use a utility function to extract the EC field
from a syndrome, rather than open-coding the shift.

Backports commit 64b91e3f890a8c221b65c6820a5ee39107ee40f5 from qemu
2018-11-10 09:28:23 -05:00
Peter Maydell ebe442b1d4
target/arm: Implement HCR.PTW
If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.

Backports commit eadb2febf05452bd8062c4c7823d7d789142500c from qemu
2018-11-10 09:25:57 -05:00
Peter Maydell 28fcb58c69
target/arm: Implement HCR.VI and VF
The HCR_EL2 VI and VF bits are supposed to track whether there is
a pending virtual IRQ or virtual FIQ. For QEMU we store the
pending VIRQ/VFIQ status in cs->interrupt_request, so this means:
* if the register is read we must get these bit values from
cs->interrupt_request
* if the register is written then we must write the bit
values back into cs->interrupt_request

Backports commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f from qemu
2018-11-10 09:23:21 -05:00
Peter Maydell 0f0befc90a
target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
The A/I/F bits in ISR_EL1 should track the virtual interrupt
status, not the physical interrupt status, if the associated
HCR_EL2.AMO/IMO/FMO bit is set. Implement this, rather than
always showing the physical interrupt status.

We don't currently implement anything to do with external
aborts, so this applies only to the I and F bits (though it
ought to be possible for the outer guest to present a virtual
external abort to the inner guest, even if QEMU doesn't
emulate physical external aborts, so there is missing
functionality in this area).

Backports commit 636540e9c40bd0931ef3022cb953bb7dbecd74ed from qemu
2018-11-10 09:20:58 -05:00
Peter Maydell f0c9e690fb
target/arm: Implement HCR.DC
The HCR.DC virtualization configuration register bit has the
following effects:
* SCTLR.M behaves as if it is 0 for all purposes except
direct reads of the bit
* HCR.VM behaves as if it is 1 for all purposes except
direct reads of the bit
* the memory type produced by the first stage of the EL1&EL0
translation regime is Normal Non-Shareable,
Inner Write-Back Read-Allocate Write-Allocate,
Outer Write-Back Read-Allocate Write-Allocate.

Implement this behaviour.

Backports commit 9d1bab337caf2324a233e5937f415fad4ce1641b from qemu
2018-11-10 09:19:44 -05:00
Peter Maydell b9e7fa2d80
target/arm: Implement HCR.FB
The HCR.FB virtualization configuration register bit requests that
TLB maintenance, branch predictor invalidate-all and icache
invalidate-all operations performed in NS EL1 should be upgraded
from "local CPU only to "broadcast within Inner Shareable domain".
For QEMU we NOP the branch predictor and icache operations, so
we only need to upgrade the TLB invalidates:
AArch32 TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVAL, TLBIMVAAL
AArch64 TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
TLBI VALE1, TLBI VAALE1

Backports commit b4ab8ce98b8c482c8986785800f238d32a1578a9 from qemu
2018-11-10 09:17:51 -05:00
Lioncash a0358202a7
target/arm: Improve debug logging of AArch32 exception return
For AArch32, exception return happens through certain kinds
of CPSR write. We don't currently have any CPU_LOG_INT logging
of these events (unlike AArch64, where we log in the ERET
instruction). Add some suitable logging.

This will log exception returns like this:
Exception return from AArch32 hyp to usr PC 0x80100374

paralleling the existing logging in the exception_return
helper for AArch64 exception returns:
Exception return from AArch64 EL2 to AArch64 EL0 PC 0x8003045c
Exception return from AArch64 EL2 to AArch32 EL0 PC 0x8003045c

(Note that an AArch32 exception return can only be
AArch32->AArch32, never to AArch64.)

Backports commit 81e3728407bf4a12f83e14fd410d5f0a7d29b5b4 from qemu
2018-11-10 09:09:52 -05:00
Richard Henderson 03ec90f39b
target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
Backports commit 5763190fa8705863b4b725aa1657661a97113eb4 from qemu
2018-11-10 08:34:32 -05:00